Texas Instruments | 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver, TRSF3223E (Rev. A) | Datasheet | Texas Instruments 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver, TRSF3223E (Rev. A) Datasheet

Texas Instruments 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver, TRSF3223E (Rev. A) Datasheet
TRSF3223E
SLLS824A – AUGUST 2007 – REVISED SEPTEMBER 2011
www.ti.com
3-V TO 5.5-V MULTICHANNEL RS-232 LINE DRIVER/RECEIVER
WITH ±15-kV ESD PROTECTION
Check for Samples: TRSF3223E
FEATURES
1
•
•
•
•
•
•
•
•
ESD Protection for RS-232 Bus Pins
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC 61000-4-2, Contact Discharge
– ±15-kV IEC 61000-4-2, Air-Gap Discharge
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates With 3-V to 5.5-V VCC Supply
Operates up to 1000 kbit/s
Two Drivers and Two Receivers
Low Standby Current . . . 1 μA Typ
External Capacitors . . . 4 × 0.1 μF
Accepts 5-V Logic Input With 3.3-V Supply
DB, DW, OR PW PACKAGE
(TOP VIEW)
EN
C1+
V+
C1−
C2+
C2−
V−
DOUT2
RIN2
ROUT2
APPLICATIONS
The TRSF3223E consists of two line drivers, two line
receivers, and a dual charge-pump circuit with ±15-kV
ESD protection pin to pin (serial-port connection pins,
including GND). This device meets the requirements
of TIA/EIA-232-F and provides the electrical interface
between an asynchronous communication controller
and the serial-port connector. The charge pump and
four small external capacitors allow operation from a
single 3-V to 5.5-V supply. The TRSF3223E operates
at typical data signaling rates up to 1000 kbit/s.
19
3
18
4
17
5
16
6
7
15
14
8
13
9
12
10
11
FORCEOFF
VCC
GND
DOUT1
RIN1
ROUT1
FORCEON
DIN1
DIN2
INVALID
RGW PACKAGE
(TOP VIEW)
V+
EN
FORCEOFF
VCC
GND
Battery-Powered Systems
PDAs
Notebooks
Laptops
Palmtop PCs
Hand-Held Equipment
DESCRIPTION/
ORDERING INFORMATION
20
2
20 19 18 17 16
C1+
C1−
C2+
C2−
V−
15
1 DOUT1
1
2
14 RIN1
3
4
13 ROUT1
12 FORCEON
5
11 DIN1
6 7 8 9 10
DOUT2
RIN2
ROUT2
INVALID
DIN2
•
•
•
•
•
•
1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
TRSF3223E
SLLS824A – AUGUST 2007 – REVISED SEPTEMBER 2011
www.ti.com
Flexible control options for power management are available when the serial port is inactive. The
auto-powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of
operation, if the device does not sense a valid RS-232 signal, the driver outputs are disabled. If FORCEOFF is
set low and EN is high, both drivers and receivers are shut off, and the supply current is reduced to 1 mA.
Disconnecting the serial port or turning off the peripheral drivers causes auto-powerdown to occur.
Auto-powerdown can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown enabled,
the device is automatically activated when a valid signal is applied to any receiver input. The INVALID output is
used to notify the user if an RS-232 signal is present at any receiver input. INVALID is high (valid data) if any
receiver input voltage is greater than 2.7 V or less than –2.7 V, or has been between –0.3 V and 0.3 V for less
than 30 μs. INVALID is low (invalid data) if the receiver input voltage is between –0.3 V and 0.3 V for more than
30 μs. Refer to Figure 4 for receiver input levels.
Table 1. ORDERING INFORMATION
PACKAGE (1)
TA
SOIC – DW
SSOP – DB
0°C to 70°C
TSSOP – PW
SOIC – DW
SSOP – DB
–40°C to 85°C
TSSOP – PW
QFN – RGW
(1)
(2)
(2)
ORDERABLE PART NUMBER
Tube of 25
TRSF3223ECDW
Reel of 2000
TRSF3223ECDWR
Tube of 70
TRSF3223ECDB
Reel of 2000
TRSF3223ECDBR
Tube of 70
TRSF3223ECPW
Reel of 2000
TRSF3223ECPWR
Tube of 25
TRSF3223EIDW
Reel of 2000
TRSF3223EIDWR
Tube of 70
TRSF3223EIDB
Reel of 2000
TRSF3223EIDBR
Tube of 70
TRSF3223EIPW
Reel of 2000
TRSF3223EIPWR
Reel of 3000
TRSF3223EIRGWR
TOP-SIDE MARKING
TRSF3223EC
RT23EC
RT23EC
TRSF3223EI
RT23EI
RT23EI
RT23EI
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLES
ABC
Each Driver (1)
INPUTS
(1)
2
OUTPUT
DOUT
DRIVER STATUS
X
Z
Powered off
Normal operation with
auto-powerdown disabled
DIN
FORCEON
FORCEOFF
VALID RIN
RS-232 LEVEL
X
X
L
L
H
H
X
H
H
H
H
X
L
L
L
H
Yes
H
H
L
H
Yes
L
L
L
H
No
Z
H
L
H
No
Z
Normal operation with
auto-powerdown enabled
Powered off by
auto-powerdown feature
H = high level, L = low level, X = irrelevant, Z = high impedance
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TRSF3223E
SLLS824A – AUGUST 2007 – REVISED SEPTEMBER 2011
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Each Receiver (1)
INPUTS
(1)
RIN
EN
VALID RIN
RS-232 LEVEL
OUTPUT
ROUT
L
L
X
H
H
L
X
L
X
H
X
Z
Open
L
No
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off),
Open = input disconnected or connected driver off
LOGIC DIAGRAM (POSITIVE LOGIC)
DIN1
DIN2
FORCEOFF
FORCEON
EN
ROUT1
ROUT2
13
17
12
8
20
DOUT1
DOUT2
11
Powerdown
14
INVALID
1
15
16
10
9
RIN1
RIN2
Pin numbers are for the DB, DW, and PW packages.
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TRSF3223E
SLLS824A – AUGUST 2007 – REVISED SEPTEMBER 2011
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.3
6
V
V+
Positive-output supply voltage range (2)
–0.3
7
V
V–
Negative-output supply voltage range (2)
0.3
–7
V
V+ – V–
Supply voltage difference (2)
13
V
VI
Input voltage range
VO
Output voltage range
θJA
Package thermal impedance (3)
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
Driver (FORCEOFF, FORCEON, EN)
–0.3
6
Receiver
–25
25
–13.2
13.2
–0.3
VCC + 0.3
Driver
Receiver (INVALID)
(4)
DB package
70
DW package
58
PW package
(1)
(2)
(3)
(4)
V
V
°C/W
83
–65
150
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
See Figure 6
VCC = 3.3 V
Supply voltage
VCC = 5 V
VIH
Driver and control
high-level input voltage
DIN, EN, FORCEOFF, FORCEON
VIL
Driver and control
low-level input voltage
DIN, EN, FORCEOFF, FORCEON
Driver and control input voltage
DIN, EN, FORCEOFF, FORCEON
VI
TA
(1)
VCC = 3.3 V
VCC = 5 V
NOM
MAX
3
3.3
3.6
4.5
5
5.5
UNIT
V
2
V
2.4
0.8
Receiver input voltage
TRSF3223EC
Operating free-air temperature
MIN
TRSF3223EI
0
5.5
–25
25
0
70
–40
85
V
V
°C
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
II
ICC
(1)
(2)
4
Input leakage
current
Supply current
TEST CONDITIONS
MIN
EN, FORCEOFF,
FORCEON
TYP (2) MAX
UNIT
±0.01
±1
μA
0.3
1
mA
Auto-powerdown disabled
VCC = 3.3 V or 5 V, TA = 25°C,
No load, FORCEOFF and FORCEON at VCC
Powered off
No load, FORCEOFF at GND
1
10
Auto-powerdown enabled
No load, FORCEOFF at VCC, FORCEON at GND,
All RIN are open or grounded
1
10
μA
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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SLLS824A – AUGUST 2007 – REVISED SEPTEMBER 2011
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DRIVER SECTION
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
5.4
MAX
UNIT
VOH
High-level output voltage
DOUT at RL = 3 kΩ to GND
5
VOL
Low-level output voltage
DOUT at RL = 3 kΩ to GND
–5
IIH
High-level input current
VI = VCC
±0.01
±1
μA
IIL
Low-level input current
VI at GND
±0.01
±1
μA
±35
±60
mA
IOS
Short-circuit output current (3)
ro
Output resistance
IOZ
(1)
(2)
(3)
Output leakage current
–5.4
VCC = 3.6 V, VO = 0 V
VCC = 5.5 V, VO = 0 V
VCC, V+, and V– = 0 V, VO = ±2 V
V
300
V
Ω
10M
FORCEOFF = GND, VCC = 3 V to 3.6 V, VO = ±12 V
±25
FORCEOFF = GND, VCC = 4.5 V to 5.5 V, VO = ±12 V
±25
μA
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
Switching Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
CL = 1000 pF
Maximum
data rate
(see Figure 1)
RL = 3 kΩ,
One DOUT switching
tsk(p)
Pulse skew (3)
SR(tr)
Slew rate,
transition region
(see Figure 1)
(1)
(2)
(3)
MIN TYP (2) MAX
TEST CONDITIONS
250
CL = 250 pF,
VCC = 3 V to 4.5 V
1000
CL = 1000 pF,
VCC = 4.5 V to 5.5 V
1000
CL = 150 pF to 2500 pF,
RL = 3 kΩ to 7 kΩ,
See Figure 2
RL = 7 kΩ,
CL = 150 pF to 1000 pF
RL = 3 kΩ
UNIT
kbit/s
300
8
ns
90
CL = 1000 pF
12
60
CL = 150 pF to 250 pF
24
150
V/μs
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
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RECEIVER SECTION
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOL = 1.6 mA
TYP (2)
VCC – 0.6
VCC – 0.1
MAX
0.4
1.6
2.4
VCC = 5 V
1.9
2.4
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input hysteresis (VIT+ – VIT–)
IOZ
Output leakage current
EN = VCC
ri
Input resistance
VI = ±3 V to ±25 V
VCC = 3.3 V
0.6
1.1
VCC = 5 V
0.6
1.4
UNIT
V
VCC = 3.3 V
VIT+
(1)
(2)
MIN
TEST CONDITIONS
V
V
V
0.5
V
±0.05
μA
5
kΩ
3
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Switching Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (2)
UNIT
tPLH
Propagation delay time, low- to high-level output
CL = 150 pF, See Figure 3
150
ns
tPHL
Propagation delay time, high- to low-level output
CL = 150 pF, See Figure 3
150
ns
ten
Output enable time
CL = 150 pF, RL = 3 kΩ, See Figure 4
200
ns
tdis
Output disable time
CL = 150 pF, RL = 3 kΩ, See Figure 4
200
ns
tsk(p)
Pulse skew (3)
See Figure 3
50
ns
(1)
(2)
(3)
6
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
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AUTO-POWERDOWN SECTION
Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
MIN
VT+(valid)
Receiver input threshold for
INVALID high-level output voltage
FORCEON = GND,
FORCEOFF = VCC
VT–(valid)
Receiver input threshold for
INVALID high-level output voltage
FORCEON = GND,
FORCEOFF = VCC
–2.7
VT(invalid)
Receiver input threshold for
INVALID low-level output voltage
FORCEON = GND,
FORCEOFF = VCC
–0.3
VOH
INVALID high-level output voltage
IOH = 1 mA,
FORCEOFF = VCC
FORCEON = GND,
VOL
INVALID low-level output voltage
IOL = 1.6 mA,
FORCEOFF = VCC
FORCEON = GND,
MAX
UNIT
2.7
V
V
0.3
V
VCC – 0.6
V
0.4
V
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TYP (1)
UNIT
tvalid
Propagation delay time, low- to high-level output
1
μs
tinvalid
Propagation delay time, high- to low-level output
30
μs
ten
Supply enable time
100
μs
(1)
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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PARAMETER MEASUREMENT INFORMATION
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 Ω
RL
1.5 V
0V
CL
(see Note A)
tTHL
3V
FORCEOFF
tTLH
VOH
3V
3V
Output
−3 V
−3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr) +
t
THL
6V
or t
TLH
Figure 1. Driver Slew Rate
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPLH
tPHL
VOH
3V
FORCEOFF
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Driver Pulse Skew
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
EN
0V
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
50 Ω
tPHL
CL
(see Note A)
tPLH
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. Receiver Propagation Delay Times
8
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
GND
S1
RL
3 V or 0 V
Output
CL
(see Note A)
EN
3V
Input
1.5 V
0V
tPZH
(S1 at GND)
tPHZ
(S1 at GND)
VOH
Output
50%
0.3 V
Generator
(see Note B)
1.5 V
50 Ω
tPLZ
(S1 at VCC)
0.3 V
Output
50%
VOL
tPZL
(S1 at VCC)
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 4. Receiver Enable and Disable Times
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
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PARAMETER MEASUREMENT INFORMATION (continued)
2.7 V
2.7 V
EN
0V
Receiver
Input
0V
50 Ω
VCC
INVALID
Output
50% V CC
0V
ten
≈V+
V+
0.3 V
VCC
0V
0.3 V
Supply
Voltages
FORCEOFF
FORCEON
50% V CC
INVALID
CL = 30 pF
(see Note A)
DIN
DOUT
≈V−
V−
TEST CIRCUIT
−3 V
tvalid
tinvalid
AutoPowerdown
2.7 V
−2.7 V
ROUT
Generator
(see Note B)
3V
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
VOLTAGE WAVEFORMS
Valid RS-232 Level, INVALID High
2.7 V
Indeterminate
0.3 V
If Signal Remains Within This Region
for More Than 30 ms, INVALID Is Low †
0V
0.3 V
Indeterminate
2.7 V
Valid RS-232 Level, INVALID High
†
Auto-powerdown disables drivers
reduces supply current to 1 µA
and
Figure 5. INVALID Propagation Delay Times and Supply Enabling Time
10
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APPLICATION INFORMATION
1
EN
2
20
AutoPowerdown
VCC
C1+
FORCEOFF
19
CBYPASS
+
3
C1
V+
GND
18
= 0.1mF
C3 †
4
5
17
C1
16
C2+
DOUT1
RIN1
+
C2
6
15
C2
ROUT1
5 kΩ
7
C4
FORCEON
+
8
13
9
12
10
11
DOUT2
RIN2
ROUT2
14
V
DIN1
DIN2
INVALID
5 kΩ
† C3 can be connected to V
CC or GND.
NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
VCC vs CAPACITOR VALUES
VCC
3.3 V " 0.3 V
C1
0.1 µF
C2, C3, and C4
0.1 µF
5 V " 0.5 V
0.047 µF
0.33 µF
3 V to 5.5 V
0.1 µF
0.47 µF
Figure 6. Typical Operating Circuit and Capacitor Values
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REVISION HISTORY
Changes from Original (August 2007) to Revision A
Page
•
Added RGW package to datasheet. ..................................................................................................................................... 1
•
Deleted RHL package from datasheet. ................................................................................................................................. 1
12
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TRSF3223ECDBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RT23EC
TRSF3223ECPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RT23EC
TRSF3223EIDBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RT23EI
TRSF3223EIDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRSF3223EI
TRSF3223EIPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RT23EI
TRSF3223EIPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RT23EI
TRSF3223EIRGWR
ACTIVE
VQFN
RGW
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
RT23EI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
12.0
16.0
Q1
TRSF3223ECDBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
TRSF3223ECPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TRSF3223EIDBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
TRSF3223EIDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
TRSF3223EIPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TRSF3223EIRGWR
VQFN
RGW
20
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TRSF3223ECDBR
SSOP
DB
20
2000
367.0
367.0
38.0
TRSF3223ECPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TRSF3223EIDBR
SSOP
DB
20
2000
367.0
367.0
38.0
TRSF3223EIDWR
SOIC
DW
20
2000
367.0
367.0
45.0
TRSF3223EIPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TRSF3223EIRGWR
VQFN
RGW
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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