Texas Instruments | 11.3-Gbps Limiting Transimpedance Amplifier with RSSI (Rev. B) | Datasheet | Texas Instruments 11.3-Gbps Limiting Transimpedance Amplifier with RSSI (Rev. B) Datasheet

Texas Instruments 11.3-Gbps Limiting Transimpedance Amplifier with RSSI (Rev. B) Datasheet
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
11.3 Gbps Limiting Transimpedance Amplifier With RSSI
Check for Samples: ONET8501T
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
10 GHz Bandwidth
7 kΩ Differential Small Signal Transimpedance
2.5 mAPP Input Overload Current
Received Signal Strength Indication (RSSI)
100mW Typical Power Dissipation
CML Data Outputs With On-Chip 50Ω
Back-Termination
On Chip Supply Filter Capacitor
Single 3.3V Supply
Die Size: 940 × 1195 μm
SONET OC-192
SFP+ Optical Receivers
10x Fibre Channel Optical Receivers
10G Ethernet Receivers
PIN Preamplifier-Receivers
APD Preamplifier Receivers
DESCRIPTION
The ONET8501T is a high-speed, high gain, limiting transimpedance amplifier used in optical receivers with data
rates up to 12.5Gbps. It features low input referred noise, 10GHz bandwidth, 7kΩ small signal transimpedance,
and a received signal strength indicator (RSSI).
The ONET8501T is available in die form, includes an on-chip VCC bypass capacitor and is optimized for
packaging in a TO can.
The ONET8501T requires a single 3.3V ±10% supply and its power efficient design typically dissipates less than
105mW. The device is characterized for operation from –40°C to 100°C case (IC back side) temperature.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
A simplified block diagram of the ONET8501T is shown in Figure 1.
The ONET8501T consists of the signal path, supply filters, a control block for dc input bias, automatic gain
control (AGC) and received signal strength indication (RSSI). The RSSI provides the bias for the TIA stage and
the control for the AGC.
The signal path consists of a transimpedance amplifier stage, a voltage amplifier, and a CML output buffer. The
on-chip filter circuit provides a filtered VCC for the PIN photodiode and for the transimpedance amplifier.
The DC input bias circuit and automatic gain control use internal low pass filters to cancel the dc current on the
input and to adjust the transimpedance amplifier gain. Furthermore, circuitry to monitor the received signal
strength is provided.
VCC_OUT
To Voltage Amplifier and Output Buffer
To TIA
VCC_IN
GND
220 W
FILTER1/2
RSSI_IB
AGC and DC
Offset
Cancellation
RF
OUT+
IN
OUTTIA
Voltage Amplifier
CML Output Buffer
RSSI_EB
Figure 1. Simplified Block Diagram of the ONET8501T
2
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
BOND PAD ASSIGNMENT
GND
GND
GND
GND
GND
GND
The ONET8501T is available in die form. The locations of the bondpads are shown in Figure 2.
T8501
19 18 17 16 15 14
13
GND
OUT+
1
12
OUT-
VCC_OUT
2
11
NC
10
RSSI_EB
9
RSSI_IB
4
5
6
7
8
FILTER1
IN
FILTER2
GND
3
GND
VCC_IN
Figure 2. Bond Pad Assignment of ONET8501T
PIN FUNCTIONS
PIN
NAME
TYPE
DESCRIPTION
NO.
GND
4, 8,
13–19
Supply
Circuit ground. All GND pads are connected on die. Bonding all pads is optional; however, for
optimum performance a good ground connection is mandatory.
OUT+
1
Analog
output
Non-inverted CML data output. On-chip 50Ω back-terminated to VCC.
VCC_OUT
2
Supply
2.97V–3.63V supply voltage for the voltage and CML amplifiers.
VCC_IN
3
Supply
2.97V–3.63V supply voltage for input TIA stage.
FILTER
5, 7
Analog
Bias voltage for photodiode cathode. These pads are internally connected to an 220Ω resistor to
VCC and a filter capacitor to ground (GND).
6
Analog input
10
Analog
output
Optional use when operated with external PD bias (e.g. APD). Analog output current proportional to
the input data amplitude. Indicates the strength of the received signal (RSSI).Connected to an
external resistor to ground (GND). For proper operation, ensure that the voltage at the RSSI pad
does not exceed VCC – 0.65V. If the RSSI feature is not used this pad should be left open.
RSSI_IB
9
Analog
output
Analog output current proportional to the input data amplitude. Indicates the strength of the received
signal (RSSI) if the photo diode is biased from the TIA. Connected to an external resistor to ground
(GND). For proper operation, ensure that the voltage at the RSSI pad does not exceed VCC –
0.65V. If the RSSI feature is not used this pad should be left open.
OUT–
12
Analog
output
Inverted CML data output. On-chip 50Ω back-terminated to VCC.
IN
RSSI_EB
Data input to TIA (photodiode anode).
Copyright © 2008–2011, Texas Instruments Incorporated
3
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
VI
II
IO
ESD
TJ
(1)
(2)
(2)
at VCC_IN, VCC_OUT
VALUE
UNIT
–0.3 to 4.0
V
Voltage at FILTER1, FILTER2, OUT+, OUT–, RSSI_IB, RSSI_EB (2)
–0.3 to 4.0
V
Current into IN
–0.7 to 3.5
mA
Current into FILTER1, FILTER2
–8 to 8
mA
Continuous current at outputs at OUT+, OUT-
–8 to 8
mA
ESD rating at all pins except input IN, RSSI_IB, and RSSI_EB
2
kV (HBM)
ESD rating at RSSI_IB and RSSI_EB
1
kV(HBM)
ESD rating at input IN
0.5
kV(HBM)
Maximum junction temperature
125
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
VCC
Supply voltage
PARAMETER
2.97
3.3
3.63
V
TA
Operating backside die temperature
–40
100 (1)
°C
L
Wire-bond inductor at pins FILTER and IN
0.3
0.5
nH
CPD
Photodiode Capacitance
0.2
(1)
CONDITIONS
UNIT
pF
105°C maximum junction temperature
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted). Typical values are at VCC = 3.3 V and TA = 25°C
PARAMETER
VCC
ICC
Supply current
VIN
Input bias voltage
R(OUT)
Output resistance
R(FILTER)
Photodiode filter resistance
(1)
4
CONDITIONS
Supply voltage
Input current IIN < 1500 μAPP
MIN
TYP
MAX
UNIT
2.97
3.3
3.63
V
28
(1)
21
Single-ended to VCC
41
44 (1)
Input current IIN < 2500 μAPP
mA
0.75
0.85
0.98
V
40
50
60
Ω
220
Ω
Including RSSI current
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted). Typical values are at VCC = +3.3 V and TA = 25°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
5,000
7,000
10,000
7
10
UNIT
Z
Small signal transimpedance
Differential output; Input current IIN = 20 μAPP
f(HSS,3dB)
Small signal bandwidth
iIN = 16 μAPP
f(L,3dB)
Low frequency –3 dB bandwidth
16 μA < IIN < 2000 μAPP
30
100
kHz
i(N,IN)
Input referred RMS noise
10 GHz bandwidth (2)
0.9
1.6
μA
Unstressed sensitivity
10.3125 Gbps, PRBS31 pattern,
850 nm, BER 10–12
–14
S(US)
DJ
Deterministic jitter
(1)
Ω
GHz
dBm
16 μAPP < IIN < 500 μAPP
(10.3125 Gbps, PRBS31 pattern)
6
11
500 μAPP < IIN < 2000 μAPP
(10.3125 Gbps, PRBS31 pattern)
6
13
6
15
psPP
psPP
DJ(OL)
Overload deterministic jitter
2000 μAPP < IIN < 2500 μAPP
(K28.5 pattern)
VOUT,D,MAX
Maximum differential output voltage
Input current IIN = 200 μAPP
240
280
350
mVPP
ARSSI_IB
RSSI gain internal bias
Resistive load to GND (3)
0.48
0.5
0.52
A/A
3.5
10
16
μA
0.6
A/A
RSSI internal bias output offset current
(no light) (4)
ARSSI_EB
RSSI gain external bias
Resistive load to GND
(3)
RSSI external bias output offset current
(no light)
PSNR
(1)
(2)
(3)
(4)
(5)
Power supply noise rejection
(5)
F < 10 MHz , supply filtering according to SFF8431
0.43
25
μA
–15
dB
The small signal bandwidth is specified over process corners, temperature, and supply voltage variation. The assumed photodiode
capacitance is 0.2 pF and the bond-wire inductance is 0.3 nH. The small signal bandwidth strongly depends on environmental parasitics.
Careful attention to layout parasitics and external components is necessary to achieve optimal performance.
Input referred RMS noise is (RMS output noise)/ (gain at 100 MHz).
The RSSI output is a current output, which requires a resistive load to ground (GND). The voltage gain can be adjusted for the intended
application by choosing the external resistor; however, for proper operation, ensure that the voltage at RSSI does not exceed
VCC – 0.65V.
Offset is added to improve accuracy below 5μA. When measured without input current (no light) the offset can be subtracted as a
constant offset from RSSI measurements.
PSNR is the differential output amplitude divided by the voltage ripple on supply; no input current at IN.
Copyright © 2008–2011, Texas Instruments Incorporated
5
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
DETAILED DESCRIPTION
SIGNAL PATH
The first stage of the signal path is a transimpedance amplifier which converts the photodiode current into a
voltage. If the input signal current exceeds a certain value, the transimpedance gain is reduced by means of a
nonlinear AGC circuit to limit the signal amplitude.
The second stage is a limiting voltage amplifier that provides additional limiting gain and converts the single
ended input voltage into a differential data signal. The output stage provides CML outputs with an on-chip 50Ω
back-termination to VCC.
FILTER CIRCUITRY
The FILTER pins provide a filtered VCC for a PIN photodiode bias. The on-chip low pass filter for the photodiode
is implemented using a filter resistor of 220Ω and a capacitor. The corresponding corner frequency is below
5MHz. The supply voltages for the transimpedance amplifier are filtered by means of on-chip capacitors, thus
avoiding the necessity to use an external supply filter capacitor. The input stage has a separate VCC supply
(VCC_IN) which is not connected on chip to the supply of the limiting and CML stages (VCC_OUT).
AGC AND RSSI
The voltage drop across the internal photodiode supply-filter resistor is monitored by the bias and RSSI control
circuit block in the case where a PIN diode is biased using the FILTER pins.
If the dc input current exceeds a certain level then it is partially cancelled by means of a controlled current
source. This keeps the transimpedance amplifier stage within sufficient operating limits for optimum performance.
The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of
the complete amplifier.
Finally this circuit block senses the current through the filter resistor and generates a mirrored current that is
proportional to the input signal strength. The mirrored current is available at the RSSI_IB output and can be sunk
to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSI_IB pad
does not exceed VCC – 0.65V.
If an APD or PIN photodiode is used with an external bias then the RSSI_EB pin should be used. However, for
greater accuracy under external photo diode biasing conditions, it is recommended to derive the RSSI from the
external bias circuitry.
6
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
TYPICAL OPERATION CHARACTERISTICS
Typical Operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
TRANSIMPEDANCE
vs
INPUT CURRENT
SMALL SIGNAL TRANSIMPENDANCE
vs
AMBIENT TEMPERATURE
8
9000
7
8000
7000
Transimpedance - W
Transimpedance - kW
6
5
4
3
2
6000
5000
4000
3000
2000
1
1000
0
0
200
400
600
800
IIN - Input Current - mAPP
0
-40
1000
-20
0
20
40
60
80
TA - Ambient Temperature - °C
Figure 3.
Figure 4.
SMALL SIGNAL TRANSFER
CHARACTERISTICS
SMALL SIGNAL BANDWIDTH
vs
AMBIENT TEMPERATURE
36
20
33
18
30
100
16
27
14
Bandwidth - GHz
Gain - dB
24
21
18
15
12
12
10
8
6
9
4
6
2
3
0
0.1
1
10
f - Frequency - GHz
Figure 5.
Copyright © 2008–2011, Texas Instruments Incorporated
100
0
-40
-20
0
20
40
60
80
TA - Ambient Temperature - °C
100
Figure 6.
7
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical Operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
OUTPUT VOLTAGE
vs
INPUT CURRENT
DETERMINISTIC JITTER
vs
INPUT CURRENT
10
250
8
Deterministic Jitter - ps
Differential Output Voltage - mVPP
300
200
150
100
0
0
200
400
600
800
IIN - Input Current - mAPP
1000
0
Figure 8.
RSSI_IB OUTPUT CURRENT
vs
AVERAGE INPUT CURRENT
POWER SUPPLY NOISE REJECTION
vs
FREQUENCY
0
PSNR - Power Supply Noise Rejection - dB
900
800
700
600
500
400
300
200
100
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
IIN - Input Current - mAPP
Figure 7.
1000
RSSI_IB Output Current - mA
4
2
50
0
200
400
600
800
Average Input Current - mA
Figure 9.
8
6
1000
1200
-5
-10
-15
-20
-25
-30
0
1
2
3
4
5
6
7
f - Frequency - MHz
8
9
10
Figure 10.
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical Operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 20 μAPP INPUT CURRENT
60 mVdiv
15.6 ps/div
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 100 μAPP INPUT CURRENT
15.6 ps/div
100 mV/div
Figure 11.
Figure 12.
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 500 μAPP INPUT CURRENT
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 2 mAPP INPUT CURRENT
100 mV/div
15.6 ps/div
Figure 13.
Copyright © 2008–2011, Texas Instruments Incorporated
100 mV/div
15.6 ps/div
Figure 14.
9
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
APPLICATION INFORMATION
Figure 15 shows the ONET8501T used in a typical fiber optic receiver using the internal photodiode bias. The
ONET8501T converts the electrical current generated by the PIN photodiode into a differential output voltage.
The FILTER inputs provide a dc bias voltage for the PIN that is low pass filtered by the combination of an internal
220Ω resistor and a capacitor. Because the voltage drop across the 220Ω resistor is sensed and used by the
bias circuit, the photodiode must be connected to the FILTER pads for the bias to function correctly.
The RSSI output is used to mirror the photodiode output current and can be connected via a resistor to GND.
The voltage gain can be adjusted for the intended application by choosing the external resistor; however, for
proper operation of the ONET8501T, ensure that the voltage at RSSI never exceeds VCC – 0.65V. If the RSSI
output is not used while operating with internal PD bias, it should be left open.
The OUT+ and OUT– pins are internally terminated by 50Ω pull-up resisters to VCC. The outputs must be ac
coupled, for example by using 0.1μF capacitors, to the succeeding device.
VCC_OUT
OUT+
0.1 mF
VCC_IN
3
2
1
4
5
19
220 W
18
17
6
16
7
15
14
8
9
10
11
12
13
0.1 mF
OUTRSSI
RRSSI
GND
Figure 15. Basic Application Circuit for PIN Receivers
10
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
Figure 16 shows the ONET8501T being used in a typical fiber optic receiver using an external photodiode bias
for an APD photodiode. This configuration can also be used for a PIN diode if desired. The external bias RSSI
signal is based on a dc offset value and is not as accurate as the internal bias RSSI signal which is based upon
the photodiode current.
OUT+
VCC_OUT
0.1 mF
VCC_IN
3
2
1
4
5
19
220 W
18
17
6
APD_BIAS
16
7
15
14
8
9
10
11
12
13
0.1 mF
OUT-
GND
Figure 16. Basic Application Circuit for APD Receivers
ASSEMBLY RECOMMENDATIONS
Careful attention to assembly parasitics and external components is necessary to achieve optimal performance.
Recommendations that optimize performance include:
1. Minimize the total capacitance on the IN pad by using a low capacitance photodiode and paying attention to
stray capacitances. Place the photodiode close to the ONET8501T die in order to minimize the bond wire
length and thus the parasitic inductance.
2. Use identical termination and symmetrical transmission lines at the ac coupled differential output pins OUT+
and OUT–.
3. Use short bond wire connections for the supply terminals VCC_IN, VCC_OUT and GND. Supply voltage
filtering is provided on chip but filtering may be improved by using an additional external capacitor.
Copyright © 2008–2011, Texas Instruments Incorporated
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ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
T8501
CHIP DIMENSIONS AND PAD LOCATIONS
19
17
18
15
16
14
1195 mm
13
1
12
2
11
10
9
y
3
5
4
6
7
8
940 mm
Origin
0.0
x
Die Thickness: 203 ± 13 μm
Pad Dimensions: 105 × 65 μm
Die Size: 940 ± 40 μm × 1195 ± 40 μm
PAD
12
COORDINATES
(based on typical die size)
SYMBOL
TYPE
DESCRIPTION
x (μm)
y (μm)
1
116
739
OUT+
Analog output
Non-inverted data output
2
116
575
VCC_OUT
Supply
3.3V supply voltage
3
116
289
VCC_IN
Supply
3.3V supply voltage
4
243
136
GND
Supply
Circuit ground
5
358
136
FILTER1
Analog
Bias voltage for photodiode
6
473
136
IN
Analog input
Data input to TIA
7
588
136
FILTER2
Analog
Bias voltage for photodiode
8
703
136
GND
Supply
Circuit ground
9
828
289
RSSI_IB
Analog output
RSSI output signal for internally biased receivers
10
828
404
RSSI_EB
Analog output
RSSI output signal for externally biased receivers
11
828
575
NC
12
828
739
OUT–
Analog output
Inverted data output
13
828
910
GND
Supply
Circuit ground
14
760
1063
GND
Supply
Circuit ground
15
645
1063
GND
Supply
Circuit ground
16
530
1063
GND
Supply
Circuit ground
17
415
1063
GND
Supply
Circuit ground
18
300
1063
GND
Supply
Circuit ground
19
185
1063
GND
Supply
Circuit ground
Not connected
Copyright © 2008–2011, Texas Instruments Incorporated
ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
TO46 LAYOUT EXAMPLE
An example for a layout (top view) in a 5 pin TO46 can is shown in Figure 17.
OUT+
OUT-
VCC
RSSI
Figure 17. TO46 5 Pin Layout Using the ONET8501T With Dual Cathode PIN Diode
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ONET8501T
SLLS884B – FEBRUARY 2008 – REVISED AUGUST 2011
www.ti.com
REVISION HISTORY
Changes from Original (February 2008) to Revision A
Page
•
Changed Features bullet From: Die Size 945 x 1200 μm To: Die Size: 940 × 1195 μm ..................................................... 1
•
Changed the CHIP DIMENSIONS AND PAD LOCATIONS image. Y = 1200 µm To: 1195 µm and X = 945 µm To:
940 µm ................................................................................................................................................................................ 12
•
Added Die Thickness, Pad Dimensions, and Die Size ....................................................................................................... 12
Changes from Revision A (January 2010) to Revision B
Page
•
Changed From: Die Size: 940 ± 20 μm × 1195 ± 20 μm To: Die Size: 940 ± 40 μm × 1195 ± 40 μm .............................. 12
•
Changed the Coordinates column to include " (based on typical die size)" ....................................................................... 12
14
Copyright © 2008–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ONET8501TY
ACTIVE
DIESALE
Y
0
1800
TBD
Call TI
Call TI
-40 to 100
ONET8501TYS
ACTIVE
DIESALE
Y
0
1
TBD
Call TI
Call TI
-40 to 100
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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