Texas Instruments | 2.5 Gbps 2-to-1 DVI/HDMI Switch, TMDS251 (Rev. A) | Datasheet | Texas Instruments 2.5 Gbps 2-to-1 DVI/HDMI Switch, TMDS251 (Rev. A) Datasheet

Texas Instruments 2.5 Gbps 2-to-1 DVI/HDMI Switch, TMDS251 (Rev. A) Datasheet
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
2.5 Gbps 2-TO-1 DVI/HDMI SWITCH
Check for Samples: TMDS251
FEATURES
1
•
•
•
•
•
•
•
Compatible with HDMI 1.3a
Supports 2.5 Gbps Signaling Rate for 480i/p,
720i/p, and 1080i/p Resolutions up to 12-Bit
Color Depth
Integrated Switchable Receiver Termination
Selectable Receiver Equalization to
Accommodate to Different Input Cable
Lengths
Intra-Pair Skew < 40 ps
Inter-Pair Skew < 65 ps
HBM ESD Protection Exceeds 8 kV to TMDS
Inputs
•
•
•
•
•
•
•
3.3-V Fixed Supply to TMDS I/Os
5-V Fixed Supply to HPD, DDC, and Source
Selection Circuits
64-Pin TQFP Package
Footprint Compatible with 3-to-1 Switch
TMDS351 with Port 3 Disabled
ROHS Compatible and 260°C Reflow Rated
TMDS250 is Available with Port 1 Disabled and
Ports 2 and 3 Enabled
Supports 5-V to 3.3-V Level Shifting on DDC
Links
APPLICATIONS
•
•
Digital TV
Digital Projector
DESCRIPTION
The TMDS251 is a 2-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that
allows up to 2 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug
detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports
signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.
The input port is enabled by configuring source selectors, S1 and S2. When an input port is selected, the TMDS
inputs are connected to the TMDS outputs through a 2-to-1 multiplexer, the MOSFET between the input DDC
channel and the output DDC channel is turned on, and the HPD output follows the state of the HPD_SINK. The
other input port is inactive with disconnected input terminations, disconnected TMDS inputs to the outputs,
disconnected DDC inputs to the outputs, and the HPD outputs are low state. Check the source selection look up
table for the details of port selections.
When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with
standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs
are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process.
Termination resistors (50-Ω), pulled up to VCC, are integrated at each TMDS receiver input. External terminations
are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the
differential output voltage to be compliant with the TMDS standard.
Typical Application
DVD Player
STB
Digital TV
TMDS251
2-to-1
PHY SX
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
The TMDS251 provides two levels of receiver input equalization for different ranges of cable lengths. Each
TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the
input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in
long range HDMI cables. The TMDS251 supports power saving operation. When a system is under standby
mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, VCC, can be
powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits. The
HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, VDD, to maintain the system
hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The
device is characterized for operation from 0°C to 70°C.
2
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
EQ
Vcc
RINT
RINT
A14
B14
TMDS
Rx
Vcc
RINT
Y3
Vcc
TMDS
Driver
RINT
A12
A11
Z4
TMDS
Rx
RINT
B12
Y4
TMDS
Driver
RINT
A13
B13
2-to-1
MUX
Z3
TMDS
Rx
Vcc
RINT
Y2
RINT
TMDS
Driver
TMDS
Rx
B11
Z2
Vcc
A24
B24
RINT
Y1
RINT
TMDS
Driver
TMDS
Rx
Z1
Vcc
RINT
VSADJ
RINT
A23
B23
TMDS
Rx
Vcc
RINT
RINT
A22
B22
TMDS
Rx
Vcc
RINT
RINT
A21
B21
TMDS
Rx
HPD1
HPD2
S1
S2
Control
Logic
HPD_SINK
SCL1
SDA1
SCL2
SDA2
Copyright © 2007–2011, Texas Instruments Incorporated
SCL_SINK
SDA_SINK
HPD/DDC
Power Supply
VDD
3
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
49
50
51
52
53
54
A14
47
3
46
4
45
5
44
B14
Vcc
A13
B13
GND
A12
6
43
TMDS251
7
42
8
41
64-pin TQFP
9
40
B11
SCL1
SDA1
HPD1
EQ
S2
32
31
30
29
28
B12
Vcc
A11
Y1
Z1
GND
SCL_SINK
SDA_SINK
HPD_SINK
S1
27
33
26
34
16
25
35
15
24
36
14
23
13
22
37
21
38
12
20
39
11
19
10
Y4
Z4
Vcc
Y3
Z3
GND
Y2
Z2
Vcc
4
55
56
57
58
59
60
61
62
48
2
17
NC
Vcc
NC
NC
GND
VSADJ
1
18
NC
NC
GND
NC
NC
Vcc
NC
NC
GND
NC
63
64
NC
A24
B24
Vcc
A23
B23
GND
A22
B22
Vcc
A21
B21
SCL2
SDA2
HPD2
VDD
PAG PACKAGE
(TOP VIEW)
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
PIN FUNCTIONS
PIN
NAME
I/O
NO.
DESCRIPTION
A11, A12, A13, A14
39, 42, 45, 48
I
Source port 1 TMDS positive inputs
A21, A22, A23, A24
54, 57, 60, 63
I
Source port 2 TMDS positive inputs
B11, B12, B13, B14
38, 41, 44, 47
I
Source port 1 TMDS negative inputs
B21, B22, B23, B24
53, 56, 59, 62
I
Source port 2 TMDS negative inputs
Y1, Y2, Y3, Y4
26,23,20,17
O
Sink port TMDS positive outputs
Z1, Z2, Z3, Z4
27,24,21,18
O
Sink port TMDS negative outputs
SCL1
37
I/O
Source port 1 DDC I2C clock line
SDA1
36
I/O
Source port 1 DDC I2C data line
SCL2
52
I/O
Source port 2 DDC I2C clock line
SDA2
51
I/O
Source port 2 DDC I2C data line
SCL_SINK
29
I/O
Sink port DDC I2C clock line
SDA_SINK
30
I/O
Sink port DDC I2C data line
HPD1
35
O
Source port 1 hot plug detector output (status pin)
HPD2
50
O
Source port 2 hot plug detector output (status pin)
HPD_SINK
31
I
Sink port hot plug detector input (status pin)
32, 33
I
Source selector
EQ
34
I
TMDS Input equalization selector (control pin)
EQ = Low – HDMI 1.3 compliant cable
EQ = High – 10m 28 AWG HDMI cable
VSADJ
16
I
TMDS compliant voltage swing control (control pin)
VDD
49
VCC
6, 12, 19, 25, 40,
46, 55, 61
Power supply
GND
3, 9, 15, 22, 28,
43, 58
Ground
S1, S2
HPD/DDC Power supply
1, 2, 4, 5, 7, 8,
10, 11, 13, 14, 64
NC
No connect: these pins should be left floating
Table 1. Source Selection Lookup (1)
CONTROL BITS
(1)
I/O SELECTED
HOT PLUG DETECT STATUS
S2
S1
Y/Z
SCL_SINK
SDA_SINK
H
H
A1/B1
Terminations of A2/B2 are
disconnected
SCL1
SDA1
HPD_SINK
L
H
L
A2/B2
Terminations of A1/B1 are
disconnected
SCL2
SDA2
L
HPD_SINK
L
L
Disallowed (indeterminate)
State
All terminations are
disconnected
L
L
L
H
None (Z)
All terminations are
disconnected
HPD_SINK
HPD_SINK
None (Z)
Are pulled HIGH by
external pull-up
termination
HPD1
HPD2
H: Logic high; L: Logic low; X: Don't care; Z: High impedance
Copyright © 2007–2011, Texas Instruments Incorporated
5
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TMDS Input Stage
TMDS Output Stage
VCC
VCC
Y
Z
50 W
50 W
A
B
10 mA
Control Input Stage
Status and Source Selector
VDD
VCC
HPD_SINK
S1
S2
EQ
DDC Pass Gate
HPD Output Stage
VDD
VDD
HPD1
HPD2
6
SCL/SDA
Source
SCL/SDA
Sink
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
TMDS251PAGR
TMDS251
64-PIN TQFP Tape/Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage
range (2)
–0.5 V to 6 V
VDD
Anm
Voltage range
–0.5 V to 4 V
VCC
(3)
, Bnm
2.5 V to 4 V
Ym, Zm, VSADJ, EQ
–0.5V to 4 V
SCLn, SCL_SINK, SDAn, SDA_SINK, HPDn, HPD_SINK, S1, S2
–0.5 V to 6 V
Human body model (4)
Electrostatic
discharge
Anm, Bnm, Ym, Zm
±8000 V
All pins
±4000 V
Charged-device model (5) (all pins)
±1500 V
(6)
±200 V
Machine model
(all pins)
See Dissipation Rating
Table
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
(6)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
n = 1, 2; m = 1, 2, 3, 4
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
Low-K
1111 mW
11.19 mW/°C
611 mW
High-K
1492 mW
14.92
820 mW
64-TQFP PAG
(1)
DERATING FACTOR
ABOVE TA = 25°C
(1)
PCB JEDEC
STANDARD
TA = 70°C
POWER RATING
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
RθJB
Junction-to-board thermal
resistance
33.4
°C/W
RθJC
Junction- to-case thermal
resistance
15.6
°C/W
PD
Device power dissipation
TJ
Junction Temperature
(1)
VIH = VCC, VIL = VCC - 0.6 V, RT = 50 Ω, AVCC = 3.3V,
Am/Bm(2:4) = 2.5-Gbps HDMI data pattern,
Am/Bm(1) = 250-MHz clock
590
0
750
mW
125
°C
The maximum rating is simulation under 3.6-V VCC, 5.5-V VDD, and 600 mV VID.
Copyright © 2007–2011, Texas Instruments Incorporated
7
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage
VDD
Standby supply voltage
TA
Operating free-air temperature
MIN
NOM
MAX
3
3.3
3.6
UNIT
4.5
5
5.5
V
0
70
°C
V
TMDS DIFFERENTIAL PINS
VIC
Input common mode voltage
VCC–0.4
VCC+0.01
VID
Receiver peak-to-peak differential input voltage
150
1560
mVp-p
RVSADJ
Resistor for TMDS compliant voltage swing range
3.66
4.02
4.47
kΩ
AVCC
TMDS output termination voltage, see Figure 1
3
3.3
3.6
V
RT
Termination resistance, see Figure 1
45
50
55
Ω
0
2.5
Gbps
Signaling rate
V
CONTROL PINS
VIH
LVTTL High-level input voltage
2
VCC
V
VIL
LVTTL Low-level input voltage
GND
0.8
V
GND
VDD
V
DDC I/O PINS
VI(DDC)
DDC Input voltage
STATUS and SOURCE SELECTOR PINS
VIH
LVTTL High-level input voltage
2
VDD
V
VIL
LVTTL Low-level input voltage
GND
0.8
V
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
Supply current
IDD
Power supply current, 5-V
TYP (1)
MAX
S1/S2 =
Low/Low,
Low/High,
High/High
176
200
S1/S2 =
High/Low
8
20
2
5
mA
TEST CONDITIONS
VIH = VCC, VIL = V CC – 0.6 V,
RT = 50 Ω, AVCC = 3.3 V
Am/Bm(2:4) = 2.5 Gbps HDMI data
pattern
Am/Bm(1) = 250 MHz clock
MIN
UNIT
mA
VIH = VCC, VIL = V CC – 0.6 V,
RT = 50 Ω, AVCC = 3.3 V
Am/Bm(2:4) = 2.5 Gbps HDMI data pattern
Am/Bm(1) = 250 MHz clock
TMDS DIFFERENTIAL PINS
VOH
Single-ended high-level output voltage
AVCC–10
AVCC+10
mV
VOL
Single-ended low-level output voltage
AVCC–600
AVCC–400
mV
Vswing
Single-ended output swing voltage
400
600
mV
VOD(O)
Overshoot of output differential voltage
VOD(U)
Undershoot of output differential voltage
ΔVOC(SS)
Change in steady-state common-mode
output voltage between logic states
I(OS)
Short circuit output current
See Figure 3
VI(open)
Single-ended input voltage under high
impedance input or open input
II = 10 µA
RINT
Input termination resistance
VIN = 2.9 V
See Figure 2, AVCC = 3.3 V,
RT = 50 Ω
15% 2× Vswing
25% 2× Vswing
5
mV
-12
12
mA
VCC–10
VCC+10
mV
45
50
55
Ω
CONTROL PINS
IIH
High-level digital input current (2)
VIH = 2 V or VCC
-10
10
µA
IIL
Low-level digital input current (2)
VIL = GND or 0.8 V
-10
10
µA
(1)
(2)
8
All typical values are at 25°C and with a 3.3-V supply.
IIH and IIL specifications are not applicable to the VSADJ pin.
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
DDC I/O PINS
Ilkg
Input leakage current
VI = 0.1 VDD to 0.9 VDD to isolated DDC inputs
CIO
Input/output capacitance
VI(pp) = 1 V, 100 kHz
RON
Switch resistance
IO = 3 mA, VO = 0.4 V
VPASS
Switch output voltage
VI = 5 V, IO = 100 µA
10
µA
10
pF
40
Ω
2.4
2.7
V
-10
27
STATUS AND SOURCE SELECTOR PINS
IIH
High-level digital input current
VIH = 2 V or VDD
-10
10
µA
IIL
Low-level digital input current
VIL = GND or 0.8 V
-10
10
µA
VOH
TTL High-level output voltage
IOH = –100 μA
2.4
VDD
V
VOL
TTL Low-level output voltage
IOL = 100 μA
GND
0.4
V
SWITCHING CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
TMDS DIFFERENTIAL PINS (Y/Z)
tPLH
Propagation delay time, low-to-high-level output
400
650
900
ps
tPHL
Propagation delay time, high-to-low-level output
400
650
900
ps
tr
Differential output signal rise time (20% - 80%)
60
80
140
ps
tf
Differential output signal fall time (20% - 80%)
60
80
140
ps
tsk(p)
Pulse skew (|tPHL – tPLH|) (3)
6
20
ps
tsk(D)
Intra-pair differential skew, see Figure 4
20
40
ps
tsk(o)
Inter-pair channel-to-channel output skew (4)
30
65
ps
tsk(pp)
Part-to-part skew  (5)
510
ps
tjit(pp)
Peak-to-peak output jitter from Yj/Zj(1) residual jitter
8
20
ps
tjit(pp)
Peak-to-peak output jitter from Yj/Zj(2:4) residual jitter
60
80
ps
tSX
Select to switch output
50
70
ns
ten
Enable time
170
200
ns
tdis
Disable time
9
15
ns
tpd(DDC)
Propagation delay from SCLn to SCL_SINK or SDAn to
SDA_SINK or SDA_SINK to SDAn
8
15
ns
tsx(DDC)
Switch time from SCLn to SCL_SINK
8
15
ns
tpd(HPD)
Propagation delay (from HPD_SINK to the active port of HPD)
14
20
ns
tsx(HPD)
Switch time from port select to the latest valid status of HPD
33
50
ns
(1)
(2)
(3)
(4)
(5)
See Figure 2, AVCC = 3.3 V,
RT = 50 Ω
See Figure 5,
Am/Bm(1) = 250 MHz clock,
Am/Bm(2:4) = 2.5 Gbps HDMI pattern
See Figure 6,
10-mA Current source to the input
See Figure 7, CL = 10 pF
Measurements are made with the Agilent 81250 ParBert System with a N4872A generator (600 fs tJIT(CLK), 13 ps tJIT(pp)) and a N4873A
analyzer.
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2007–2011, Texas Instruments Incorporated
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TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
AVcc
RT
RT
ZO = RT
TMDS
Driver
TMDS
Receiver
ZO = RT
Figure 1. Termination for TMDS Output Driver
Vcc
R
R
INT
INT
RT
Y
A
VA
TMDS
Receiver
VID
TMDS
Driver
CL
0.5 pF
B
VB
V
AVcc
RT
VY
Z
ID
=
VA −
VB
Vswing =
VY −
VZ
VZ
VA
VB
DC Coupled
Vcc
AC Coupled
Vcc+0.2 V
Vcc−0.4 V
Vcc−0.2 V
0.4 V
VID
V
VID(pp)
ID
0V
−0.4 V
t PHL
t
PLH
100%
80%
Vswing
V OD(O)
0V Differential
VOD(pp)
20%
0%
tf
tr
VOD(U)
V OC
nVOC(SS)
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf < 100 ps, 100 MHz from
Agilent 81250. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement
equipment provides a bandwidth of 20 GHz minimum.
Figure 2. TMDS Input, Output, and Timing Definitions
10
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
50 W
IOS
TMDS
Driver
50 W
+
_
0 V or 3.6 V
Figure 3. Short Circuit Output Current Test Circuit
VOH
VY
50%
VZ
VOL
tsk(D)
Figure 4. Definition of Intra-Pair Differential Skew
AVcc
RT
Data +
Data Video Patterm
Generator
Coax
Coax
SMA
RX
+
SMA
EQ
HDMI Cables
1000 mVpp
Differential
M
U
X
OUT
<2" 50!
Transmission Line
<2" 50!
Transmission Line
SMA
SMA
Coax
Coax
TMDS251
AVcc
RT
Clk+
Clk-
Coax
Coax
SMA
RX
SMA
+
EQ
M
U
X
OUT
<2" 50!
Transmission Line
<2" 50!
Transmission Line
SMA
SMA
RT
Jitter Test
Instrument
RT
Coax
Coax
Jitter Test
Instrument
TP1
TP2
TP3
A.
HDMI 1.3 compliant cable when EQ = Low, and 10m 28AWG input cable when EQ = High.
B.
All jitters are measured in BER of 10-9
C.
The residual jitter reflects the total jitter measured at the output of the DUT, TP3, subtract the total jitter from the
signal generator, TP1
Figure 5. Jitter Test Circuit
Copyright © 2007–2011, Texas Instruments Incorporated
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TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Port 1 A
B
Port 2 A
B
S1
Clocking
VDD
2
VDD
0V
S2
tSX
tSX
75 mV
Output
-75 mV
75 mV
Hi-Z
-75 mV
ten
tdis
Figure 6. TMDS Outputs Control Timing Definitions
VDD
2
HPD_SINK
VDD
2
0.4 V
HPD1
tpd(HPD)
tsx(HPD)
tpd(HPD)
2.4 V
HPD2
S1
VDD
2
S2
VDD
tsx(DDC)
SDA_SINK
1.5V
tpd(DDC)
tpd(DDC)
SDA1
1.5V
SDA2
0V
Figure 7. Port Switch Timing Definitions
12
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SIGNAL RATE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
200
200
S1 = S2 = HIGH
150
VCC = AVCC = 3.3 V, TA = 25°C,
TP1 VID(PP) = 1200 mVPP, RVSADJ = 4.02 kW,
Am/Bm(2:4) HDMI Data pattern, 250 Mbps-2.5 Gbps
Am/Bm(1) Clock, 25 MHz-250 MHz
100
50
S1 = HIGH S2 = LOW
ICC - Supply Current - mA
ICC - Supply Current - mA
S1 = S2 = HIGH
VCC = AVCC = 3.3 V,
150
VID(PP) = 1200 mVPP, RVSADJ = 4.02 kW,
Am/Bm(2:4) 2.5-Gbps HDMI Data pattern,
Am/Bm(1) 250-MHz Clock
100
50
IDD
0
0
250 450 650 850 1050 1250 1450 1650 1850 2450
0
Signal Rate - Mbps
20
30
40
50
60
TA - Free Air Temperature - °C
Figure 9.
RESIDUAL PEAK-TO-PEAK JITTER
(Data Channels)
vs
SIGNAL RATE
RESIDUAL PEAK-TO-PEAK JITTER
(Clock Channel)
vs
FREQUENCY
70
5
See Note A
See Note A
Peak-to-Peak Jitter - % Tbit
Peak-to-Peak Jitter - % Tbit
10
Figure 8.
20
15
EQ = LOW
5m 28 AWG
10
IDD
S1 = HIGH S2 = LOW
EQ = HIGH
15m 26 AWG
5
4
EQ = HIGH 15m 26 AWG
3
EQ = HIGH 10m 28 AWG
EQ = LOW 3m 30 AWG
2
1
EQ = HIGH 10m 28 AWG
EQ = LOW 5m 28 AWG
EQ = LOW 3m 30 AWG
0
750
950
1150
1485
1850
Signal Rate - Mbps
0
2250
A. Channels 2, 3, 4, VCC = AVCC = 3.3 V, TA = 25°C, RVSADJ = 4.02
kΩ, See Figure 5
Figure 10.
Copyright © 2007–2011, Texas Instruments Incorporated
75
95
115
148.5
185
225
f - Frequency - MHz
A. Channel 1, VCC = AVCC = 3.3 V, TA = 25°C, RVSADJ = 4.02 kΩ,
See Figure 5
Figure 11.
13
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RESIDUAL PEAK-TO-PEAK JITTER
(Data Channel)
vs
CABLE
20
RESIDUAL PEAK-TO-PEAK JITTER
(Data Channel)
vs
CABLE
20
See Note A
See Note A
Peak-to-Peak Jitter - % Tbit
16
14
12
EQ = Low
10
8
EQ = High
6
Peak-to-Peak Jitter - % Tbit
18
15
EQ = Low
EQ = High
10
5
4
2
0
0
1.5m
30AWG
3m 30
AWG
5m
28AWG
Cable
10m
28AWG
15m
26AWG
A. 1080p 10-Bit, VCC = AVCC = 3.3 V, TA = 25°C, RVSADJ = 4.02 kΩ,
See Figure 5, Clock Channel = 185.6 MHz, Data Channel = 1.856
Gbps
Figure 12.
14
1.5m
30AWG
3m 30
AWG
5m
28AWG
Cable
10m
28AWG
15m
26AWG
A. 1080p 12-Bit, VCC = AVCC = 3.3 V, TA = 25°C, RVSADJ = 4.02 kΩ,
See Figure 5, Clock Channel = 222.8 MHz, Data Channel = 2.228
Gbps
Figure 13.
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
Supply Voltage
The TMDS251 is powered up with two different power sources. One is 3.3-V VCC for the TMDS circuitry, and the
other is 5-V VDD for HPD, DDC, and most of the control logic. It is recommended to provide the same 3.3-V
power source to the TMDS circuitry of the TMDS251 and its output termination voltage. This minimizes the
leakage current from the ESD protection circuitry. When the digital television (DTV) is in standby mode operation,
the same common 3.3-V power source can be turned on or off. Either way will minimize the leakage current in
the device, and in the receiver connected at the output where the termination is integrated.
TMDS Inputs
Selectable frequency response equalization circuitries are provided to all twelve differential input to support short
range and long range cable connections. The frequency response compensation curves and target cable losses
are shown in Figure 14 and Figure 15.
0
-1
EQ = Low
-2
3m 30 AWG cable
-3
Loss - dB
-4
-5
spec
-6
-7
-8
-9
-10
-11
-12
-13
0
250
500
750
1000
1250
1500
1750
2000
f - Frequency - MHz
Figure 14. Frequency Response Compensation Curve at EQ = L
Copyright © 2007–2011, Texas Instruments Incorporated
15
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
0
-2
-4
spec
-6
Loss -dB
-8
-10
10m cable
-12
-14
EQ = High
-16
-18
-20
0
250
500
750
1000
1250
1500
1750
2000
f - Frequency - MHz
Figure 15. Frequency Response Compensation Curve at EQ = H
Internal termination circuitry which can be switched on or off, provides 50-Ω resistance to each differential input
pin when a port is selected. External terminations are not required. When the termination is switched on, current
will flow to the TMDS driver. When a port is not selected, the termination is open. This stops supply current
flowing from the input pins of the unselected ports. This switchable termination provides the connected HDMI
source another method of determining the sink port status, and whether it is selected or not selected, without
referring to the HPD pin status.
TMDS Input Fail-Safe
The TMDS input does not incorporate a fail-safe circuit. To implement fail-safe, the input can be externally biased
to prevent output oscillation. One pin can be pulled high to VCC with the other grounded through a 1-kΩ resistor
as shown in Figure 16.
VCC
RINT
RINT
RT
A
B
TMDS
Receiver
TMDS
Driver
Y
AVCC
Z
RT
Figure 16. TMDS Input Fail-Safe Recommendation
TMDS Outputs
A 10% precision resistor, 4.02-kΩ, is recommended to control the output swing to the HDMI compliant 400 mV to
600 mV range (500 mV typical). The TMDS outputs are high impedance under standby mode operation, S1 = H
and S2 = L.
16
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
HPD Pins
The HPD circuits are powered by the 5-V supply. They provide 5-V TTL output signals to the SOURCE with a
typical 1-kΩ output resistance. An external 1-kΩ resistor is not needed here. The HPD output of the selected
source port follows the logic level of the HPD_SINK input. Unselected HPD outputs are kept low. When the
device is in standby mode, all HPD outputs follow HPD_SINK. A 1-kΩ resistor to ground keeps all HPD outputs
low in standby mode if a fixed low state is preferred.
DDC Channels
The DDC circuits (SDA, SCL) are powered by a 5-V supply. The I/O pins can connect to the 5-V termination
voltages directly. A 47-kΩ pull-up resistor to the 5 V is recommended on the SCL1 and SCL2 pins. There is no
pull-up resistor on the SDA pins. The pull-up resistor can be replaced with a different value.
Source
Sink
VDDSink
VDDSource
VCCRx
RupSink
RupSource
RupRx
I to-Source
Ron
SCL
SDA
SCL_SINK
SDA_SINK
I to-Sink
Driver (Source)
Driver (Sink)
Figure 17. Simplified Electrical Circuit Model for DDC Channel
In Figure 17, when the Driver (Sink) pulls the bus low, the highest voltage level is Vol(Sink)max. The current flow
through the pass-gate resistor can be presented as:
Vdd * V ol(Sink)max
Ito * Sink +
RupSource ø R upSink
(1)
where the Vddsource = Vddsink = Vdd
To simplify the equation, Vol(Sink)max is set equal to 0 V to reach equation (2):
Vdd
lto * Sink +
RupSource ø R upSink
(2)
The voltage at the input of the SINK is Ito - Sink × Ron + Vol(Sink)max, which should be lower than the minimum
input low threshold voltage of the Driver (Source), Vith(Source)min to keep the bus in correct interoperations.
V ith(Source)min u lto * Sink Ron ) V ol(Sink)max
(3)
By combining equations (2) and (3), the minimum pull-up resistor at the Sink input is:
V dd Ron RupSource
R upSink w
(Vith(Source)min * Vol(Sink)max) RupSource * V dd Ron
(4)
Applying the same methodology to calculate the pull-up resistor at the input of the Driver (Sink), the minimum
pull-up resistor is:
V ccRx Ron
R upRx w
(Vith(Sink)min * Vol(Source)max)
(5)
The data sheet VPASS specification ensures the maximum output voltage is clamped at 3.6 V to support a 3.3-V
connection. Resistors pulling up to 3.3 V on SCL_SINK and SDA_SINK ensure the high level does not exceed
the 3.3-V termination voltage.
Copyright © 2007–2011, Texas Instruments Incorporated
17
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
Layout Considerations
The high-speed differential TMDS inputs are the most critical paths for the TMDS251. There are several
considerations to minimize discontinuities on these transmission lines between the connectors and the device:
• Maintain 100-Ω differential transmission line impedance into and out of the TMDS251
• Keep an uninterrupted ground plane beneath the high-speed I/Os
• Keep the ground-path vias to the device as close as possible to allow the shortest return current path
• Keep the trace lengths of the TMDS signals between connector and device as short as possible
Using the TMDS251 in Systems with Different CEC Link Requirements
The TMDS251 supports a DTV with up to three HDMI inputs when used in conjunction with a signal-port HDMI
receiver or three HDMI inputs when used in conjunction with a dual-port HDMI receiver. Figure 18 and Figure 19
show simplified application block diagrams for the TMDS251 in different DTVs with different consumer electronic
control (CEC) requirements. The CEC is an optional feature of the HDMI interface for centralizing and simplifying
user control instructions from multiple audio/video products in an inter-connected system, even when all the
audio/video products are from different manufacturers. This feature minimizes the number of remote controls in a
system, as well as reducing the number of times buttons need to be pressed.
A DTV Supporting a Passive CEC Link
In Figure 18, the DTV does not have the capability of handling CEC signals, but allows CEC signals to pass over
the CEC bus. The source selection is done by the control command of the DTV. The user cannot force the
command from any audio/video product on the CEC bus. The selected source reads the E-EDID data after
receiving an asserted HPD signal. The micro-controller loads different CEC physical addresses while changing
the source by means of the S1 and S2 pins.
E-EDID Reading Configurations in Standby Mode
When the DTV system is in standby mode, the sources will not read the E-EDID memory because the 1-kΩ
pull-down resistor keeping the HPD_SINK input at logic low forces all HPD pins to output logic low to all sources.
The source will not read the E-EDID data with a low on HPD signal. However, if reading the E-EDID data in the
system standby mode is preferred, then TMDS251 can still support this need.
The recommended configuration sequences are:
1. Apply the same 3.3-V power to the VCC of TMDS251 and the TMDS line termination at the HDMI receiver
2. Turn off VCC, and keep VDD on. The TMDS circuit is off, but the HPD, the DDC and the source selection
circuits are active.
3. Set S1 and S2 to select the source port which is allowed to read the E-EDID memory.
Please note if the source has a time-out limitation between the 5 V and the HPD signals, the above configuration
is not applicable. Uses individual EEPROMs assigned for each input port, see Figure 19. The solution uses
E-EDID data to be readable during system power off or standby mode operations.
18
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
SINK
HPD
5V
HPD
5V
5V
47kW
SOURCE 1
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
D1
D2
CLK
D0
D1
D2
HPD1
VDD
(5V)
VCC
(3.3V)
EQ
mController
S1
S2
SDA1
SCL1
CEC
A21/B11
A22/B12
A23/B13
A24/B14
HPD_SINK
1kW
3.3V
HPD
5V
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
D1
D2
CLK
D0
D1
D2
4.7kW
5V
47kW
SOURCE 2
HPD2
4.7kW
DDC_SDA
DDC_SCL
SDA_SINK
SCL_SINK
E-EDID
SDA2
SCL2
HDMI RX
CEC
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
A21/B21
A22/B22
A23/B23
A24/B24
GND
VSadj
4.02kW 10%
Figure 18. Two-Port HDMI Enabled DTV with TMDS251 – CEC Commands Passing Through
A DTV Supporting an Active CEC Link
In Figure 19, R, and S, the CEC PHY and CEC LOGIC functions are added. The DTV can initiate and/or react to
CEC signals from its remote control or other audio/video products on the same CEC bus. All sources must have
their own CEC physical address to support the full functionality of the CEC link.
A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD
feedback. When HPD is high, the sink-assigned CEC physical address should be maintained. Otherwise, when
HPD is low the source sets CEC physical address value to (F.F.F.F).
Case 1 – AC Coupled Source (See Figure 19, Port 1)
When the source TMDS lines are AC coupled or when the source cannot detect the TMDS termination provided
in the connected sink, the indication of the source selection can only come from the HPD signal. The TMDS251
HPD1 pin should be applied directly as the HPD signal back to the source.
Case 2 – DC Coupled Source (See Figure 19, Port 2)
When the source TMDS lines are DC coupled, there are two methods to inform the source that it is the active
source to the sink. One is checking the HPD signal from the sink, and the other is checking the termination
condition in the sink.
In a full CEC operation mode, the HPD signal is set high whether the port is selected or not. The source loads
and maintains the CEC physical address when HPD is high. As soon as HPD goes low, the source loses the
CEC physical address. To keep the CEC physical address to the source, the HPD signal is looping back from the
source provided 5-V signal through a 1-kΩ pull-up resistor in the sink. This method is acceptable in application
where the HDMI transmitter can detect the receiver termination by current sensing, and the receiver has
switchable termination on the TMDS inputs. The internal termination resistors are connected to the termination
voltage when the port is selected, or they are disconnected when the port is not selected. The TMDS251
features switchable termination on the TMDS inputs.
Case 3 – External Logic Control for HPD (See Figure 19, Port 3)
When the HDMI transmitter does not have the capability of detecting the receiver termination, using the HPD
signal as a reference for sensing port selections is the only possible method. External control logic for switching
the connections of the HPD signals between the HPD pins of the TMDS251 and the 5-V signal from the source
provides a good solution.
Copyright © 2007–2011, Texas Instruments Incorporated
19
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
E-EDID Reading Configurations in Standby Mode
When the TMDS251 is in standby mode operation, S1 = H and S2 = L, all sources can read their E-EDID
memories simultaneously with all HPD pins following HPD_SINK in logic-high. HPD_SINK input low will prevent
E-EDID reading in standby mode operation.
SINK
HPD
5V
SOURCE
with AC coupled
HDMI output
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
D1
D2
CLK
D0
D1
D2
HPDx
VDD
(5V)
VCC
(3.3V)
SDA SCL
EQ
5V
47kW
SDAx
SCLx
mController
S1
S2
CEC
LOGIC
CEC E-EDID
Ax1/Bx1
Ax2/Bx2
Ax3/Bx3
Ax4/Bx4
HPD_SINK
1kW
CEC
PHY
3.3V
4.7kW
4.7kW
DDC_SDA
DDC_SCL
SDA_SINK
SCL_SINK
HDMI RX
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSadj
GND
4.02kW 10%
Figure 19. Two-Port HDMI Enabled DTV with TMDS251 – AC Coupled Source - CEC Commands Active
SINK
HPD
5V
HPD
5V
1kW
5V
47kW
SOURCE
with DC coupled
HDMI output
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
D1
D2
CLK
D0
D1
D2
HPDx
VDD
(5V)
VCC
(3.3V)
SDA SCL
EQ
SDAx
SCLx
mController
S1
S2
CEC
LOGIC
CEC E-EDID
Ax1/Bx1
Ax2/Bx2
Ax3/Bx3
Ax4/Bx4
HPD_SINK
1kW
CEC
PHY
3.3V
4.7kW
SDA_SINK
SCL_SINK
4.7kW
DDC_SDA
DDC_SCL
HDMI RX
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
GND
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSadj
4.02kW 10%
Figure 20. Two-Port HDMI Enabled DTV with TMDS251 – DC Coupled Source - CEC Commands Active
20
Copyright © 2007–2011, Texas Instruments Incorporated
TMDS251
SLLS852A – AUGUST 2007 – REVISED JULY 2011
www.ti.com
SINK
SOURCE
in general HDMI output
HPD
5V
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
D1
D2
CLK
D0
D1
D2
1kW
5V
47kW
HPDx
VDD
(5V)
VCC
(3.3V)
SDA SCL
EQ
SDAx
SCLx
mController
S1
S2
CEC
LOGIC
CEC E-EDID
Ax1/Bx1
Ax2/Bx2
Ax3/Bx3
Ax4/Bx4
HPD_SINK
1kW
CEC
PHY
3.3V
4.7kW
SDA_SINK
SCL_SINK
4.7kW
DDC_SDA
DDC_SCL
HDMI RX
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
GND
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSadj
4.02kW 10%
Figure 21. Two-Port HDMI Enabled DTV with TMDS251 – External Logic - CEC Commands Active
Spacer
REVISION HISTORY
Changes from Original (August 2007) to Revision A
•
Page
Added Junction Temperature to the THERMAL CHARACTERISTICS table ....................................................................... 7
Copyright © 2007–2011, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
TMDS251PAGR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TQFP
PAG
64
1500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
0 to 70
TMDS251
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TMDS251PAGR
Package Package Pins
Type Drawing
TQFP
PAG
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1500
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMDS251PAGR
TQFP
PAG
64
1500
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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