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Texas Instruments 3 port HDMI switch (Rev. A) Datasheet
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Three-Port HDMI Switch
Check for Samples: TMDS361B
FEATURES
1
•
2
•
•
•
•
•
•
•
•
3:1 Sink-side switch Supporting DVI Above
1920 × 1200 and HDMI HDTV Resolutions up to
1080p With 16-Bit Color Depth
Designed for Signaling Rates up to 3 Gbps
Supports HDMI 1.3a Specification
Adaptive Equalization on inputs to support up
to 20-m HDMI Cable at 2.25 Gbps for 1080p
12-Bit Color Depth
TMDS Input Clock-Detect Circuit
DDC Repeater Function
<2-mW Low-Power Mode
Local I2C or GPIO Configurable
Enhanced ESD. HBM: 10 kV on All Input
TMDS, DDC I2C, HPD Pins
•
•
•
•
3.3-Volt Power Supply
Temperature Range: 0°C to 70°C
64-Pin TQFP Package: Pin-Compatible With
TMDS351
Robust TMDS Receive Stage That Can Work
With Non-Compliant Input Common-Mode
HDMI Signal
APPLICATIONS
•
High-Definition Digital TV
– LCD
– Plasma
– DLP®
DESCRIPTION
The TMDS361B is a three-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch
that allows up to three DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one
hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel
supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. TMDS361B is not intended
for source side applications such as external switch boxes.
The TMDS361B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically
compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps. (see
Figure 15).
TYPICAL APPLICATION
Digital TV
Digital
Camcorder
BRTN TV1
Game
Machine
TM
D
S36
1
169 PALplus
DVD Player or DVR
M0124-01
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to
VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC
repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines
are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated
terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled.
Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is
detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a
high-impedance state.
The TMDS361B is designed to be controlled via a local I2C interface or GPIO interface based on the status of
the I2C_SEL pin. The local I2C interface in TMDS361B is a slave-only I2C interface. (See the I2C INTERFACE
NOTES section.)
I2C Mode: When the I2C_SEL pin is set low, the device is in I2C mode. With local I2C, the interface port status
can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C
buffer output-voltage-select (OVS) settings (See the DDC I2C Function Description for detailed description on
DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature, and
TMDS input-port selection can be set. See Table 8 through Table 11.
GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is
controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO
mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default
DDC I2C buffer OVS setting (OVS3) is set. See Table 8 and the DDC I2C Function Description for a detailed
description of the DDC I2C buffer.
Following are some of the key features (advantages) that TMDS361B provides to the overall sink-side system
(HDTV).
•
•
•
3×1 switch that supports TMDS data rates up to 3 Gbps on all three input ports
ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side
pins on the TMDS361B are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI
sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to
higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference
[ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization
adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.
TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures
that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature
can be bypassed in I2C mode; see Table 10 and Table 11. It is recommended to enable the TMDS
clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS
termination-voltage test), the clock-detect feature should be disabled by using the I2C mode control. If the
customer requires passing the TMDS termination-voltage test in GPIO mode with the default TMDS
clock-detect circuitry enabled, then a valid TMDS clock should be provided for this compliace test, so that the
terminations on the TMDS data pair can be connected, and thus customer can pass the TMDS
termination-voltage test.
DDC I2C buffer: This feature provides isolation on the source side and sink side DDC I2C capacitance, thus
helping the sink system to pass system-level compliance.
Robust TMDS receive stage: This feature ensures that the TMDS361B can work with TMDS input signals
having common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI
specifications.
VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS
swing of the TMDS361B (if needed) based on the system requirements.
GPIO or local I2C interface to control the device features
•
TMDS output edge-rate control: This feature adjusts the TMDS361B TMDS output rise and fall times. There
2
Copyright © 2009–2011, Texas Instruments Incorporated
•
•
•
•
•
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall
time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV)
in passing regulatory EMI compliance.
FUNCTIONAL BLOCK DIAGRAM
Vcc
RINT RINT
Dx+_1
TMDS Rx
w/ AEQ
Dx–_1
Vcc
RINT RINT
CLK+_1
TMDS Rx
CLK–_1
Clock Detect
VSadj
Tx
SCL1
Rx
Dx+_SINK
TMDS Tx
Tx
Dx–_SINK
SDA1
Rx
xx2
3:1
MUX
Vcc
CLK+_SINK
TMDS Tx
CLK–_SINK
RINT RINT
Dx+_3
Rx
TMDS Rx
w/ AEQ
Dx–_3
SCL_SINK
Tx
Vcc
Rx
RINT RINT
SDA_SINK
CLK+_3
Tx
TMDS Rx
CLK–_3
Clock Detect
Clock Detect
Tx
SCL3
Rx
Tx
SDA3
Rx
HPD1
HPD_SINK
1 kW
I2C_SEL
2
HPD2
HPD3
1 kW
1 kW
Local I C
and
Control Logic
LP
S1/SCL
S2/SDA
B0330-01
Copyright © 2009–2011, Texas Instruments Incorporated
3
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
PAG PACKAGE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
HPD3
D2+_2
D2–_2
VCC
D1+_2
D1–_2
GND
D0+_2
D0–_2
VCC
CLK+_2
CLK–_2
SCL2
SDA2
HPD2
LP
PAG-64
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TMDS361B
64-pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D2+_1
D2–_1
VCC
D1+_1
D1–_1
GND
D0+_1
D0–_1
VCC
CLK+_1
CLK–_1
SCL1
SDA1
HPD1
I2C_SEL
S2/SDA
D2+_SINK
D2–_SINK
VCC
D1+_SINK
D1–_SINK
GND
D0+_SINK
D0–_SINK
VCC
CLK+_SINK
CLK–_SINK
GND
SCL_SINK
SDA_SINK
HPD_SINK
S1/SCL
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SDA3
SCL3
GND
CLK–_3
CLK+_3
VCC
D0–_3
D0+_3
GND
D1–_3
D1+_3
VCC
D2–_3
D2+_3
GND
VSadj
P0010-10
4
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
PIN FUNCTIONS
PIN
SIGNAL
NO.
I/O
DESCRIPTION
TMDS INPUT PINS
CLK+_1
CLK–_1
D[0:2]+_1
D[0:2]–_1
CLK+_2
CLK–_2
D[0:2]+_2
D[0:2]–_2
CLK+_3
CLK–_3
D[0:2]+_3
D[0:2]–_3
39
38
I
Port-1 TMDS differential clock
42, 45, 48
41, 44, 47
I
Port-1 TMDS differential data inputs
54
53
I
Port-2 TMDS differential clock
57, 60, 63
56, 59, 62
I
Port-2 TMDS differential data inputs
5
4
I
Port-3 TMDS differential clock
8, 11, 14
7, 10, 13
I
Port-3 TMDS differential data inputs
TMDS OUTPUT PINS
CLK+_SINK
CLK–_SINK
D[0:2]+_SINK
D[0:2]–_SINK
26
27
O
TMDS sink differential clock
23, 20, 17
24, 21, 18
O
TMDS sink differential data outputs
HOT-PLUG-DETECT STATUS PINS
HPD[1:3]
HPD_SINK
35, 50, 64
O
Source port hot-plug-detect output
31
I
Sink hot-plug-detect input
DDC PINS
SCL[1:3]
37, 52, 2
I/O
TMDS port bidirectional DDC clock
SDA[1:3]
36, 51, 1
I/O
TMDS port bidirectional DDC data
SCL_SINK
29
I/O
TMDS sink-side bidirectional DDC clock
SDA_SINK
30
I/O
TMDS sink-side bidirectional DDC data
LP
49
I
Low-power select bar
I2C_SEL
34
I
GPIO/local I2C control select
S1/SCL
32
I
Source select 1(GPIO) / local I2C clock (I2C)
S2/SDA
33
I/O
Source select 2 (GPIO) / local I2C data (I2C)
VSadj
16
I
VCC
6, 12, 19, 25,
40, 46, 55, 61
GND
3, 9, 15, 22,
28, 43, 58
CONTROL PINS
TMDS-compliant voltage swing control
SUPPLY AND GROUND PINS
Copyright © 2009–2011, Texas Instruments Incorporated
3.3-V supply
Ground
5
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Table 1. Source Selection Lookup (1)
CONTROL PINS
6
HOT-PLUG DETECT STATUS
Power Mode
S2
S1
Port Selected
SCL_SINK
SDA_SINK
H
H
Port 1
Terminations of
port 2 and port 3
are disconnected.
SCL1
SDA1
HPD_SINK
L
L
Normal mode
H
L
Port 2
Terminations of
port 1 and port 3
are disconnected.
SCL2
SDA2
L
HPD_SINK
L
Normal mode
L
L
Port 3
Terminations of
port 1 and port 2
are disconnected.
SCL3
SDA3
L
L
HPD_SINK
Normal mode
HPD_SINK
HPD_SINK
HPD_SINK
Standby mode
L
(1)
I/O SELECTED
H
None (Z)
None (Z)
Are pulled HIGH
All terminations are
by external
disconnected.
pullup
termination
HPD1
HPD2
HPD3
H: Logic high; L: Logic low; X: Don't care; Z: High impedance
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TMDS Input Stage
TMDS Output Stage
VCC
Y
Z
50 W
50 W
B
A
10 mA
HPD Output Stage
Status and Source Selector
VCC
VCC
HPD_SINK
S1
S2
HPD1
HPD2
DDC Buffer
VCC
Buffer
S0386-02
Copyright © 2009–2011, Texas Instruments Incorporated
7
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Table 2. Control-Pin Lookup Table (1)
SIGNAL
LEVEL
STATE
H
Normal mode
L
Low-power
mode
LP
S[2:1]
GPIO
mode
I2C_SEL
VSadj
(1)
DESCRIPTION
Normal operational mode for device. If LP is left floating, then a weak internal pullup to VCC
pulls it to VCC.
Device is forced into a low-power state, causing the inputs and outputs to go to a
high-impedance state. All other inputs are ignored.
S2
S1
H
H
Port 1
Port 1 is selected as the active port; all other ports are low.
H
L
Port 2
Port 2 is selected as the active port; all other ports are low.
L
L
Port 3
Port 3 is selected as the active port; all other ports are low.
L
H
HPD[1:3] follow
HPD_SINK
Standby mode: HPD[1:3] follow HPD_sink.
2
Device is configured by I2C logic.
L
I C
H
GPIO
Device is configured by GPIO. If the I2C_SEL pin is left floating, then a weak internal pullup to
VCC pulls the I2C_SEL pin high.
4.02 kΩ
Compliant
voltage
Driver output voltage swing precision control to aid with system compliance. The VSadj
resistor value can be selected to be 4.02 kΩ ±10% based on the system requirement to pass
HDMI compliance.
(H) Logic high; (L) Logic low
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
TMDS361BPAGR
TMDS361B
64-pin TQFP reel (large)
TMDS361BPAG
TMDS361B
64-pin TQFP tray
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range (2)
VCC
Electrostatic discharge
–0.3 to 5.5
Control and status I/O
–0.3 to 5.5
Human body model (3) on SCL[1:3], SDA[1:3], HPD[1:3], D[0:2]+_[1:3],
D[0:2]–_[1:3], CLK+_[1:3], CLK–_[1:3] pins
±10,000
Human body model (3) on all other pins
±9,000
Charged-device model (4)
±1500
±8,000
±15,000
, contact discharge
V
V
±200
IEC 61000-4-2 (6), air discharge
Continuous power dissipation
8
(5)
(6)
IEC 61000-4-2
(2)
(3)
(4)
(5)
(6)
V
HPD and DDC I/O
Machine model
(1)
UNIT
–0.3 to 4
TMDS I/O
Voltage range
VALUE
–0.3 to 3.6
See Dissipation Ratings table
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
Tested in accordance with IEC EN 61000-4-2
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
DISSIPATION RATINGS
PACKAGE
PCB JEDEC STANDARD
TA ≤ 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
Low-K
1066 mW
10.66 mW/°C
586 mW
High-K
1481 mW
14.8 mW/°C
814 mW
64-pin TQFP (PAG)
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
RθJB
Junction-to-board thermal resistance
37.13
°C/W
RθJC
Junction-to-case thermal resistance
15.3
°C/W
PD(1)
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
Device power dissipation in normal mode TMDS data pattern; HPD_SINK = HIGH,
S1/S2 = LOW/LOW, LOW/HIGH, HIGH/HIGH
560
780
mW
PD(2)
Device power dissipation in standby
mode
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
TMDS data pattern; HPD_SINK = HIGH,
S1 = HIGH, S2 = LOW
10
20
mW
PSD
Device power dissipation in low-power
mode
LP = LOW
1
2
mW
PNCLK
LP = HIGH, no TMDS input clock,
Device power dissipation in normal mode
HPD_SINK =HIGH, S1/S2 = LOW/LOW,
with no active TMDS input clock
LOW/HIGH, HIGH/HIGH
40
65
mW
TJ
Junction Temperature
125
°C
(1)
0
The maximum rating is simulated under 3.6-V VCC across worst-case temperature and process variation. Typical conditions are
simulated at 3.3-V VCC, 25°C with nominal process material.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
UNIT
V
TA
Operating free-air temperature
0
70
°C
V
TMDS DIFFERENTIAL OUTPUT AND INPUT PINS
VID(pp)
Peak-to-peak input differential voltage
0.15
1.56
VIC
Input common-mode voltage
VCC – 0.4
VCC + 0.01
tIN_Rise_Fall
TMDS input rise and fall time
75
VIN_PRE
Acceptable pre-emphasis on TMDS input signals. Note that an input
signal into TMDS361B with longer pre-emphasis duration and/or larger
pre-emphasis amplitude could result in over-equalization.
AVCC
TMDS output termination voltage
dR
Data rate
RVSadj
Resistor for TMDS-compliant voltage output swing
RT
Termination resistance
V
ps
See (Figure 26)
3
3.3
3.6
3.66
4.02
4.47
kΩ
45
50
55
Ω
3
V
Gbps
DDC PINS
VI
Input voltage
dR(I2C)
I2C data rate
0
5.5
V
100
Kbps
HPD AND CONTROL PINS
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
Copyright © 2009–2011, Texas Instruments Incorporated
9
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
DEVICE POWER
The TMDS361B is designed to operate from a single 3.3-V supply voltage. The TMDS361B has three power
modes of operation. These three modes are referred to as normal mode, standby mode, and low-power mode.
Normal mode is designed to be used during typical operating conditions. In normal mode, the device is fully
functional and consumes the greatest amount of power.
Standby mode is designed to be used when reduced power is desired, but DDC and HPD communication must
be maintained. Standby mode can be enabled via the I2C interface (See Table 8 through Table 11) or GPIO
interface (See Table 1). In standby mode, the high-speed TMDS data and clock channels are disabled to reduce
power consumption. The internal I2C logic and DDC function normally. HPD[1:3] follow HPD_SINK.
Low-power mode is designed to consume the least possible amount of power while still applying 3.3 V to the
device. Low-power mode can be enabled by either the LP pin or by local I2C (See Table 8 through Table 11). In
low-power mode, all of the inputs and outputs are disabled with the exception of the internal I2C logic and LP pin.
The clock-detect feature in the TMDS361B provides an automatic power-management feature in normal mode. If
no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected, and the TMDS
outputs are high-Z. As soon as a valid TMDS clock is detected, the terminations on the TMDS data lines are
connected, the TMDS outputs come out of high-Z, and the device is fully functional and consumes the greatest
amount of power.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
ICC
Normal-mode supply current
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps TMDS data
pattern; HPD_SINK = HIGH, S1/S2 = LOW/LOW, LOW/HIGH,
HIGH/HIGH
ISTBY
Standby supply current
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps TMDS data
pattern; HPD_SINK = HIGH, S1 = HIGH, S2 = LOW
ISD
Shutdown current
LP = LOW
INCLK
Normal-mode supply current, with LP = HIGH, no TMDS input clock, HPD_SINK = HIGH,
no active TMDS input clock
S1/S2 = LOW/LOW, LOW/HIGH, HIGH/HIGH
TYP MAX
UNIT
170
216
mA
3
5.5
mA
300
555
μA
12
18
mA
HOT-PLUG DETECT
The TMDS361B is designed to support the hot-plug indication to the input ports (HDMI/DVI sources connected to
the TMDS361B) via the HPD[1:3] output pins. The state of the hot-plug output of the selected source follows the
state of the hot-plug input (HPD_SINK input pin) from the sink side. The state of the hot-plug output for the
non-selected source goes low (See Table 1).
The maximum VOH of the HPD depends on VCC. It is recommended that if VOH greater than 3.6 V is needed on
HPD, then an external circuit can be used to drive VOH from the 5 V of the HDMI source (connected as shown in
Figure 45).
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
VOH(HPD)
High-level output voltage
PARAMETER
IOH = 100 μA
2
VCC
V
VOL(HPD)
Low-level output voltage
IOL = 100 μA
0
0.4
V
IH
High-level input current
VIH = 2 V, VCC = 3.6 V
–10
10
μA
IL
Low-level input current
VIL = 0.8 V, VCC = 3.6 V
–10
10
μA
RL
Output source impedance
1200
Ω
10
TEST CONDITIONS
MIN
TYP
800 1000
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPD1(HPD)
HPD_SINK propagation delay
HPD_SINK to HPD[1:3]
12
20
ns
tS1(HPD)
Selecting port HPD switch time
S[1:2] to HPD[1:3]
17
30
ns
tS2(HPD)
Deselecting port HPD switch time
S[1:2] to HPD[1:3]
14
22
ns
tZ(HPD)
Low-power to high-level propagation delay
LP to HPD[1:3]
13
20
ns
5V
HPD
BUFFER
HPD Input
HPD_SINK
HPD Output
2.5 V
5 pF
5 pF
0V
tPD1(HPD)
3.3 V
HPD[1:3]
S0367-01
1.65 V
0V
T0387-01
Figure 1. HPD Test Circuit
Figure 2. HPD Timing Diagram #1
5V
HPD_SINK
0V
5V
2.5 V
0V
S1
5V
S2
0V
VCC
VCC/2
0V
HPD2
ts2
VCC
VCC/2
0V
HPD1
ts1
5V
2.5 V
0V
LP
tz
T0423-01
Figure 3. HPD Timing Diagram #2
Copyright © 2009–2011, Texas Instruments Incorporated
11
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TMDS DDC and Local I2C Pins
DDC I2C Buffer or Repeater: The TMDS361B provides buffering on the DDC I2C interface for each of the input
ports connected. This feature isolates the capacitance on the source side from the sink side and thus helps in
passing system-level compliance. See the DDC I2C Function Description section for a detailed description on
how the DDC I2C buffer operates. Note that a key requirement on the sink side is that the VIL(Sink) (input to
TMDS361B) should be less than 0.4 V. This requirement should be met for the DDC I2C buffer to function
properly. There are three settings of VIL(Sink) and VOL(Sink) that can be chosen based on OVS settings (See Table 8
through Table 11).
Local I2C Interface: The TMDS361B includes a slave I2C interface to control device features like TMDS input
port selection, TMDS output edge-rate control, power management, DDC buffer OVS settings, etc. See Table 8
through Table 11.
The TMDS361B is designed to be controlled via a local I2C interface or GPIO interface, based on the status of
the I2C_SEL pin. The local I2C interface in the TMDS361B is only a slave I2C interface. See the I2C INTERFACE
NOTES section for a detailed description of I2C functionality.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 3.6 V, VI = 0 V
–10
10
μA
Sink pins
VCC = 3.6 V, VI = 4.95 V
–10
10
μA
Input/output capacitance
Sink pins
DC bias = 2.5 V, ac = 3.5 Vp-p,
f = 100 kHz
15
pF
VIH(Sink)
High-level input voltage
Sink pins
VIL1(Sink)
Low-level input voltage
Sink pins
OVS 1
VOL1(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = HIGH
VIL2(Sink)
Low-level input voltage
Sink pins
OVS 2
VOL2(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = LOW
VIL3(Sink)
Low-level input voltage
Sink pins
OVS 3
VOL3(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = high-Z
Ilkg(I2C)
Input leakage current
Port[1:3] pins
VCC = 3.6 V, VI = 4.95 V
CIO(I2C)
Input/output capacitance
Port[1:3] pins
DC bias = 2.5 V, ac = 3.5 Vp-p, f = 100 kHz
VIH(I2C)
High-level input voltage
VIL(I2C)
VOL(I2C)
IL
Low-level input current
Ilkg(Sink)
Input leakage current
CIO(Sink)
12
2.1
5.5
V
–0.2
0.4
V
0.6
0.7
V
–0.2
0.4
V
0.5
0.6
V
–0.2
0.3
V
0.4
0.5
V
–10
10
μA
15
pF
Port[1:3] pins
2.1
5.5
V
Low-level input voltage
Port[1:3] pins
–0.2
1.5
V
Low-level output voltage
Port[1:3] pins
0.2
V
IO = 3 mA
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH1
Propagation delay time, low to high
Source to sink
80
251
ns
tPHL1
Propagation delay time, high to low
Source to sink
35
200
ns
tPLH2
Propagation delay time, low to high
Sink to source
204
459
ns
tPHL2
Propagation delay time, high to low
Sink to source
35
200
ns
tf1
Output signal fall time
Sink side
20
72
ns
tf2
Output-signal fall time
Source side
20
72
ns
fSCL
SCL clock frequency for internal register
Local I2C
100
kHz
tW(L)
Clock LOW period for I2C register
Local I2C
4.7
μs
tW(H)
Clock HIGH period for internal register
Local I2C
4
μs
tSU1
Internal register setup time, SDA to SCL
Local I2C
250
ns
*1
2
Internal register hold time, SCL to SDA
Local I C
0
μs
t(buf)
Internal register bus free time between STOP and START
Local I2C
4.7
μs
tsu(2)
Internal register setup time, SCL to START
Local I2C
4.7
μs
th(2)
Internal register hold time, START to SCL
Local I2C
4
μs
4
μs
th(1)
tsu(3)
2
Internal register hold time, SCL to STOP
Local I C
VCC
5V
RL = 2 kW
PULSE
GENRATOR
D.U.T.
RT
CL = 100 pF
VOUT
VIN
S0369-01
Figure 4. Sink-Side Test Circuit
VCC
5V
RL = 2 kW
PULSE
GENRATOR
D.U.T.
RT
CL = 400 pF
VIN
VOUT
S0370-01
Figure 5. Source-Side Test Circuit
Copyright © 2009–2011, Texas Instruments Incorporated
13
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
5V
SCL[x]
SDA[x]
Input
1.6 V
0.1 V
tPHL2
tPLH2
5V
80%
SCL_SINK
SDA_SINK
Output
1.6 V
20%
VOL
tf2
T0388-01
Figure 6. Source-Side Output AC Measurements
5V
SCL_SINK
SDA_SINK
Input
1.6 V
0.1 V
tPHL1
5V
80%
SCL[x]
SDA[x]
Output
1.6 V
20%
VOL
tf1
T0389-01
Figure 7. Sink-Side Output AC Measurements
5V
SCL_SINK
SDA_SINK
Input
VOL
tPLH1
5V
SCL[x]
SDA[x]
Output
1.6 V
T0390-01
Figure 8. Source-Side Output AC Measurements (Continued)
TMDS Main Link Pins
The TMDS port of the TMDS361B is designed to support the Digital Video Interface (DVI) 1.0 and High Definition
Multimedia Interface (HDMI) 1.3 specifications. The differential output voltage swing can be fine-tuned with the
VSadj resistor.
14
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Single-ended HIGH-level output voltage
AVCC – 10
AVCC + 10
mV
VOL
Single-ended LOW-level output voltage
AVCC – 600
AVCC – 400
mV
VSWING
Single-ended output voltage swing
400
600
mV
VOC(SS)
Change in steady-state common-mode
output voltage between logic states
5
mV
VOD(pp)
Peak-to-peak output differential voltage
V(O)SBY
Single-ended standby output voltage
I(O)OFF
Single-ended power-down output current
IOS
VCD(pp)
AVCC = 3.3 V, RT = 50 Ω
800
1200
mV
AVCC – 10
AVCC + 10
mV
0 V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V,
RT = 50 Ω
–10
10
μA
Short-circuit output current
See Figure 16
-15
15
mA
Minimum valid clock differential voltage
(peak-to-peak)
Input TMDS clock frequency = 300
MHz
100
12
mV
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH
Propagation delay time
250
800
ps
tPHL
Propagation delay time
250
800
ps
tR1
Rise time, fastest mode (default
setting): fastest setting
84
110
140
ps
tF1
Fall time, fastest mode (default setting):
fastest setting
84
110
140
ps
tR2
Rise time, fastest mode + 50 ps
(approximately)
142
160
190
ps
tF2
Fall time, fastest mode + 50 ps
(approximately)
142
160
190
ps
tR3
Rise time, fastest mode + 100 ps
(approximately)
187
210
230
ps
tF3
Fall time, fastest mode + 100 ps
(approximately)
187
210
230
ps
tR4
Rise time, fastest mode + 120 ps
(approximately): slowest setting
216
230
260
ps
tF4
Fall time, fastest mode + 120 ps
(approximately): slowest setting
216
230
260
ps
tSK(P)
Pulse skew (see
8
15
ps
tSK(D)
Intra-pair skew
10
30
ps
tSK(O)
Inter-pair skew (see
100
ps
198
ps
tJITD(PP)
(1)
(2)
(3)
AVCC = 3.3 V, RT = 50 Ω. See Figure 9 and
Figure 10.
(2)
)
AVCC = 3.3 V, RT = 50 Ω. See Figure 11.
(3)
)
Peak-to-peak output residual data jitter
AVCC = 3.3 V, RT = 50 Ω, dR = 2.25 Gbps.
See Figure 14 for measurement setup; residual
jitter is the total jitter measured at TTP4 minus
the jitter measured at TTP1. See Figure 15 for
the loss profile of the cable used for tJITD(PP)
measurement. Also see Typical Curves for
tJITD(PP) across cable length and input TMDS
data rate.
125
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
Copyright © 2009–2011, Texas Instruments Incorporated
15
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
54
84
ps
AVCC = 3.3 V, RT = 50 Ω, input TMDS clock
frequency = 225 MHz. See Figure 14for
measurement setup; residual jitter is the total
jitter measured at TTP4 minus the jitter
measured at TTP1. See Figure 15 for the loss
profile of the cable used for tJITC(PP)
measurement. tJITC(PP) is measured at TMDS
differential clock signal crossing.
UNIT
tJITC(PP)
Peak-to-peak output residual clock jitter
tCLK1
Valid clock-detect enable time
AVCC = 3.3 V, RT = 50 Ω, input TMDS clock
frequency = 300 MHz. See Figure 13.
300
500
ns
tCLK2
Invalid clock-detect disable time
AVCC = 3.3 V, RT = 50 Ω, input TMDS clock
frequency = 1 MHz. See Figure 13.
500
800
ns
tSEL1
Port selection time (see
AVCC = 3.3 V, RT = 50 Ω
300
500
ns
tSEL2
Port deselection time (see
AVCC = 3.3 V, RT = 50 Ω
40
50
ns
fCD
Clock-detect frequency
300
MHz
(4)
(5)
(4)
(5)
)
AVCC = 3.3 V, RT = 50 Ω. See Figure 13.
25
tSEL1 includes the time for the valid clock-detect enable time and tS1(HPD), because the tS1(HPD) event happens in parallel with tSEL1; thus,
the tSEL1 time is primarily the tCLK1 time.
tSEL2 is primarily the tS2(HPD) time.
AVCC
VCC
50 W
50 W
50 W
D+
VD+
Receiver
VID
D–
VD–
50 W
0.5 pF
VID = VD+ – VD–
V
= (VD+ + VD–)
ICM
2
Y
Driver
VY
Z
VOD = VY – VZ
V = (VY + VZ)
VZ
OC
2
S0371-01
Figure 9. TMDS Main-Link Test Circuit
16
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
3.3 V
VID
2.8 V
VID+
VID(pp)
0V
VID–
tPLH
tPHL
80%
20%
tf
80%
VOD(pp)
VOD
20%
tr
T0391-01
Figure 10. TMDS Main-Link Timing Measurements
VOH
VY
50%
VZ
VOL
tsk(D)
Figure 11. Definition of Intra-Pair Differential Skew
VOC
DVOC(SS)
T0392-01
Figure 12. TMDS Main-Link Common-Mode Measurements
VCD(PP)
Valid Input TMDS clock
that meets the min
Frequency Threshold and
Amplitude
tclk1
tclk2
TMDS outputs
HiZ during this duration
VOD(PP)
TMDS
outputs
HiZ
TMDS output clock with
peak to peak swing
compliant to the HDMI
spec and same frequency
as the Input TMDS clock
frequency
T0424-01
Figure 13. Clock-Detect Timing Diagram
Copyright © 2009–2011, Texas Instruments Incorporated
17
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
(4)
AVCC
RT
Data+
Parallel
BERT
Data–
Coax
Coax
SMA
(6)
RX
+EQ
SMA
HDMI Cable
1000-mVpp
Differential
<2-inch 50-W
Transmission Line
OUT
(6)
<2-inch 50-W
Transmission Line
SMA
SMA
Coax
Clk–
Coax
Coax
Jitter Testnnn
(2, 3)
AVCC Instrument
(1)
TMDS361B
SMA
(6)
RX
+EQ
SMA
(5)
Coax
RT
Clk+
RT
<2-inch 50-W
Transmission Line
OUT
(6)
<2-inch 50-W
Transmission Line
SMA
SMA
RT
Coax
Coax
Jitter Testnnn
(2, 3)
Instrument
TTP1
TTP2
TTP4
TTP3
B0331-11
(1)
The HDMI cable between TTP1 and TTP2 is 0 m (no loss) case and 20 m case. See Figure 15 for the loss profile of
the cable.
(2)
All jitter is measured at a BER of 10–9.
(3)
Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.
(4)
AVCC = 3.3 V; VSadj = 4.02 kΩ.
(5)
RT = 50 Ω.
(6)
2 inches = 5,08 cm.
NOTES: Output edge rate default (fastest): input edge rate from the parallel BERT greater than 75 ps (20%–80%). The input
signal from the parallel BERT has no pre-emphasis.
Figure 14. Jitter Measurement Setup
2
HDMI Cable 0 m
−3
Amplitude − dB
−8
−13
−18
−23
HDMI Cable 20 m
−28
−33
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f − Frequency − GHz
G001
Figure 15. Loss Profile of 20-m HDMI Cable
18
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
50 W
OS
Driver
50 W
+
– 0 V or 3.6 V
S0372-01
Figure 16. TMDS Main Link Short-Circuit Output Circuit
TYPICAL CHARACTERISTICS
AVCC = 3.3 V, RT = 50 Ω
POWER
vs
AMBIENT TEMPERATURE
POWER
vs
INPUT TMDS DATA RATE
590
590
Fastest (Default) TMDS Output Edge Rate
570
570
550
P − Power − mW
P − Power − mW
550
Fastest (Default) TMDS Output Edge Rate
530
510
Slowest TMDS Output Edge Rate
490
530
510
Slowest TMDS Output Edge Rate
490
VCC = 3.3 V
VSadj = 4.02 KΩ
Input TMDS Data Rate = 2.25 Gbps
470
470
450
0
10
20
30
40
50
TA − Ambient Temperature − °C
Figure 17.
Copyright © 2009–2011, Texas Instruments Incorporated
60
70
450
0.0
TA = 25°C
VCC = 3.3 V
VSadj = 4.02 KΩ
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Input TMDS Data Rate − Gbps
G002
G003
Figure 18.
19
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
PEAK-to-PEAK RESIDUAL CLOCK JITTER
vs
INPUT TMDS DATA RATE
PEAK-to-PEAK RESIDUAL DATA JITTER
vs
INPUT TMDS DATA RATE
160
TA =25°C
VCC = 3.3 V
VSadj = 4.02 kΩ
50
20 m, 22 AWG
HDMI Cable
Peak-to-Peak Residual Data Jitter − ps
Peak-to-Peak Residual Clock Jitter − ps
60
20 m, 24 AWG
HDMI Cable
40
30
15 m, 26 AWG
HDMI Cable
20
10
3 m, 28 AWG HDMI Cable
50
100
150
200
140
20 m, 24 AWG
HDMI Cable
120
100
80
20 m, 22 AWG
HDMI Cable
60
3 m, 28 AWG HDMI Cable
40
TA =25°C
VCC = 3.3 V
VSadj = 4.02 kΩ
20
10 m, 28 AWG
HDMI Cable
0
0
15 m, 26 AWG
HDMI Cable
250
300
0
0.0
350
0.5
Input TMDS Clock Frequency − MHz
1.0
1.5
10 m, 28 AWG
HDMI Cable
2.0
2.5
3.0
G009
G005
Figure 19.
Figure 20.
PEAK-to-PEAK RESIDUAL CLOCK JITTER
vs
HDMI CABLE LENGTH
PEAK-to-PEAK RESIDUAL DATA JITTER
vs
HDMI CABLE LENGTH
250
TA = 25°C
VCC = 3.3 V
VSadj = 4.02 kΩ
70
Peak-to-Peak Residual Data Jitter − ps
Peak-to-Peak Residual Clock Jitter − ps
80
60
50
40
30
20
10
0
20 m
28
AWG
TA = 25°C
VCC = 3.3 V
VSadj = 4.02 kΩ
200
150
100
50
0
20 m
24
AWG
20 m
22
AWG
15 m
26
AWG
10 m
28
AWG
5m
28
AWG
3m
28
AWG
HDMI Cable Length
Figure 21.
20
3.5
Input TMDS Data Rate − Gbps
3m
30
AWG
1m
28
AWG
1m
30
AWG
G010
20 m
28
AWG
20 m
24
AWG
20 m
22
AWG
15 m
26
AWG
10 m
28
AWG
5m
28
AWG
3m
28
AWG
HDMI Cable Length
3m
30
AWG
1m
28
AWG
1m
30
AWG
G007
Figure 22.
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
DIFFERENTIAL OUTPUT VOLTAGE
vs
RESISTANCE
VOD(pp) − Differential Output Voltage − mV
1600
TA = 25°C
1400
VCC = 3.6 V
1200
1000
VCC = 3.3 V
800
VCC = 3 V
600
400
200
0
3
4
5
6
7
VSadj Resistance − kΩ
G008
Figure 23.
(1)
The HDMI cable between TTP1 and TTP2 is 0 m (no loss) case. See Figure 15 for the loss profile of the cable.
(2)
Eye data is measured using an 8-GHz bandwith oscilloscope (Agilent).
(3)
Eye data is taken at TTP4.
(4)
AVCC = 3.3 V; VSadj = 4.02 kΩ.
(5)
RT = 50 Ω.
(6)
2 inches = 5,08 cm.
NOTES: Output edge rate default (fastest): input edge rate from the video pattern generator greater than 75 ps (20%–80%).
The input signal from the parallel BERT has pre-emphasis. See Figure 26 for acceptable input pre-emphasis duration
and amplitude.
Pass/fail criterion: output eye at TTP4 should comply with output eye mask (See Figure 25). The input TMDS clock
frequencies tested: 25 MHz, 30.24 MHz, 36 MHz, 54 MHz, 65 MHz, 74.25 MHz, 84.75 MHz, 108 MHz, 135 MHz,
148.5 MHz, 185.625 MHz, 222.75 MHz, 297 MHz.
(4)
AVCC
Parallel
BERT
RT
Data+
800-mVpp, Data–
1000-mVpp,
1200-mVpp,
Differential
Signal
Coax
Coax
SMA
(6)
RX
+EQ
SMA
HDMI Cable
<2-inch 50-W
Transmission Line
OUT
(6)
<2-inch 50-W
Transmission Line
SMA
SMA
Coax
Coax
Eye Testnnn
(2, 3)
AVCC Instrument
(1)
TMDS361B
Clk–
Coax
SMA
(6)
RX
+EQ
SMA
(5)
Coax
RT
With
Clk+
Preemphasis
RT
<2-inch 50-W
Transmission Line
OUT
(6)
<2-inch 50-W
Transmission Line
(3-dB, 120-ps
Duration
SMA
SMA
RT
Coax
Coax
Eye Testnnn
(2, 3)
Instrument
TTP1
TTP2
TTP3
TTP4
B0331-12
Figure 24. Input Pre-Emphasis Tolerance-Measurement Setup
Copyright © 2009–2011, Texas Instruments Incorporated
21
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
780 mV
200 mV
0
–200 mV
–780 mV
0
0.25 UI
0.75 UI
1.0 UI
M0146-01
Figure 25. Output-Eye Mask at TTP4
Pre-emphasis
Duration
120 ps
3-dB Pre-emphasis Level
80%
20%
VOD p-p = 800 mV–1200 mV
20%
80%
Input Signal Rise Time (20–80%)
Input Signal Fall Time (20–80%)
T0235-02
Figure 26. Acceptable Pre-Emphasis Into TMDS361B
Any input pre-emphasis higher than the input condition shown in Figure 26 can result in over-equalization and
potential system failure. During over-equalization, the TMDS361B in the setup of Figure 24 fails the output eye
mask as shown in Figure 25.
22
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
Figure 27. TMDS Data Rate of 250 Mbps
Figure 28. TMDS Data Rate of 302.4 Mbps
Figure 29. TMDS Data Rate of 360 Mbps
Figure 30. TMDS Data Rate of 540 Mbps
Copyright © 2009–2011, Texas Instruments Incorporated
23
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
24
Figure 31. TMDS Data Rate of 650 Mbps
Figure 32. TMDS Data Rate of 742.5 Mbps
Figure 33. TMDS Data Rate of 847.5 Mbps
Figure 34. TMDS Data Rate of 1080 Mbps
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
Figure 35. TMDS Data Rate of 1350 Mbps
Figure 36. TMDS Data Rate of 1485 Mbps
Figure 37. TMDS Data Rate of 1856.25 Mbps
Figure 38. TMDS Data Rate of 2227.5 Mbps
Copyright © 2009–2011, Texas Instruments Incorporated
25
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50 Ω
Figure 39. TMDS Data Rate of 2970 Mbps
26
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
Table 3. TMDS361B vs TMDS351 Pinout
PIN NUMBER
I/O
Pins 32 and 33
I
TMDS351
GPIO mode: S1 and S2 configured as
source selector pins
TMDS361B
GPIO mode: S1 and S2 configured as source selector pins (same as
TMDS351)
I2C mode: S1 and S2 configured as SCL and SDA for local slave I2C
communication
Pin 34
Pin 49
I
—
EQ: TMDS input equalization control
select
I2C_SEL: GPIO / local I2C control select
EQ = High – 10-m 28 AWG HDMI cable
I2C_SEL = High – Device is configured by GPIO logic.
EQ = Low – HDMI 1.3 compliant cable
I2C_SEL= Low – Device is configured by I2C logic.
VDD: HPD/DDC power supply
LP: Low-power mode select bar
LP = High – Normal operational mode
LP = Low – Device goes into low-power state.
Based on the differences listed in Table 3, attention must be given to pin 34, which determines whether the
device uses I2C or GPIO control.
Supply Voltage
The TMDS361B is powered up with a single power source that is 3.3-V VCC for the TMDS circuitry for HPD,
DDC, and most of the control logic.
TMDS Input Fail-Safe
The TMDS361B incorporates clock-detect circuitry. If there is no valid TMDS clock from the connected HDMI/DVI
source, the TMDS361B does not switch on the terminations on the source-side data channels. Additionally, the
TMDS outputs are placed in the high-impedance state. This prevents the TMDS361B from turning on its outputs
if there is no valid incoming HDMI/DVI data.
TMDS Outputs
A 10% precision resistor, 4.02-kΩ, is recommended to control the output swing to the HDMI-supporting 800-mV
to 1200-mV range VOD(pp) (1000 mV typical). The TMDS outputs are high-impedance under standby-mode
operation, S1 = H and S2 = L.
DDC I2C Function Description
The TMDS361B provides buffers on the DDC I2C lines on all three input ports. This section explains the
operation of the buffer. For representation, the source side of the TMDS361B is represented by RSCL/RSDA,
and the sink side is represented by TSCL/TSDA. The buffers on the RSCL/RSDA and TSCL/TSDA pins are 5-V
tolerant when the device is powered off and high-impedance under low supply voltage, 1.5 V or below. If the
device is powered up, the driver T (see Figure 40) is turned on or off depending on the corresponding R-side
voltage level.
When the R side is driven low, below 1.5 V, the corresponding T-side driver turns on and drives the T side down
to a low-level output voltage, VOL. The value of VOL and VIL on the T side or the sink side of the TMDS361B
switch depends on the output-voltage select (OVS) control settings. OVS control can be changed by the slave
I2C; see Table 8. When the OVS1 setting is selected, VOL is typically 0.7 V and VIL is typically 0.4 V. When the
OVS2 setting is selected, VOL is typically 0.6 V and VIL is typically 0.4 V. When the OVS3 setting (default) is
selected, VOL is typically 0.5 V and VIL is typically 0.3 V. VOL is always higher than the driver-R input threshold,
VIL on the T side or the sink side, preventing lockup of the repeater loop. The TMDS361B is targeted primarily as
a switch in the HDTV market and is expected to be a companion chip to an HDMI receiver; thus, the OVS control
has been provided on the sink side, so that the requirement of VIL to be less than 0.4 V can be met. The VOL
value can be selected to improve or optimize noise margins between VOL and VIL of the repeater itself or VIL of
some external device connected on the T side.
When the R side is pulled up, above 1.5 V, the T-side driver turns off and the T-side pin is high-impedance.
Copyright © 2009–2011, Texas Instruments Incorporated
27
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
OVS
T
RSCL
RSDA
TSCL
TSDA
R
B0344-01
2
Figure 40. I C Drivers in the TMDS361B (R Side Is the HDMI Source Side, T Side Is the HDMI Sink Side)
When the T side is driven below 0.4 V by an external I2C driver, both drivers R and T are turned on. Driver R
drives the R side to near 0 V, and driver T is on, but is overridden by the external I2C driver. If driver T is already
on due to a low on the R side, driver R just turns on.
When the T side is released by the external I2C driver, driver T is still on, so the T side is only able to rise to the
VOL of driver T. Driver R turns off, because VOL is above its 0.4-V VIL threshold, releasing the R side. If no
external I2C driver is keeping the R side low, the R side rises, and driver T turns off once the R side rises above
1.5 V; see Figure 41.
Vcc
TSCL/TSDA
0.5V
tPLH
5V +
10%
RSCL/RSDA
Vcc/2
Figure 41. Waveform of Driver T Turning Off
It is important that any external I2C driver on the T side is able to drive the bus below 0.4 V to achieve full
operation. If the T side cannot be driven below 0.4 V, driver R may not recognize and transmit the low value to
the R side.
DDC I2C Behavior
The typical application of the TMDS361B is as a 3×1 switch in a TV connecting up to three HDMI input sources
to an HDMI receiver. The I2C repeater is 5-V tolerant, and no additional circuitry is required to translate between
3.3-V and 5-V bus voltages. In the following example, the system master is running on an R-side I2C-bus while
the slave is connected to a T-side bus. Both buses run at 100 kHz, supporting standard-mode I2C operation.
Master devices can be placed on either bus.
VRdd
V Tdd
Driver T
RRup
RTup
Master
Slave
CSOURCE
CI
CO
Cslave
Driver R
Cmedium
CCABLE
Figure 42. Typical Application
28
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Figure 43 illustrates the waveforms seen on the R-side I2C-bus when the master writes to the slave through the
I2C repeater circuit of the TMDS361B. This looks like a normal I2C transmission, and the turnon and turnoff of the
acknowledge signals are slightly delayed.
9th Clock Pulse - Acknowledge From Slave
RSCL
RSDA
Figure 43. Bus-R Waveform
Figure 44 illustrates the waveforms seen on the T-side I2C-bus under the same operation as in Figure 43. On the
T-side of the I2C repeater, the clock and data lines would have a positive offset from ground equal to the VOL of
the driver T. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close
to ground in this example. At the end of the acknowledge, the slave device releases and the bus level rises back
to the VOL set by the driver until the R-side rises above VCC/2, after which it continues to be high. It is important
to note that any arbitration or clock-stretching events require that the low level on the T-side bus at the input of
the TMDS361B I2C repeater is below 0.4 V to be recognized by the device and then transmitted to the R-side I2C
bus.
9th Clock Pulse - Acknowledge From Slave
TSCL
TSDA
VOL Of Driver T
V OL Of Slave
Figure 44. Bus-T Waveform
I2C Pullup Resistors
The pullup resistor value is determined by two requirements:
1. The maximum sink current of the I2C buffer:
The maximum sink current is 3 mA or slightly higher for an I2C driver supporting standard-mode I2C
operation.
Rup(min) = VDD / Isink
(1)
2. The maximum transition time on the bus:
The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pullup resistor
value and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by solving for
t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce
different values of t. Table 4 summarizes the possible values of k under different threshold combinations.
t = k ´ RC
(2)
(
V(t) = VDD 1 - e- t/RC
)
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www.ti.com
Table 4. Value of k for Different Input Threshold Voltages
Vth–\Vth+
0.7 VDD
0.65 VDD
0.6 VDD
0.55 VDD
0.5 VDD
0.45 VDD
0.4 VDD
0.35 VDD
0.3 VDD
0.1 VDD
1.0986
0.9445
0.8109
0.6931
0.5878
0.4925
0.4055
0.3254
0.2513
0.15 VDD
1.0415
0.8873
0.7538
0.6360
0.5306
0.4353
0.3483
0.2683
0.1942
0.2 VDD
0.9808
0.8267
0.6931
0.5754
0.4700
0.3747
0.2877
0.2076
0.1335
0.25 VDD
0.9163
0.7621
0.6286
0.5108
0.4055
0.3102
0.2231
0.1431
0.0690
0.3 VDD
0.8473
0.6931
0.5596
0.4418
0.3365
0.2412
0.1542
0.0741
—
From Equation 1, Rup(min) = 5.5 V/3 mA = 1.83 kΩ to operate the bus under a 5-V pullup voltage and provide less
than 3 mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is
allowed, Rup(min) can be as low as 1.375 kΩ.
Given a 5-V I2C device with input low- and high-threshold voltages at 0.3 Vdd and 0.7 Vdd, respectively, the value
of k is 0.8473 from Table 4. Taking into account the 1.83-kΩ pullup resistor, the maximum total load capacitance
is C(total-5V) = 645 pF. Ccable(max) should be restricted to be less than 545 pF if Csource and Ci can be as high as 50
pF. Here the Ci is treated as Csink, the load capacitance of a sink device.
Fixing the maximum transition time from Table 4, T = 1 μs, and using the k values from Table 4, the
recommended maximum total resistance of the pullup resistors on an I2C bus can be calculated for different
system setups.
To support the maximum load capacitance specified in the HDMI spec, Ccable(max) = 700 pF/Csource = 50 pF/Ci =
50 pF, R(max) can be calculated as shown in Table 5.
Table 5. Pullup Resistor for Different Threshold Voltages and 800-pF Load
Vth–\Vth+
0.7 VDD
0.65 VDD
0.6 VDD
0.55 VDD
0.5 VDD
0.45 VDD
0.4 VDD
0.35 VDD
0.3 VDD
UNIT
0.1 VDD
1.14
1.32
1.54
1.80
2.13
2.54
3.08
3.84
4.97
kΩ
0.15 VDD
1.20
1.41
1.66
1.97
2.36
2.87
3.59
4.66
6.44
kΩ
0.2 VDD
1.27
1.51
1.80
2.17
2.66
3.34
4.35
6.02
9.36
kΩ
0.25 VDD
1.36
1.64
1.99
2.45
3.08
4.03
5.60
8.74
18.12
kΩ
0.3 VDD
1.48
1.80
2.23
2.83
3.72
5.18
8.11
16.87
—
kΩ
Or, limiting the maximum load capacitance of each cable to 400 pF to accommodate with I2C specification
version 2.1, Ccable(max) = 400 pF/Csource = 50 pF/Ci = 50 pF, the maximum values of R(max) are calculated as
shown in Table 6.
Table 6. Pullup Resistor for Different Threshold Voltages and 500-pF Load
Vth–\Vth+
0.7 VDD
0.65 VDD
0.6 VDD
0.55 VDD
0.5 VDD
0.45 VDD
0.4 VDD
0.35 VDD
0.3 VDD
UNIT
0.1 VDD
1.82
2.12
2.47
2.89
3.40
4.06
4.93
6.15
7.96
kΩ
0.15 VDD
1.92
2.25
2.65
3.14
3.77
4.59
5.74
7.46
10.30
kΩ
0.2 VDD
2.04
2.42
2.89
3.48
4.26
5.34
6.95
9.63
14.98
kΩ
0.25 VDD
2.18
2.62
3.18
3.92
4.93
6.45
8.96
13.98
28.99
kΩ
0.3 VDD
2.36
2.89
3.57
4.53
5.94
8.29
12.97
26.99
—
kΩ
Obviously, to accommodate the 3-mA drive-current specification, a narrower threshold voltage range is required
to support a maximum 800-pF load capacitance for a standard-mode I2C bus.
When the input low- and high-level threshold voltages, Vth– and Vth+, are 0.7 V and 1.9 V, respectively, which is
0.15 VDD and 0.4 VDD, approximately, then with VDD = 5 V from Table 5, the maximum pullup resistor is 3.59 kΩ.
The allowable pullup resistor is in the range of 1.83 kΩ and 3.59 kΩ.
30
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TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
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HPD Pins
The HPD circuits are powered by the 3.3-V VCC supply. This provides maximum VOH = VCC and maximum
VOL= 0.4-V output signals to the SOURCE with a typical 1-kΩ output resistance. An external 1-kΩ resistor is not
needed here. The HPD output of the selected source port follows the logic level of the HPD_SINK input.
Unselected HPD outputs are kept low. When the device is in standby mode, all HPD outputs follow HPD_SINK.
If VOH greater than VCC is desired, then an external circuit as shown in Figure 45 can be used. In this case, the
max VOH can be equal to the 5 V coming from the HDMI source.
5V_Source (5V coming from HDMI source)
VCC/5V_source
VCC
1 kW
1 kW
HPD_SOURCE
1 kW (internal
series resistor)
10 kW
HPD[1:3]
HPD_SINK
TMDS361B
VCC
HPD_SINK
HPD[1:3]
ON
L
H
HPD_SOURCE
L
ON
H
L
H
OFF
X
Z
H
S0387-08
Figure 45. External Circuit to Drive 5-V VOH on HPD[1:3]
Layout Considerations
The high-speed differential TMDS inputs are the most critical paths for the TMDS361B. There are several
considerations to minimize discontinuities on these transmission lines between the connectors and the device:
• Maintain 100-Ω differential transmission line impedance into and out of the TMDS361B.
• Keep an uninterrupted ground plane beneath the high-speed I/Os.
• Keep the ground-path vias to the device as close as possible to allow the shortest return current path.
• Keep the trace lengths of the TMDS signals between connector and device as short as possible.
• Keep intra-pair skew (trace length) between the positive and negative TMDS inputs to be matched to within 5
mils (0.005 inches or 0.127 mm).
Using the TMDS361B in Systems With Different CEC Link Requirements
The TMDS361B supports a DTV with up to three HDMI inputs when used in conjunction with a signal-port HDMI
receiver. Figure 46 and Figure 47 show simplified application block diagrams for the TMDS361B in different
DTVs with different consumer electronic control (CEC) requirements. The CEC is an optional feature of the HDMI
interface for centralizing and simplifying user control instructions from multiple audio/video products in an
interconnected system, even when all the audio/video products are from different manufacturers. This feature
minimizes the number of remote controls in a system, as well as reducing the number of times buttons must be
pressed.
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TMDS361B
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www.ti.com
A DTV Supporting a Passive CEC Link
In Figure 46, the DTV does not have the capability of handling CEC signals, but allows CEC signals to pass over
the CEC bus. The source selection is done by the control command of the DTV. The user cannot force the
command from any audio/video product on the CEC bus. The selected source reads the E-EDID data after
receiving an asserted HPD signal. The microcontroller loads different CEC physical addresses while changing
the source by means of the S1 and S2 pins.
E-EDID Reading Configurations in Standby Mode
When the DTV system is in standby mode, the sources do not read the E-EDID memory because the 1-kΩ
pulldown resistor keeping the HPD_SINK input at logic-low forces all HPD pins to output logic-low to all sources.
The source does not read the E-EDID data with a low on the HPD signal. However, if reading the E-EDID data in
the system standby mode is preferred, then the TMDS361B can still support this need.
The recommended configuration sequences are:
1. Apply the same 3.3-V power to the VCC of the TMDS361B and the TMDS line termination at the HDMI
receiver.
2. Because the TMDS361B has clock-detect circuitry and there is no valid input TMDS clock in the standby
mode, the TMDS361B draws significanty less current.
3. Set S1 and S2 to select the source port which is allowed to read the E-EDID memory.
Note that if the source has a time-out limitation between the 5-V and the HPD signals, the foregoing configuration
is not applicable. Uses individual EEPROMs assigned for each input port, see Figure 47. The solution uses
E-EDID data to be readable during system power-off or standby-mode operations.
SINK
HPD
5V
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
5V
47kW
SOURCE 1
CLK
D0
CLK
D0
D1
D2
D1
D2
HPD
5V
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
5V
CLK
D0
CLK
D0
D1
D2
D1
D2
EQ
mController
S1
S2
SDA1
SCL1
HPD2
HPD_SINK
SDA2
SCL2
SDA_SINK
SCL_SINK
CEC
5V
1kW
3.3V
4.7kW
4.7kW
DDC_SDA
DDC_SCL
E-EDID
A21/B21
A22/B22
A23/B23
A24/B24
47kW
SOURCE 3
VCC
(3.3 V)
A11/B11
A12/B12
A13/B13
A14/B14
D1
D2
HPD
5V
VDD
(5 V)
CEC
47kW
SOURCE 2
HPD1
HDMI RX
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
HPD3
VSADJ
SDA3
SCL3
4.02 kW 10%
CEC
A31/B31
A32/B32
A33/B33
A34/B34
GND
Figure 46. Three-Port HDMI-Enabled DTV With TMDS361B – CEC Commands Passing Through
32
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TMDS361B
www.ti.com
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
A DTV Supporting an Active CEC Link
In Figure 47, the CEC PHY and CEC LOGIC functions are added. The DTV can initiate and/or react to CEC
signals from its remote control or other audio/video products on the same CEC bus. All sources must have their
own CEC physical address to support the full functionality of the CEC link.
A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD
feedback. When HPD is high, the sink-assigned CEC physical address should be maintained. Otherwise, when
HPD is low, the source sets the CEC physical address value to (F.F.F.F).
Case 1 – AC-Coupled Source (See Figure 47, Port 1)
When the source TMDS lines are ac-coupled or when the source cannot detect the TMDS termination provided
in the connected sink, the indication of the source selection can only come from the HPD signal. The TMDS361B
HPD1 pin should be applied directly as the HPD signal back to the source.
Case 2 – DC-Coupled Source (See Figure 47, Port 2)
When the source TMDS lines are dc-coupled, there are two methods to inform the source that it is the active
source to the sink. One is checking the HPD signal from the sink, and the other is checking the termination
condition in the sink.
In a full-CEC operation mode, the HPD signal is set high whether the port is selected or not. The source loads
and maintains the CEC physical address when HPD is high. As soon as HPD goes low, the source loses the
CEC physical address. To keep the CEC physical address to the source, the HPD signal loops back from the
source-provided 5-V signal through a 1-kΩ pullup resistor in the sink. This method is acceptable in applications
where the HDMI transmitter can detect the receiver termination by current sensing and the receiver has
switchable termination on the TMDS inputs. The internal termination resistors are connected to the termination
voltage when the port is selected, or they are disconnected when the port is not selected. The TMDS361B
features switchable termination on the TMDS inputs.
Case 3 – External Logic Control for HPD (See Figure 47, Port 3)
When the HDMI transmitter does not have the capability of detecting the receiver termination, using the HPD
signal as a reference for sensing port selections is the only possible method. External control logic for switching
the connections of the HPD signals between the HPD pins of the TMDS361B and the 5-V signal from the source
provides a good solution.
E-EDID Reading Configurations in Standby Mode
When the TMDS361B is in standby mode operation, S1 = H and S2 = L, all sources can read their E-EDID
memories simultaneously with all HPD pins following HPD_SINK in logic-high. HPD_SINK input low prevents
E-EDID reading in standby-mode operation. See Figure Figure 47.
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33
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
SINK
HPD
5V
SOURCE 1
With AC Coupled
HDMI Output
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
CLK
D0
D1
D2
HPD1
5V
47kW
VDD
(5 V)
VCC
(3.3 V)
SDA1
SCL1
SDA SCL
EQ
mController
S1
S2
CEC
LOGIC
CEC E-EDID
A11/B11
A12/B12
A13/B13
A14/B14
D1
D2
CEC
PHY
HPD
5V
SOURCE 2
With DC Coupled
HDMI Output
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
CLK
D0
D1
D2
SOURCE 3
in General
HDMI Output
HPD
5V
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
D1
D2
HPD2
HPD_SINK
SDA2
SCL2
3.3V
4.7kW
4.7kW
DDC_SDA
SDA_SINK
DDC_SCL
SCL_SINK
1 kW
1 kW
CEC E-EDID
A21/B21
A22/B22
A23/B23
A24/B24
D1
D2
HPD
5V
CLK
D0
5V
47kW
5V
47kW
HDMI RX
HPD3
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
SDA3
SCL3
VSADJ
1k W
4.02 k W 10%
CEC E-EDID
CLK
D0
D1
D2
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
A31/B31
A32/B32
A33/B33
A34/B34
GND
Figure 47. Three-Port HDMI-Enabled DTV With TMDS361B – CEC Commands Active
I2C INTERFACE NOTES
The I2C interface is used to access the internal registers of the TMDS361B. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device. The TMDS361B works as a slave and supports standard-mode transfer (100
kbps).
The basic I2C start and stop access cycles are shown in Figure 48.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
34
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
SDA
SDA
SCL
SCL
S
P
Start
Condition
Stop
Condition
T0393-01
2
Figure 48. I C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
•
•
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 48. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 49). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 50) by driving the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver must acknowledge the data sent by the transmitter. So an
acknowledge signal can be generated either by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (See Figure 52 through Figure 55).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 48). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
T0394-01
2
Figure 49. I C Bit Transfer
Copyright © 2009–2011, Texas Instruments Incorporated
35
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
T0395-01
Figure 50. I2C Acknowledge
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
MSB
Acknowledge
Slave Address
Stop
Acknowledge
Data
T0396-01
Figure 51. I2C Address, Data Cycle(s), and Stop
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 52 and Figure 53.
Note that the TMDS361B allows multiple write transfers to occur. See the Example – Writing to the TMDS361A
section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 54 and Figure 55.
See the Example – Reading from the TMDS361A section for more information.
From Receiver
S
Slave Address
W
A
Data
A
Data
A
P
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
From Transmitter
R0007-01
Figure 52. I2C Write Cycle
36
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Acknowledge
(From Receiver)
Start
Condition
A5
A6
SDA
A1
A0
R/W ACK
D7
2
I C Device Address and
Read/Write Bit
Acknowledge
(Receiver)
D6
D0 ACK
D1
First Data Byte
Acknowledge
(Receiver)
D7
D6
D1
D0 ACK
Stop
Condition
Other Last Data Byte
Data Bytes
T0397-01
Figure 53. Multiple-Byte Write Transfer
S
R
Slave Address
A
Data
Data
A
A
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
Transmitter
Receiver
R0008-01
2
Figure 54. I C Read Cycle
A0 R/W ACK
A6
SDA
Not Acknowledge
(Transmitter)
Acknowledge
Acknowledge
(From Receiver) (From Transmitter)
Start
Condition
2
I C Device Address and
Read/Write Bit
D7
D0
ACK
D7
D6
D1
D0
First Data
Other Last Data Byte
Byte
Data Bytes
ACK
Stop
Condition
T0398-01
Figure 55. Multiple-Byte Read Transfer
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via pullup resistors. These resistors should
comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7-bit address is
factory preset to 0101 100. Table 7 lists the calls to which the TMDS361B responds.
Table 7. TMDS361B Slave Address
FIXED ADDRESS
READ/WRITE BIT
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (R/W)
0
1
0
1
1
0
0
1/0
EXAMPLE – WRITING TO THE TMDS361B
The proper way to write to the TMDS361B is illustrated as follows:
An I2C master initiates a write operation to the TMDS361B by generating a start condition (S) followed by the
TMDS361B I2C address (as shown following, in MSB-first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TMDS361B, the master presents the subaddress (sink port) to be written,
consisting of one byte of data, MSB-first. The TMDS361B acknowledges the byte after completion of the transfer.
Finally, the master presents the data to be written to the register (sink port), and the TMDS361B acknowledges
the byte. The master can continue presenting data to be written after the TMDS361B acknowledges the previous
byte (steps 6, 7). After the last byte to be written has been acknowledged by the TMDS361B, the I2C master then
terminates the write operation by generating a stop condition (P).
Step 1
0
I2C start (master)
S
Copyright © 2009–2011, Texas Instruments Incorporated
37
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
0
1
0
1
1
0
0
0
Step 3
8
I2C acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C write sink logic address (master)
0
0
0
0
Addr
Addr
Addr
Addr
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Step 5
8
I2C acknowledge (slave)
A
Step 6
2
I C write data (master)
Data is the register address or register data to be written.
Step 7
8
I2C acknowledge (slave)
A
Step 8
0
I2C stop (master)
P
An example of the proper bit control for selecting port 2 is:
Step 4: 0000 0001
Step 6: 1001 0000
EXAMPLE – READING FROM THE TMDS361B
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the TMDS361B by generating a start condition (S) followed by the TMDS361B I2C
address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
TMDS361B, the master presents the subaddress of the register to be read. After the cycle is acknowledged (A),
the master may optionally terminate the cycle by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TMDS361B by
generating a start condition followed by the TMDS361B I2C address (as shown following for a read operation), in
MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS361B, the I2C
master receives one byte of data from the TMDS361B. The master can continue receiving data byes by issuing
an acknowledge after each byte read (steps 10, 11). After the last data byte has been transferred from the
TMDS361B to the master, the master generates a not-acknowledge followed by a stop.
TMDS361B Read Phase 1
Step 1
0
I2C start (master)
S
Step 2
2
I C general address (master)
7
6
5
4
3
2
1
0
0
1
0
1
1
0
0
0
Step 3
8
I2C acknowledge (slave)
A
38
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Step 4
7
6
5
4
3
2
1
0
I2C write sink logic address (master)
0
0
0
0
Addr
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 7.
Step 5
8
I2C acknowledge (slave)
A
Step 6
0
2
I C stop (master)
P
Step 6 is optional.
TMDS361B Read Phase 2
Step 7
0
I2C start (master)
S
Step 8
2
I C general address (master)
7
6
5
4
3
2
1
0
0
1
0
1
1
0
0
1
Step 9
8
2
I C acknowledge (slave)
A
Step 10
I2C read data (slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the logic values contained in the internal registers.
Step 11A
8
I2C acknowledge (master)
A
If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12.
Step 11B
8
I2C not-acknowledge (master)
A
Step 12
0
2
I C stop (master)
P
Table 8. I2C Register 0x01 Lookup Table
BIT
VALUE
STATE
7:6
Bit 7
Bit 6
1
1
1
0
Port 2 is selected as the active port; HPD on non-selected ports is low. HPD2 can go low, high
or high-Z.
0
0
Port 3 is selected as the active port; HPD on non-selected ports is low. HPD3 can go low, high
or high-Z.
Standby mode: HPD[1:3] follow HPD_SINK.
5:4
0
1
Bit 4
Bit 3
0
0
0
1
1
1
DEFAULT
DESCRIPTION
Port Select I2C Mode
X
Port 1 is selected as the active port; HPD on non-selected ports is low. HPD1 can go low, high
or high-Z.
OVS Control
OVS2: DDC sink-side VOL and VIL offset range 2: VIL2 (max): 0.4 V, VOL2 (max): 0.6 V
X
OVS3: DDC sink-side VOL and VIL offset range 3: VIL3 (max): 0.3 V, VOL3 (max): 0.5 V
OVS1: DDC sink-side VOL and VIL offset range 1: VIL1 (max): 0.4 V, VOL1 (max): 0.7 V
Copyright © 2009–2011, Texas Instruments Incorporated
39
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Table 8. I2C Register 0x01 Lookup Table (continued)
BIT
VALUE
STATE
3:2
Bit 3
Bit 2
1
1
Fastest TMDS output rise- and fall-time setting + 120 ps approximately (slowest rise- and
fall-time setting)
1
0
Fastest TMDS output rise- and fall-time setting + 100 ps approximately
0
1
0
0
Bit 1
Bit 0
1
0
Device enters low-power mode.
1
1
Device enters low-power mode.
0
1
0
0
1:0
DEFAULT
DESCRIPTION
Output Edge Rate Control
Fastest TMDS output rise- and fall-time setting + 50 ps approximately
X
Fastest TMDS output rise- and fall-time setting
Power Mode
Reserved
X
Device is in normal-power mode.
Register 0x01 is read/write.
Table 9. I2C Register 0x02 Lookup Table
BIT
VALUE
STATE
7:6
Bit 7
Bit 6
1
1
1
0
Indicates port 2 is selected as the active port, all other ports are low.
0
0
Indicates port 3 is selected as the active port, all other ports are low.
0
1
Indicates standby mode: HPD[1:3] follow HPD_SINK.
Bit 4
Bit 3
0
0
0
1
5:4
3:2
1:0
DEFAULT
DESCRIPTION
Port Select Status Indicator
X
Indicates port 1 is selected as the active port, all other ports are low.
OVS Control Status Indicator
Indicates DDC sink side VOL and VIL offset range 2: VIL2 (max): 0.4 V, VOL2 (max): 0.6 V
X
Indicates DDC sink side VOL and VIL offset range 3: VIL3 (max): 0.3 V, VOL3 (max): 0.5 V
1
1
Bit 3
Bit 2
Indicates DDC sink side VOL and VIL offset range 1: VIL1 (max): 0.4 V, VOL1 (max): 0.7 V
1
1
Indicates fastest TMDS output rise- and fall-time setting + 120 ps approximately (slowest rise
and fall time setting)
1
0
Indicates fastest TMDS output rise- and fall-time setting + 100 ps approximately
0
1
0
0
Bit 1
Bit 0
1
0
Indicates device enters low-power mode
1
1
Indicates device enters low-power mode
0
1
0
0
Output Edge Rate Status Control
Indicates fastest TMDS output rise- and fall-time setting + 50 ps approximately
X
Indicates fastest TMDS output rise- and fall-time setting
Power Mode Status Indicator
Reserved
X
Indicates device is in normal-power mode
Register 0x02 is read-only.
Table 10. I2C Register 0x03 Lookup Table
BIT
VALUE
STATE
7
1
Clock
detect
disabled
0
Clock
detect
enabled
6:5
X
RSVD
4
0
RSVD
X
Note: Do not write a 1 to this bit.
3:0
0
RSVD
X
Reserved
40
DEFAULT
DESCRIPTION
Clock-detect circuit disabled. For HDMI compliance testing (TMDS termination-voltage test), the
clock-detect feature should be disabled. In this mode, the terminations on the TMDS input data
lines are always connected when the port is selected.
X
Clock-detect circuit enabled. It is recommended that TMDS361B is used in this default mode
during normal operation where the clock detect circuit is enabled. The terminations on the
TMDS input data lines are connected only when a valid TMDS clock is detected on the selected
port.
Reserved
Copyright © 2009–2011, Texas Instruments Incorporated
TMDS361B
www.ti.com
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
Register 0x03 is read/write, For disabling clock detect, value of 80h or 1000 0000b can be written to register
0x03.
Copyright © 2009–2011, Texas Instruments Incorporated
41
TMDS361B
SLLS988A – SEPTEMBER 2009 – REVISED JULY 2011
www.ti.com
Table 11. I2C Register 0x04 Lookup Table
BIT
VALUE
STATE
7
1
Clock
detected
DEFAULT
DESCRIPTION
0
No clock
detect
6:5
X
RSVD
4
0
RSVD
X
This bit should always read 0
3:0
0
RSVD
X
Reserved
A valid clock signal is detected on the selected port. If clock detect is disabled in register
0x03, then bit 7 of register 0x04 is always 1.
X
The selected port does not have a valid clock signal.
Reserved
Register 0x04 is read-only.
Table 12. I2C Register 0x05 Lookup Table
BIT
VALUE
STATE
DEFAULT
7:0
—
RSVD
X
DESCRIPTION
Reserved. Read-only, value is indeterministic.
Register 0x05 is TI internal use only.
Table 13. I2C Register 0x06 Lookup Table
BIT
VALUE
STATE
DEFAULT
7:0
—
RSVD
X
DESCRIPTION
Reserved. Read-only, value is indeterministic.
Register 0x06 is TI internal use only.
Table 14. I2C Register 0x07 Lookup Table
BIT
VALUE
STATE
DEFAULT
7:0
—
RSVD
X
DESCRIPTION
Reserved. Read-only, value is indeterministic.
Register 0x07 is TI internal use only.
SPACER
REVISION HISTORY
Changes from Original (September 2009) to Revision A
•
42
Page
Added Junction Temperature to the THERMAL CHARACTERISTICS table ....................................................................... 9
Copyright © 2009–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TMDS361BPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TMDS361B
TMDS361BPAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TMDS361B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TMDS361BPAGR
Package Package Pins
Type Drawing
TQFP
PAG
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1500
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMDS361BPAGR
TQFP
PAG
64
1500
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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