Texas Instruments | SN65LVDS125A, SN65LVDT125A - LVDS 4x4 Crosspoint Switch (Rev. C) | Datasheet | Texas Instruments SN65LVDS125A, SN65LVDT125A - LVDS 4x4 Crosspoint Switch (Rev. C) Datasheet

Texas Instruments SN65LVDS125A, SN65LVDT125A - LVDS 4x4 Crosspoint Switch (Rev. C) Datasheet
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
LVDS 4x4 CROSSPOINT SWITCH
Check for Samples: SN65LVDT125A, SN65LVDS125A
FEATURES
1
•
•
•
•
•
•
•
•
•
Signaling Rates >1.5 Gbps per Channel
Supports Telecom/Datacom and HDTV
Video Switching
Non-Blocking Architecture Allows Each
Output to be Connected to Any Input
Compatible With ANSI TIA/EIA-644-A LVDS
Standard
25 mV of Input Voltage Threshold Hysteresis
Propagation Delay Times, 900 ps Typical
Inputs Electrically Compatible With LVPECL,
CML and LVDS Signal Levels
Operates From a Single 3.3-V Supply
Integrated 110-Ω Line Termination Resistors
Available With SN65LVDT125A
APPLICATIONS
•
•
•
•
Clock Buffering/Clock Muxing
Wireless Base Stations
High-Speed Network Routing
HDTV Video Switching
SN65LVDS125ADBT ( Marked as LVDS125A)
SN65LVDT125ADBT ( Marked as LVDT125A)
(TOP VIEW)
S10
S11
1A
1B
S20
S21
2A
2B
GND
VCC
GND
3A
3B
S30
S31
4A
4B
S40
S41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VCC
GND
1Y
1Z
1DE
2Y
2Z
2DE
GND
VCC
GND
3Y
3Z
3DE
4Y
4Z
4DE
GND
VCC
Eye Pattern of Two Outputs
Operating Simultaneously
The SN65LVDS125A and SN65LVDT125A are 4x4
nonblocking
crosspoint
switches.
Low-voltage
differential signaling (LVDS) is used to achieve
signaling rates of 1.5 Gbps per channel. Each output
driver includes a 4:1 multiplexer to allow any input to
be routed to any output. Internal signal paths are fully
differential to achieve the high signaling speeds while
maintaining low signal skews. The SN65LVDT125A
incorporates 110-Ω termination resistors for those
applications where board space is a premium.
Designed to support signaling rates up to 1.5 Gbps
for OC-12 clocks (622 MHz). The 1.5-Gbps signaling
rate allows use in HDTV systems, including SMPTE
292 video applications requiring signaling rates of
1.485 Gbps.
The SN65LVDS125A and SN65LVDT125A
characterized for operation from -40°C to 85°C.
175 mV/div
DESCRIPTION
VIC = 1.2 V
SVIDS = 200 mV
1.5 Gbps
223-1 PRBS
VCC = 3.3 V
200 - ps/div
are
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM
8
S10 - S41
1DE
1A
1Y
1B
1Z
2DE
2A
2Y
2B
2Z
4X4
MUX
3DE
3A
3Y
3B
3Z
4DE
4A
4Y
4B
4Z
Integrated 110-W Termination on LVDT Only
SN65LVDS125A Pin Description
Pin Numbers
Pin Description
S10 - S41
Inputs; Input channel to out output channel selection control pins
1A, 2A, 3A, 4A
Inputs; Positive leg of LVDS data input
1B, 2B, 3B, 4B
Inputs; Negative leg of LVDS data input
1Y, 2Y, 3Y, 4Y
Outputs; Positive leg of LVDS data output
1Z, 2Z, 3Z, 4Z
Outputs; Negative leg of LVDS data output
1DE, 2DE, 3DE, 4DE
Inputs; Output port disable
VCC
Input Voltage
GND
Ground
2
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT LVDS125A
VCC
A
VCC
B
7V
7V
VCC
VCC
300 kΩ
DE
S10, S41
400 Ω
400 Ω
300 kΩ
7V
7V
OUTPUT LVDS125A
VCC
VCC
VCC
Y
7V
Copyright © 2003–2011, Texas Instruments Incorporated
Z
7V
3
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
Table 1. CROSSPOINT LOGIC TABLES
OUTPUT CHANNEL 1
CONTROL
PINS
OUTPUT CHANNEL 2
INPUT
SELECTED
CONTROL
PINS
OUTPUT CHANNEL 3
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
OUTPUT CHANNEL 4
CONTROL
PINS
INPUT
SELECTED
S10
S11
1Y/1Z
S20
S21
2Y/2Z
S30
S31
3Y/3Z
S40
S41
4Y/4Z
0
0
1A/1B
0
0
1A/1B
0
0
1A/1B
0
0
1A/1B
0
1
2A/2B
0
1
2A/2B
0
1
2A/2B
0
1
2A/2B
1
0
3A/3B
1
0
3A/3B
1
0
3A/3B
1
0
3A/3B
1
1
4A/4B
1
1
4A/4B
1
1
4A/4B
1
1
4A/4B
PACKAGE DISSIPATION RATINGS
PACKAGE
CIRCUIT BOARD
MODEL
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
TSSOP (DBT)
High-K (2)
1772 mW
15.4 mW/°C
847 mW
(1)
(2)
This is the inverse of the junction-to-ambient thermal resistance when board-mounded and with no air flow.
In accordance with the High-K thermal metric definitions of EIA/JESD51-6.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
θJB
Junction-to-board thermal resistance
40.3
θJC
Junction-to-case thermal resistance
8.5
PD
Device power dissipation
UNITS
°C/W
Typical
VCC = 3.3 V, TA = 25°C, 750 MHz
356
mW
Maximum
VCC = 3.6 V, TA = 85°C, 750 MHz
522
mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNITS
Supply voltage range, Vcc
Voltage range (2)
-0.5 V to 4 V
S, DE
-0.5 V to 4 V
(A, B)
-0.5 V to 4 V
|VA - VB| (LVDT only)
1V
(Y, Z)
Electrostatic discharge
Continuous power dissipation
Storage temperature range
(1)
(2)
(3)
(4)
4
-0.5 V to 4 V
Human body model (3)
All pins
±3 kV
Charged-device model (4)
All pins
±500 V
See Dissipation Rating Table
-65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage, VCC
3
High-level input voltage, VIH
S10-S41, 1DE-4DE
Low-level input voltage, VIL
S10-S41, 1DE-4DE
Magnitude of differential input voltage |VID|
3.3
V
LVDS
0.1
LVDT
0.1
0.8
V
V
0
3.3
V
140
°C
85
°C
Junction temperature, TJ
(1)
V
V
0.8
Input voltage (any combination of common-mode or input signals)
Operating free-air temperature, TA
3.6
2
(1)
-40
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
TIMING SPECIFICATIONS
PARAMETER
tSET
Input to select setup time
tHOLD
Input to select hold time
tSWITCH
Select to switch output
MIN
NOM
MAX UNIT
0.6
See Figure 7
ns
0.2
1.2
ns
1.6
ns
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted (1)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input voltage
threshold
See Figure 1
VIT-
Negative-going differential input voltage
threshold
See Figure 1
VID(HYS)
Differential input voltage hysteresis
1DE-4DE
MIN TYP (1)
MAX
UNIT
100
mV
-100
mV
25
mV
-10
High-level input current
IIL
Low-level input current
II
Input current
VI = 0 V or 3.3 V, Second input at 1.2 V (other
input open for LVDT)
-20
20
µA
II(OFF)
Input current
VCC ≤ 1.5 V, VI = 0 V or 3.3 V, Second input at
1.2 V (other input open for LVDT)
-20
20
µA
IIO
Input offset current (|IIA - IIB|) ('LVDS)
VIA = VIB, 0 ≤ VIA≤ 3.3 V
-6
6
µA
Termination resistance ('LVDT)
VID = 300 mV, VIC = 0 V to 3.3 V
90
110
132
RT
Termination resistance('LVDT with
power-off)
VID = 300 mV, VIC = 0 V to 3.3 V, VCC= 1.5 V
90
110
132
CT
Differential input capacitance
(1)
S10-S41
1DE-4DE
S10-S41
VIH = 2 V
µA
IIH
20
-10
VIL = 0.8 V
20
0.6
µA
Ω
pF
All typical values are at 25°C and with a 3.3 V supply.
Copyright © 2003–2011, Texas Instruments Incorporated
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SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
247
350
454
mV
-50
50
mV
1.125
1.375
-50
50
mV
50
150
mV
107
|VOD|
Differential output voltage magnitude
Δ|VOD|
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode output voltage
between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
ICC
Supply current
RL = 100 Ω, CL = 1 pF
145
mA
IOS
Short-circuit output current
VOY or VOZ = 0 V
-27
27
mA
IOSD
Differential short circuit output current
VOD = 0 V
-12
12
mA
IOZ
High-impedance output current
VO = 0 V or VCC
-1
±1
µA
CO
Differential output capacitance
(1)
See Figure 2,
VID = ±100 mV
See Figure 3
1.2
V
pF
All typical values are at 25°C and with a 3.3 V supply.
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Differential output signal rise time (20%-80%)
tf
Differential output signal fall time (20%-80%)
tsk(p)
Pulse skew (|tPHL - tPLH|) (1)
tsk(o)
Channel-to-channel output skew (2)
tsk(pp)
Part-to-part skew
See Figure 4
Period jitter, rms (1 standard deviation)
tjit(cc)
Cycle-to-cycle jitter (peak) (4)
(4)
750 MHz clock input (5)
(see Figure 6)
750 MHz clock input (6)
(see Figure 6)
23
1.5 Gbps 2 -1 PRBS input
(see Figure 6)
tjit(det)
Deterministic jitter, peak-to-peak (4)
1.5 Gbps 27-1 PRBS input (8)
(see Figure 6)
tPHZ
Propagation delay, high-level-to-high-impedance output
tPLZ
Propagation delay, low-level-to-high-impedance output
tPZH
Propagation delay, high-impedance -to-high-level output
tPZL
Propagation delay, high-impedance-to-low-level output
6
1200
700
900
1200
210
270
210
270
UNIT
ps
50
ps
150
ps
300
ps
0.4
3
ps
4.7
13
ps
65
110
ps
56
90
ps
(7)
Peak-to-peak jitter (4)
(5)
(6)
(7)
(8)
MAX
900
0
tjit(pp)
(4)
TYP
700
(3)
tjit(per)
(1)
(2)
(3)
MIN
6
See Figure 5
6
300
ns
300
tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Jitter specifications are based on design and characteriztion. Stimulus system jitter of 1.9 ps tjit(per), 16 ps tjit(cc). 17 ps tjit(pp), and 7.2 ps
tjit(det) have been subtracted from the values.
Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf= 50 ps (20% to 80%), measured over 1000 samples.
Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf= 50 ps (20% to 80%).
Input voltage = VID = 200 mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples.
Input voltage = VID = 200 mV, 27-1 PRBS pattern at 1.5 Gbps, tr= tf = 50 ps (20% to 80%).
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
IIA
A
Y
VID
VIC
VIA+VIB
VOD
VIA
B
VIB
2
VOY
Z
VOY+VOZ
VOZ
IIB
2
Figure 1. Voltage and Current Definitions
3.75 kΩ
Y
VOD
Z
+
_
100 Ω
0 V ≤ V(test) ≤ 2.4 V
3.75 kΩ
Figure 2. Differential Output Voltage (VOD) Test Circuit
A
Y
A
≈1.4 V
B
≈1 V
49.9 Ω ±1%
VID
VOC(PP)
B
Z
1 pF
49.9 Ω ±1%
VOC
VOC(SS)
VOC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100W; CL includes instrumentation and fixture capacitance within
0,06 mm of the D.U.T.; the measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300
MHz.
Figure 3. Test Circuit and Definitions fot the Driver Common-Mode Output Voltage
A
VID
VIA
B
VIB
Y
1 pF
VOY
Z
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
-0.4 V
100 Ω
VOZ
tPHL
tPLH
0V
Differential
80%
VOY - VOZ
20%
tf
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ .25 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Timing Test Circuit and Waveforms
Copyright © 2003–2011, Texas Instruments Incorporated
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SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω ±1%
Y
1 V or 1.4 V
1 pF
1.2 V
49.9 Ω ±1%
VOY
Z
DE
1.2 V
VOZ
3V
1.5 V
0V
DE
1.4 V
1.25 V
1.2 V
VOY or VOZ
tPZH
tPHZ
1.2 V
1.15 V
1V
VOZ or VOY
tPZL
tPLZ
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
VA
0V
VB
Clock Input
0V
Ideal Output
VY - VZ
1/fo
1/fo
Period Jitter
Cycle-to-Cycle Jitter
Actual Output
Actual Output
0V
0V
VY - VZ
tc(n)
VY - VZ
tc(n)
tc(n +1)
tjit(cc) = | tc(n) - tc(n + 1) |
tjit(pp) = | tc(n) - 1/fo |
Peak-to-Peak Jitter
VA
PRBS Input
0V
VB
VY
PRBS Output
0V
VZ
tjit(pp)
NOTE: All input pulses are supplied by an Agilent 81250 Stimulus System. The measurement is made on a TEK TDS6604
running TDSJIT3 application software.
Figure 6. Driver Jitter Measurement Waveforms
8
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A/B
A/B
S
tSET
tHOLD
OUT
Y/Z
Y/Z
tSWITCH
DE
A/B
A/B
S
tSET
OUT
tHOLD
Y/Z
Y/Z
tSWITCH
DE
NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 7. Input to Select for Both Rising and Falling Edge Setup and Hold Times
Copyright © 2003–2011, Texas Instruments Incorporated
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SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
105
100
940
tPHL
880
tPLH
820
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
f = 1 MHz
760
-45
100 200 300 400 500 600 700 800
f - Frequency - MHz
tPLH
820
VCC = 3.3 V
TA = 25°C
VID = 200 mV
f = 1 MHz
760
-25
-5
15
35
55
75
0
95
0.5
1
1.5
2
2.5
3
3.5
VIC - Common-Mode Input Voltage - V
Figure 8.
Figure 9.
Figure 10.
PEAK-TO-PEAK JITTER
vs
FREQUENCY
PEAK-TO0PEAK JITTER
vs
DATA RATE
PEAK-TO-PEAK JITTER
vs
FREQUENCY
20
120
100
VID = 800 m V
VID =200 m V
8
4
Peak-To-Peak Jitter - ps
12
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = PRBS 223-1
16
80
VID = 400 m V
60
VCC = 3.3 V
TA = 25°C
VIC= 1.2 mV
Input = Clock
VID = 800 m V
Peak-To-Peak Jitter - ps
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
40
VID =200 m V
12
VID = 400 m V
8
4
20
VID = 800 m V
VID = 400 m V
VID =200 m V
0
0
100
0
0
200 300 400 500 600 700 800
0
200 400 600 800 1000 1200 1400 1600
0
Data Rate - Mbps
f - Frequency - MHz
Figure 11.
Figure 12.
Figure 13.
PEAK-TO-PEAK JITTER
vs
DATA RATE
PEAK-TO0PEAK JITTER
vs
FREQUENCY
PEAK-TO-PEAK JITTER
vs
DATA RATE
120
20
80
VID = 400 m V
60
40
20
VID =200 m V
0
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = Clock
16
VID =200 m V
12
VID = 800 m V
8
VID = 400 m V
4
200 400 600 800 1000 1200 1400 1600
Data Rate - Mbps
Figure 14.
VID = 800 m V
80
VID =200 m V
60
40
VID = 400 m V
20
0
0
0
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = PRBS 223-1
100
Peak-To-Peak Jitter - ps
VID = 800 m V
Peak-To-Peak Jitter - ps
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Input = PRBS 223-1
100
100 200 300 400 500 600 700 800
f - Frequency - MHz
120
Peak-To-Peak Jitter - ps
880
TA - Free-Air Temperature - °C
20
16
tPHL
940
700
700
0
10
t pd - Propagation Delay Time - ps
110
95
Peak-To-Peak Jitter - ps
1000
1000
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID = 200 mV
t pd - Propagation Delay Time - ps
I CC - Supply Current - mA
115
PROPAGATION DELAY TIME
vs
COMMON-MODE INPUT VOLTAGE
0
100
200 300
400 500
f - Frequency - MHz
Figure 15.
600 700 800
0
200 400 600 800 1000 1200 1400 1600
Data Rate - Mbps
Figure 16.
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
PEAK-TO-PEAK JITTER
vs
DATA RATE
140
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
Input = 1.5 Gbps
PRBS 223-1
72
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
TA = 25°C
Input = PRBS 223-1
120
Peak-To-Peak Jitter - ps
Peak-To-Peak Jitter - ps
80
64
56
100
80
60
40
48
20
0
40
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
Figure 17.
Copyright © 2003–2011, Texas Instruments Incorporated
100
0
500
1000
1500
2000
2500
Data Rate - Mbps
Figure 18.
11
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
APPLICATION INFORMATION
CONFIGURATION EXAMPLES
S10
0
S30
1
S11
0
S31
0
S20
0
S40
1
S21
1
S41
1
S10
0
S30
0
S20
0
S40
0
S21
0
S41
0
1A
1Y
1A
1Y
1B
1Z
1B
1Z
2A
2Y
2Y
2B
2Z
2Z
3A
3Y
3Y
3B
3Z
3Z
4A
4Y
4Y
4B
4Z
4Z
S10
0
S30
1
S11
0
S31
0
S20
0
S40
1
S21
0
S41
0
S10
1
S30
0
S11
1
S31
0
S20
1
S40
0
S21
1
S41
0
1A
1Y
1A
1Y
1B
1Z
1B
1Z
2Y
2Y
2Z
2Z
12
S11
0
S31
0
3A
3Y
3Y
3B
3Z
3Z
4Y
4A
4Y
4Z
4B
4Z
Copyright © 2003–2011, Texas Instruments Incorporated
SN65LVDT125A
SN65LVDS125A
SLLS595C – OCTOBER 2003 – REVISED JUNE 2011
www.ti.com
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
50 Ω
3.3 V or 5 V
3.3 V
SN65LVDS125A
A
ECL
B
50 Ω
50 Ω
50 Ω
VTT = VCC -2 V
VTT
Figure 20. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
3.3 V
50 Ω
3.3 V
SN65LVDS125A
A
CML
B
50 Ω
50 Ω
3.3 V
Figure 21. Current-Mode Logic (CML)
3.3 V
3.3 V
50 Ω
SN65LVDS125A
A
ECL
B
50 Ω
1.1 kΩ
VTT
1.5 kΩ
VTT = VCC -2 V
3.3 V
Figure 22. Single-Ended (LVPECL)
3.3 V or 5 V
50 Ω
3.3 V
SN65LVDS125A
A
100 Ω
LVDS
B
50 Ω
Figure 23. Low-Voltage Differential Signaling (LVDS)
See the EVM Users Guide (SLLU064) for example board layout and schematics examples.
Copyright © 2003–2011, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65LVDS125ADBT
ACTIVE
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDS125A
SN65LVDS125ADBTR
ACTIVE
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDS125A
SN65LVDS125ADBTRG4
ACTIVE
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDS125A
SN65LVDT125ADBT
ACTIVE
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDT125A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65LVDS125ADBTR
Package Package Pins
Type Drawing
TSSOP
DBT
38
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDS125ADBTR
TSSOP
DBT
38
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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