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Texas Instruments Two Channel SATA 3 Gbps Redriver with Cable Detect Datasheet
SN75LVCP412CD
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Two Channel SATA 3 Gbps Redriver With Cable Detect
Check for Samples: SN75LVCP412CD
FEATURES
1
•
•
•
•
•
•
Fully Integrated Cable Detect Feature
Compliant with SATA 2.6 Spec
Enables System Power Savings of up to
200mW When HDD is Not Detected at eSATA
Connector
Low Device Power
– <200mW (Typ) in Active Mode
– <20mW (Typ) in Auto Low Power Mode
– <2mW (Max) in Standby Mode
Supports Common Mode Biasing for OOB
Signaling with Fast Turn-On
Channel Selectable Output Pre-Emphasis
Excellent Jitter and Loss Compensation
•
•
•
Capability to Over 20" FR4 Trace
High Protection Against ESD Transient
– HBM: 8,000V
– CDM: 1,500V
– MM: 200V
20 Pin QFN 4x4 Package
Pin Compatible to
LVCP412/LVCP412A
APPLICATIONS
•
Notebooks, Desktops, Docking Stations,
Servers and Workstations
DESCRIPTION
The SN75LVCP412CD is a dual channel, single lane SATA redriver and signal conditioner supporting data rates
up to 3.0Gbps that complies with SATA spec revision 2.6.
The SN75LVCP412CD operates from a single 3.3V supply. Integrated 100-Ω line termination and self-biasing
make the device suitable for AC coupling. The inputs incorporate an OOB detector which automatically turns the
differential outputs off while maintaining a stable output common-mode voltage compliant to SATA link. The
device is also designed to handle SSC transmission per SATA spec.
The SN75LVCP412CD handles interconnect losses at both its input and output. The built-in transmitter
pre-emphasis feature is capable of applying 0dB or 2.5dB of relative amplification at higher frequencies to
counter the expected interconnect loss. On the receive side the device applies a fixed equalization of 7dB to
boost input frequencies near 1.5GHz. Collectively, the input equalization and output pre-emphasis features of the
device works to fully restore SATA signal integrity over extended cable and backplane pathways.
The device is hot-plug capable(1) preventing device damage under device hot-insertion such as async signal
plug/removal, un-powered plug/removal, powered plug/removal or surprise plug/removal.
(1) Requires use of AC coupling capacitors at differential inputs and outputs
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
SN75LVCP412CDRTJR
412CD
20-pin RTJ reel (large)
SN75LVCP412CDRTJT
412CD
20-pin RTJ reel (small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN75LVCP412CD
SLLSE62 – DECEMBER 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PC Motherboard
SATA
Host
CD
HDD
R
R = SN75LVCP412CD
eSATA
connector
SATA Cable
(2m)
In Notebook and Desktop
Motherboard
HDD
Dock Connector
R = SN75LVCP412CD
ICH
Notebook
R
eSATA
connector
SATA Cable
(2m)
Dock
In Notebook Dock
Figure 1. Typical Application
2
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GND[3,13,17]
VBB = 1.6V TYP
RT
RX1P [1]
TX1P [15]
Driver
Equalizer
RT
RX1N [2]
TX1N [14]
OOB
Detect
VBB
SN75LVCP412CD
RT
RX2N [12]
Driver
Equalizer
TX2N [4]
RT
RX2P [11]
OOB
Detect
TX2P [5]
PS [19]
CTRL
CD [18]
VCC[6,10,16,20]
EN[7] PE2[8] PE1[9]
Figure 2. Block Diagram
PIN ASSIGNMENTS
Top View
TX1P
TX1N
GND
RX2N
RX2P
15
14
13
12
11
TX2P
VCC
16
10
7
EN
GND
17
9
PE1
8
PE2
CD
18
8
PE2
9
PE1
PS
19
7
EN
VCC
20
6
VCC
5
VCC
TX2P
4
TX2N
3
GND
2
RX1N
VCC
LVCP412CD
RTJ
1
TX2N
4
RX1N
GND
3
5
VCC
RX1P
TX1P
6
10
RX2P
VCC
16
11
17
12
GND
Thermal Pad
should be soldered
to PCB GND plane
for efficient thermal
performance
RX2N
18
13
CD
GND
19
TX1N
PS
LVCP412CD
RTJ
14
20
15
VCC
2
1
RX1P
Bottom View
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PIN FUNCTIONS
PIN
NO.
I/O TYPE
NAME
DESCRIPTION
HIGH SPEED DIFFERENTIAL I/O
2
RX1N
I, VML
1
RX1P
I, VML
12
RX2N
I, VML
11
RX2P
I, VML
14
TX1N
O, VML
15
TX1P
O, VML
4
TX2N
O, VML
5
TX2P
O, VML
Non-inverting and inverting CML differential inputs for CH 1 and CH 2. These pins are tied to an
internal voltage bias by dual termination resistor circuit.
Non-inverting and inverting CML differential outputs for CH 1 and CH 2. These pins are internally tied
to voltage bias by termination resistors.
CONTROL PINS
7
EN
18
CD
I, LVCMOS Device enable pin. Internally PU to VCC.
19
PS
I, LVCMOS Selects/de-selects cable detect feature of device. Internally PU to VCC.
8, 9
PE1,
PE2
I, LVCMOS Selects pre-emphasis settings for CH 1 and CH 2 per Table 4. Internally PD to GND.
O,
LVCMOS
Indicates presence or absence of external HDD attachment to LVCP412CD (via eSATA connector).
POWER
6, 10, 16,
20
VCC
Power
Positive supply, should be 3.3V ±10%.
3, 13, 17
GND
Power
Supply ground
DEVICE SETTINGS
Table 1. Device State
EN
(1)
DEVICE STATE
H
Active
L
Standby
DESCRIPTION
ALP
(1)
enabled (default state)
Device in standby mode
ALP = Auto low power mode active
Table 2. Enabling/Disabling Cable Detect via PS Pin
PS
CABLE DETECT FEATURE
L
Disabled
CD feature is not enabled
DESCRIPTION
H
Enabled
CD feature is enabled (default state)
Table 3. Cable Detect Status Indicator Pin
CD
CABLE CONNECTION STATUS
L
Valid connection detected at eSATA port
H
Valid connection NOT detected at eSATA port
DESCRIPTION
Ext HDD attached
Ext HDD NOT attached
Table 4. Output Pre-Emphasis (Device in active state)
4
PE1
PE2
FUNCTION
0
0
Normal SATA output (default state); CH 1 and CH 2 → 0 dB
1
0
CH 1 → 2.5 dB pre-emphasis; CH 2 → 0 dB
0
1
CH 2 → 2.5 dB pre-emphasis; CH 1 → 0 dB
1
1
CH 1 and CH 2 → 2.5 dB pre-emphasis
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CD
16
17
18
19
20
10 nF
0.01 mF
0.1 mF
1 mF
PS
Interlock
3.3 V
eSATA
Connector
10 nF
SATA Host
1
RX1P
TX1P
2
RX1N
TX1N
15
10 nF
3
LVCP412CD RTJ
A+
14
13
A10 nF
10 nF
10 nF
4
TX2N
RX2N
12
5
TX2P
RX2P
11
10 nF
BB+
10 nF
10
9
8
7
6
4.7K
PE1
4.7K
PE2
EN
GPIO
Must be <2" (5 cm)
for reliable CD operation
(1)
Place supply caps close to device pin.
(2)
Device shown with cable detect mode ON (PS=H, EN=H).
(3)
Output pre-emphasis (PE1, PE2) is shown enabled. Setting will depend on device placement relative to eSATA
connector.
(4)
For reliable cable detect operation, CH1 trace length to eSATA connector pin must be within 2" (<5 cm).
Figure 3. Device Implementation
OPERATION DESCRIPTION
INPUT EQUALIZATION
Each differential input of the SN75LVCP412CD has +7dB of fixed equalization in its front stage. The equalization
will amplify high frequency signals to correct for loss from the transmission channel. The input equalizer is
designed to recover a signal even when no eye is present at the receiver and will affectively support a FR4 trace
at the input anywhere from <4 inches to 20 inches or <10 cm to >50 cm.
OUTPUT PRE-EMPHASIS
The SN75LVCP412CD provides single step pre-emphasis from 0dB to 2.5dB at each of its differential outputs.
Pre-emphasis is controlled independently for each channel and is set by the control pins PE1 and PE2 as shown
in Table 4. The pre-emphasis duration is 0.7 UI or 133ps (typ) at SATA 3.0Gbps speed.
LOW POWER MODES
• Standby Mode (Triggered by EN pin when EN = H→L)
Standby mode is controlled by enable (EN) pin. In its default state this pin is internally pulled high, pulling this
pin LOW will put the device in standby mode within 2us (max). In this mode all active components of the
device are driven to their quiescent level and differential outputs are driven to Hi Z (open). Max power
dissipation is 2mW. Exiting to normal operation requires a maximum latency of 20 us.
• Auto Low Power Mode (Triggered when a given channel is in electrical idle state for >10us and EN = H, PS =
X)
Device enters and exits low power mode by actively monitoring input signal (VIDp-p) level on each of its
channel independently. When input signal on either or both channel is in the electrical idle state, i.e. VIDp-p <
50mV and stays in this state for > 18 µs the associated channel(s) enter low power state. In this state, output
of the associated channel(s) is held to TX VCM and device selectively shuts off some circuitry to lower power
by >75% of its normal operating power. Exit time from auto low power mode is less than 50ns (max).
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Cable Detect Feature (see Figure 4 and Figure 5)
Cable detect mode (for this mode to be active PS and EN must be tied H via a 4.7kΩ or both pins left as NC.
Device must be placed < 2" (or <5cm) from eSATA connector).
To use this feature CH 1 input must be connected to SATA host while CH 2 input to eSATA connector. After
power up device sets CD = 0, which makes the SATA Host monitoring this pin go into normal SATA OOB state
where host will send out COMRESETs (refer to SATA spec ver. 2.6 Gold) to look for a connected device. The
LVCP412CD has a detector circuit that monitors voltage level at its CH1 outputs which changes based on a
closed or open termination. CD pin polarity at power up is at L and remains L if connection is found. It will
transition to H if connection is not found.
In the event that an eSATA host connected to CH1 of LVCP412CD goes to Partial or Slumber mode and the ext
HDD is removed, then CD pin of device will continue to remain L until Host wakes up from Partial or Slumber
mode and restarts the link by sending out COMWAKE. After the transmission of first valid OOB signal from host
the LVCP412CD will detect that no device is attached to esata socket and thereby pull CD pin H indicating to the
host that device is removed.
eSATA host can utilize the polarity of CD pin to shutdown (CD = 1) or turn ON (CD = 0). When host is in
shutdown mode then no COMRESETs are transmitted thereby saving power. After having established no
connection the LVCP412CD switches to listen mode whereby it listens to COMINTS (refer to SATA spec ver. 2.6
Gold) on CH2. Per SATA spec any SATA compliant peripheral PHY, after power-up, will transmit COMINT in the
event that it does not receive a valid COMRESET from the host. If COMINT is detected by the LVCP412CD on
CH2 it will switch CD status to L indicating a connection has been found. The SATA host that is monitoring the
status of CD pin can now turn-ON as a device is connected and the link training is subsequently established.
Without CD feature, eSATA host sends
COMRESETs at frequent intervals(ms) looking for
attached HDD thereby burning power even when
there is no external HDD attached
COMRESET
eSATA Host
1
2
PC MB
eSATA Redriver
W.O. CD feature
PCH Interlock Pin
eSATA
eSATA Host
COMRESET
PC MB
Interlock Pin
412CD
1
2
CD
With 412CD, eSATA host is automatically turned OFF
when no HDD is connected. Power savings of
~100mW - 200mW is possible on host side
Figure 4. Cable Detect
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Vcc = Valid
(>2.9V)
EN = L
Device Power
UP (EN = H)
CD=L
Standby Mode
CD=H
EN = H
PS = H
NO
CD Mode
Enabled
CD Mode
Disabled
YES
Active Mode
CD=L
H
=L
PS
OOB Detected
on CH2
Monitor
CH1 for valid
Termination
Termination Not
Detected
Monitor OOB
on CH2 RX
Termination
Detected
Active Mode
CD = L
Listen Mode
Diable CH1
CD=H
Figure 5. Device Operating States
DEVICE POWER
The SN75LVCP412CD is designed to operate from a single 3.3V supply. Always practice proper power supply
sequencing procedures. Apply VCC first before any input signals are applied to the device. Power down sequence
is in reverse order.
OUT-OF-BAND (OOB) SUPPORT
The squelch detector circuit within the device enables full detection of OOB signaling as specified in SATA spec
2.6. Differential signal amplitude at the receiver input of 50mVp-p or less is not detected as an activity and hence
not passed to the output. Differential signal amplitude of 150mVp-p or more is detected as an activity and
therefore passed to the output indicating activity. Squelch circuit ON/OFF time is 5ns max. While in squelch
mode outputs are held to VCM.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage range (2)
(1)
VCC
Differential I/O
Voltage range
V
V
Human body model (3)
±8000
V
Charged-device model (4)
±1500
V
±200
V
Machine model
(2)
(3)
(4)
(5)
V
–0.5 to 4
(5)
Continuous power dissipation
(1)
UNIT
–0.5 to VCC + 0.5
Control I/O
Electrostatic discharge
VALUE
–0.5 to 4
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
THERMAL INFORMATION
THERMAL METRIC (1)
SN75LVCP412CD
RTJ (20) PINS
qJA
Junction-to-ambient thermal resistance
47.9
qJCtop
Junction-to-case (top) thermal resistance
44.9
qJB
Junction-to-board thermal resistance
24.4
yJT
Junction-to-top characterization parameter
0.6
yJB
Junction-to-board characterization parameter
24.4
qJCbot
Junction-to-case (bottom) thermal resistance
5.7
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
typical values for all parameters are at VCC = 3.3V and TA = 25°C. All temperature limits are specified by design.
VCC
Supply voltage
TVcc0-90%
Supply ramp time
CCOUPLING
Coupling capacitor
NOM
MAX
3
3.3
3.6
V
1
10
ms
Supply ramp 0V – 0.9VCC
12
Operating free-air temperature
8
MIN
0
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UNITS
nF
85
°C
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DEVICE ELECTRICAL CHARACTERISTICS
under recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
185
280
mW
PActive
Device power dissipation
ICC
Active Supply Current
PSDWN
Standby Power
ICCSDWN
Standby Current
ICC-ALP
ALP (auto low power) supply current
Auto low power conditions met
PALP
ALP (auto low power) supply power
Auto low power conditions met
17
EN, PE1, PE2 in default state, K28.5 pattern
at 3 Gbps, VID = 700 mVp-p
EN = 0 V
56
78
mA
1.3
2.1
mW
380
560
uA
5.0
6.5
mA
Maximum data rate
320
24
mW
3.0
Gbps
450
ps
tPDelay
Propagation delay
Measured using K28.5 pattern (see Figure 8)
tENB
Device enable time
EN = 0 → 1
5
us
tDIS
Device disable time
EN = 1 → 0
2
us
AutoLPENTRY
ALP entry time
Electrical idle at input, See Figure 11
30
us
AutoLPEXIT
ALP exit time
After first signal activity, See Figure 11
VOOB
Input OOB threshold
tOOB1
OOB mode enter
tOOB2
OOB mode exit
18
50
See Figure 9
28
50
ns
90
150
mVpp
4
8
ns
5
8
ns
CONTROL LOGIC ELECTRICAL CHARACTERISTICS
under recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
VIH
Input high voltage (EN, PS, PE)
1.4
VIL
Input low voltage (EN, PS, PE)
V
VINHYS
Input hysteresis (EN, PS, PE)
IIH
Input high current (EN, PS, PE)
10
µA
IIL
Input low current (EN, PS, PE)
10
µA
VOH
High level output voltage (CD)
IO = -500 µA
3.6
V
VOL
High level output voltage (CD)
IO = 500 µA
0.1
V
0.5
100
2.7
mV
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RECEIVER AC/DC ELECTRICAL CHARACTERISTICS
under recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
UNITS
ZDIFFRX
Differential-input
impedance
PARAMETER
85
100
115
Ω
ZSERX
Single-ended input
impedance
40
VCMRX
Common-mode voltage
RLDiffRX
RLCMRX
Differential mode return
Loss
Common-mode return
Loss
Differential input voltage
PP
VdiffRX
IBRX
Impedance balance
TEST CONDITIONS
1.6
f = 150 MHz – 300 MHz
18
24
f = 300 MHz – 600 MHz
14
20
f = 600 MHz – 1.2 GHz
10
20
f = 1.2 GHz – 2.4 GHz
8
11
f = 2.4 GHz – 3.0 GHz
3
11
f = 150 MHz – 300 MHz
5
11
f = 300 MHz – 600 MHz
5
14
f = 600 MHz – 1.2 GHz
2
17
f = 1.2 GHz – 2.4 GHz
1
16
f = 2.4 GHz – 3.0 GHz
1
8
f = 750 MHz and 1.5 GHz
200
30
42
f = 300 MHz – 600 MHz
30
40
f = 600 MHz – 1.2 GHz
20
36
f = 1.2 GHz – 2.4 GHz
10
27
f = 2.4 GHz – 3.0 GHz
4
23
Rise/fall time
Rise times and fall times measured between 20% and 80% of
the signal
TskewRX
Differential skew
Difference between the single-ended mid-point of the RX+
signal rising/falling edge, and the single-ended mid-point of the
RX– signal falling/rising edge
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V
dB
dB
2000
f = 150 MHz – 300 MHz
T20-80RX
10
Ω
mVppd
dB
136
ps
50
ps
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TRANSMITTER AC/DC ELECTRICAL CHARACTERISTICS
under recommended operating conditions (unless otherwise noted)
MIN
TYP MAX
ZdiffTX
Pair differential impedance
PARAMETER
85
115
ZSETX
Single-ended input
impedance
40
RLDiffTX
RLCMTX
CONDITIONS
Common-mode return Loss
14
24
f = 300 MHz – 600 MHz
8
21
6
21
f = 1.2 GHz – 2.4 GHz
6
14
f = 2.4 GHz – 3.0 GHz
3
15
f = 150 MHz – 300 MHz
5
31
f = 300 MHz – 600 MHz
5
23
f = 600 MHz – 1.2 GHz
2
13
f = 1.2 GHz – 2.4 GHz
1
11
f = 2.4 GHz – 3.0 GHz
IBTX
Impedance balance
Ω
f = 150 MHz – 300 MHz
Differential mode return Loss f = 600 MHz – 1.2 GHz
UNITS
1
6
f = 150 MHz – 300 MHz
30
43
f = 300 MHz – 600 MHz
20
39
f = 600 MHz – 1.2 GHz
10
34
f = 1.2 GHz – 2.4 GHz
10
28
f = 2.4 GHz – 3.0 GHz
4
26
dB
dB
dB
DiffVppTX
Differential output voltage PP f = 1.5 GHz, PE1/PE2 = 0, See Figure 10
400
510
700
DiffVppTX_DE
Differential output voltage PP f = 1.5 GHz, PE1/PE2 = 1 See Figure 10
600
720
965
mVppd
Output pre-emphasis
at 1.5GHz (when enabled)
2.5
dB
tDE
Pre-emphasis width
At 3Gbps, Also see Figure 10
0.5
UI
VCMTX
Common-mode voltage
VCMTX_AC
AC CM voltage active mode
Maximum amount of AC CM signal at TX
T20-80TX
Rise/fall time
Rise times and fall times measured between 20% and 80%
of the signal. PE2/PE1 = 0
TskewTX
Differential skew
Difference between the SE mid-point of the TX+ signal
rising/falling edge, and the SE mid-point of the TX– signal
falling/rising edge;
1.97
67
V
20
50
mVpp
90
136
ps
7
20
ps
Jitter (with pre-emphasis disabled at device pin + 2" loadboard trace)
TJTX
Total jitter (1)
UI = 333ps, ±K28.5 control character; PE2/PE1 = 0 V
35
63
ps-pp
DJTX
Deterministic jitter (1)
UI = 333ps, ±K28.5 control character; PE2/PE1 = 0 V
8
33
ps-pp
UI = 333ps, ±K28.7 control character; PE2/PE1 = 0 V
1.9
2.1
ps-rms
35
97
ps-pp
RJTX
Random jitter
(1)
Jitter (with pre-emphasis enabled and measured as shown in Figure 6)
TJTX
Total jitter (1)
DJTX
Deterministic jitter
RJTX
Random jitter (1)
(1)
UI = 333ps, ±K28.5 control character; PE2/PE1 = VCC
(1)
UI = 333ps, ±K28.5 control character; PE2/PE1 = VCC
8
67
Uip-p
UI = 333ps, ±K28.7 control character; PE2/PE1 = VCC
1.9
2.1
ps-rms
TJ = (14.1×RJSD + DJ) where RJSD is one standard deviation value of RJ Gaussian distribution. TJ measurement is at the SATA
connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect.
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Jitter
Measurement
Point
*Signal
Source
10" FR4
6" FR4
*Signal
Source
LVCP412CD
Jitter
Measurement
Point
Figure 6. Jitter Measurement Setup
A
Redriver
SATA Host
PC MB
Suggested Trace Lengths
eSATA
connector
PC MB
B
C
A
B
TYP (inch)
4 to 16
0.5
4.5
(1)
MAX (inch)
18
2
20
C
Redriver on PC
Motherboard
A
B1
SATA Host
Redriver
PC MB
eSATA
connector
DOCK
DOCK
TYP (inch)
B = (B1+B2)
8 to 14
C
0.5
A
10 to 18
Redriver on Dock
Board
(1)
Suggested Trace Lengths
C
B2
(1)
MAX (inch)
16
2
18
Trace lengths are suggested values based on TI lab measurements (taken with output pre-emphasis enabled on both
channels) to meet SATA loss and jiter spec.
spacer
Actual trace length supported by the LVCP412CD may be more or less than suggested values and will depend on
board layout, number of connectors used in the SATA signal path, and SATA host and eSATA connector design.
Figure 7. Suggested Trace Length for LVCP412CD in PC M B and Dock
IN
tPDelay
tPDelay
OUT
Figure 8. Propagation Delay Timing Diagram
12
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :SN75LVCP412CD
SN75LVCP412CD
www.ti.com
SLLSE62 – DECEMBER 2010
spacing
spacing
IN+
50 mV
Vcm
IN-
tOOB2
tOOB1
OUT +
Vcm
OUT -
Figure 9. OOB Enter and Exit Timing
spacing
spacing
1-bit
1 to N bits
1 to N bits
1-bit
2.5 dB
0dB
Vcm
DiffVppTX
DiffVppTX_DE
0dB
50 %
tDE
Figure 10. TX Differential Output with 2.5 dB Pre-Emphasis Step
spacing
spacing
RX1,2P
VCMRX
RX1,2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY
Power Saving
Mode
Figure 11. Auto Low Power Mode Timing
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :SN75LVCP412CD
13
SN75LVCP412CD
SLLSE62 – DECEMBER 2010
www.ti.com
spacing
spacing
spacing
Vcc
90%
0%
<10ms
Figure 12. Vcc Waveform Rise Time
14
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :SN75LVCP412CD
PACKAGE OPTION ADDENDUM
www.ti.com
23-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN75LVCP412CDRTJR
ACTIVE
QFN
RTJ
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 85
412CD
SN75LVCP412CDRTJT
ACTIVE
QFN
RTJ
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 85
412CD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Feb-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN75LVCP412CDRTJR
QFN
RTJ
20
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
SN75LVCP412CDRTJT
QFN
RTJ
20
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75LVCP412CDRTJR
QFN
RTJ
20
3000
367.0
367.0
35.0
SN75LVCP412CDRTJT
QFN
RTJ
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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