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Texas Instruments Two Channel SATA 3Gbps Redriver Datasheet
SN75LVCP412A
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SLLS991 – DECEMBER 2009
Two Channel SATA 3-Gbps Redriver
Check for Samples: SN75LVCP412A
FEATURES
•
1
•
•
•
•
•
•
•
•
Supports SATA 1.5 Gbps and 3.0 Gbps Data
Rates
SATA Hot-Plug Capable
Supports Common-Mode Biasing for OOB
Signaling with Fast Turn-On
Channel Selectable Output Pre-Emphasis
7dB Fixed Receiver Equalization
Integrated Termination
Low Power
– <200 mW (typ) in Active Mode
– <20 mW (typ) in Auto Low Power Mode
– 2.1 mW (max) in Standby Mode
Excellent Jitter and Loss Compensation
Capability to Over 20 Inch FR4 Trace
•
•
•
High Protection Against ESD Transient
– HBM: 12000 V
– CDM: 1500 V
– MM: 200 V
IEC 61000-4-2 Qualified (on eSATA connector
pins)
– ±8 kV Contact Discharge
– ±15 kV Air Discharge
20-Pin QFN Package
Pin Compatible to MAX4951
APPLICATIONS
•
Notebooks, Desktops, Docking Stations, Set
Top Box, Servers, and Workstations
DESCRIPTION
The SN75LVCP412A is a dual channel, single lane SATA redriver and signal conditioner supporting data rates
up to 3.0 Gbps that complies with SATA specification revision 2.6.
The SN75LVCP412A operates from a single 3.3-V supply. Integrated 100-Ω line termination with self-biasing
make the device suitable for AC coupling. The inputs incorporate an OOB detector which automatically turns the
differential outputs off while maintaining a stable output common-mode voltage compliant to SATA link. The
device is also designed to handle SSC transmission per the SATA specification.
The SN75LVCP412A handles interconnect losses at both its input and output. The built-in transmitter
pre-emphasis feature is capable of applying 0 dB or 2.5 dB of relative amplification at higher frequencies to
counter the expected interconnect loss. On the receive side, the device applies a fixed equalization of 7 dB to
boost input frequencies near 1.5 GHz. Collectively, the input equalization and output pre-emphasis features of
the device work to fully restore SATA signal integrity over extended cable and backplane pathways.
The device is hot-plug capable(1) preventing device damage under hot-insertion such as async signal
plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal.
(1) Requires use of AC coupling capacitors at differential inputs and outputs.
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
SN75LVCP412ARTJR
CP412A
20-Pin RTJ Reel (large)
SN75LVCP412ARTJT
CP412A
20-Pin RTJ Reel (small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN75LVCP412A
SLLS991 – DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION
PC Motherboard
ICH
HDD
R
R = SN75LVCP412A
eSATA
connector
SATA Cable
(2m)
In Notebook and Desktop
Motherboard
HDD
Dock Connector
R = SN75LVCP412A
ICH
Notebook
R
eSATA
connector
SATA Cable
(2m)
Dock
In Notebook Dock
2
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GND [3, 13, 17-19]
VBB = 1.6 V typ
RT
TX1P [15]
RT
Driver
Equalizer
RX1P [1]
TX1N [14]
OOB
Detect
RX1N [2]
VBB
SN75LVCP412A
RT
RX2N [12]
Driver
Equalizer
TX2N [4]
RX2P [11]
OOB
Detect
TX2P [5]
RT
CTRL
PE2 [8]
PE1 [9]
EN [7]
VCC [6, 10, 16, 20]
Figure 1. Data Flow Block Diagram
Table 1. Device State
EN
(1)
DEVICE
STATE
DESCRIPTION
(1)
H
Active
ALP enabled
L
Standby
Device in standby mode
(default)
ALP = Auto low power mode
Table 2. Output Pre-Emphasis (Device in active state)
PE1
PE2
0
0
Normal SATA output (default state); CH 1 and CH 2 → 0 dB
FUNCTION
1
0
CH 1 → 2.5 dB pre-emphasis; CH 2 → 0 dB
0
1
CH 2→ 2.5 dB pre-emphasis; CH 1 → 0 dB
1
1
CH 1 and CH 2 → 2.5 dB pre-emphasis
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PIN ASSIGNMENT
TOP VIEW
Thermal Pad
should be soldered
to PCB GND plane
for efficient thermal
performance
GND 18
GND 17
15
14
13
12
11
TX1P
TX1N
GND
RX2N
RX2P
VCC 16
RX2N
RX2P
14
13
12
11
6 VCC
VCC 16
10 VCC
7 EN
GND 17
9 PE1
8 PE2
GND 18
9 PE1
10 VCC
8
PE2
GND 19
7
EN
VCC 20
6
VCC
LVCP412ARTJ
1
2
3
4
5
TX2P
LVCP412ARTJ
GND 19
15
TX2N
VCC 20
GND
5
GND
TX2P
4
TX1N
TX2N
3
RX1N
GND
2
TX1P
RX1N
1
RX1P
RX1P
BOTTOM VIEW
TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
NAME
DESCRIPTION
High Speed Differential I/O
2
RX_1N
I, CML
1
RX_1P
I, CML
12
RX2N
I, CML
11
RX2P
I, CML
14
TX_1N
O, CML
15
TX_1P
O, CML
4
TX_2N
O, CML
5
TX_2P
O, CML
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an
internal voltage bias by dual termination resistor circuit.
Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are internally
tied to voltage bias by termination resistors.
Control Pins
7
EN
I, LVCMOS
Device enable pin. Internally PU to VCC
9,8
PE1, PE2
I, LVCMOS
Selects pre-emphasis settings for CH 1 and CH 2 perTable 2. Internally PD to GND
Power
4
6, 10, 16, 20
VCC
Power
Positive supply should be 3.3V ± 10%
3, 13 17 - 19
GND
Power
Supply ground
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DEVICE IMPLEMENTATION
3.3 V
0.01 mF
0.1 mF
1 mF
16
17
18
19
20
10 nF
eSATA
Connector
10 nF
1
SATA Host
2
RX1P
TX1P
RX1N
TX1N
15
10 nF
3
LVCP412A RTJ
A+
14
13
A10 nF
10 nF
10 nF
4
TX2N
RX2N
12
5
TX2P
RX2P
11
10 nF
BB+
10 nF
10
9
8
7
6
4.7K
PE1
4.7K
PE2
EN
GPIO
A.
Place supply capacitors close to the pin.
B.
EN can be left open or tied to supply when no external control is implemented.
C.
Output pre-emphasis (PE1, PE2) is shown enabled. Setting depends on device palcement relative to eSATA
connector.
DETAILED DESCRIPTION
INPUT EQUALIZATION
Each differential input of the SN75LVCP412A has +7 dB of fixed equalization in its front stage. The equalization
amplifies high frequency signals to correct for loss from the transmission channel. The input equalizer is
designed to recover a signal even when no eye is present at the receiver and effectively supports FR4 trace at
the input anywhere from <4 inches to 20 inches or <10 cm to >50 cm.
OUTPUT PRE-EMPHASIS
The SN75LVCP412A provides single step pre-emphasis from 0 dB to 2.5 dB at each of its differential outputs.
Pre-emphasis is controlled independently for each channel and is set by the control pins PE1 and PE2 as shown
in the terminal functions table. The pre-emphasis duration is 0.7 UI or 133 ps (typ) at SATA 3-Gbps speed.
LOW POWER MODE
Long battery life has become the single most important differentiator for mobile platforms. The SN75LVCP412A
supports this emphasis on low system power by offering the choice of two low power modes, one requires
control by SATA host (option 1) and the second (option 2) is completely autonomous whereby the
SN75LVCP412A goes into ultra low power mode (<20mW) on its own when no data traffic is detected for longer
than 10us. Both low power modes are described below:
• Standby Mode (option 1) (triggered by EN pin when EN = H → L)
– Standby mode is controlled by the enable (EN) pin. In its default state this pin is internally pulled high.
Pulling this pin LOW puts the device in standby mode within 2μs (max). In this mode all active
components of the device are driven to their quiescent level and differential outputs are driven to Hi-Z
(open). Max power dissipation is 2 mW. Exiting to normal operation requires a maximum latency of 20 μs.
• Auto Low Power Mode (option 2) (triggered when a given channel is in the electrical idle state for > 10 μs and
EN = H)
– The device enters and exits low power mode by actively monitoring the input signal (VIDp-p) level on each
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of its channels independently. When the input signal of either or both channels is in the electrical idle
state, i.e. VIDp-p <50 mV and stays in this state for > 10 μs, the associated channel(s) enters the low power
state. In this state, the output of the associated channel(s) is held to TX VCM and the device selectively
shuts off some circuitry to lower power by > 90% (typ) of its normal operating power. Exit time from auto
low power mode is less than 50 ns max.
OUT-OF-BAND (OOB) SUPPORT
The squelch detector circuit within the device enables full detection of OOB signaling as specified in SATA
specification 2.6. Differential signal amplitude at the receiver input of 50 mVp-p or less is not detected as an
activity and hence is not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as
an activity and therefore passed to the output indicating activity. Squelch circuit on/off time is 8 ns max. While in
squelch mode outputs are held to VCMTX.
DEVICE POWER
The SN75LVCL412A is designed to operate from a single 3.3-V supply. Always practice proper power supply
sequencing procedures. Apply VCC first before any input signals are applied to the device. The power-down
sequence is in reverse order.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
(2)
Voltage range
VALUE
UNIT
VCC
–0.5 to 4
V
Differential I/O
–0.5 to 4
V
Control I/O
Electrostatic discharge
–0.5 to VCC + 0.5
Human body model (3)
Charged-device model
±12000
(4)
±1500
Machine model (5)
±200
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
V
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B.
Tested in accordance with JEDEC Standard 22, Test Method C101-A.
Tested in accordance with JEDEC Standard 22, Test Method A115-A.
DISSIPATION RATINGS
PACKAGE
20-pin QFN (RTJ)
(1)
PCB JEDEC
STANDARD
TA ≤ 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
Low-K
1176 mW
11.76 mW/°C
470 mW
High-K
2631 mW
26.3 mW/°C
1052 mW
TA = 85°C
POWER RATING
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
RθJB
Junction-to-board thermal resistance
10
°C/W
RθJC
Junction-to-case thermal resistance
60
°C/W
RθJP
Junction-to-pad thermal resistance
15.2
°C/W
(1)
6
The maximum rating is simulated under 3.6-V VCC.
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RECOMMENDED OPERATING CONDITIONS
with typical values measured at VCC = 3.3 V, TA = 25°C; all temperature limits are assured by design
PARAMETER
VCC
Supply voltage
CCOUPLING
Coupling capacitor
TA
Operating free-air temperature
CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
UNITS
V
12
0
nF
85
°C
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE
PActive
Device power dissipation
EN, PE1, PE2 in default state,
K28.5 pattern at 3 Gbps, VID = 700 mVp-p
185
280
mW
ICC
Supply current, active
EN, PE1, PE2 in default state,
K28.5 pattern at 3 Gbps, VID = 700 mVp-p
56
78
mA
PSDWN
Standby power
EN = 0V
1.3
2.1
mW
ICCSDWN
Shutdown current
EN = 0V
380
560
μA
PALP
ALP (auto low power) supply
current
Auto low power conditions met
17
24
mW
ICC-ALP
ALP (auto low power) supply
current
Auto low power conditions met
5.0
6.5
mA
3.0
Gbps
300
500
ps
Maximum data rate
tPDelay
Propagation delay
Measured using K28.5 pattern, See Figure 2
tENB
Device enable time
ENB = 0 → 1
5
μs
tDIS
Device disable time
ENB = 1 → 0
1
μs
AutoLPENTRY
ALP entry time
Electrical Idle at Input, See Figure 2
17
AutoLPEXIT
ALP exit time
After first signal activity, See Figure 2
25
50
ns
VOOB
Input OOB threshold
See Figure 3
100
150
mVp-p
tOOB1
OOB mode enter
See Figure 3
5
8
ns
tOOB2
OOB mode exit
See Figure 3
5
8
ns
50
μs
CONTROL LOGIC
VIH
High-level input voltage
VIL
Low-level input voltage
1.4
V
VINHYS
Input hysteresis
IIH
High-level input current
10
μA
IIL
Low-level input current
10
μA
115
Ω
0.5
100
V
mV
RECEIVER AC/DC
ZDiffRX
Differential input impedance
85
ZSERX
Single-ended input impedance
40
VCMRX
Common-mode voltage
RLDiffRX
Differential mode return loss
100
Ω
1.6
f = 150 MHz–300 MHz
18
f = 300 MHz–600 MHz
14
f = 600 MHz–1.2 GHz
10
f = 1.2 GHz–2.4 GHz
8
f = 2.4 GHz–3.0 GHz
3
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dB
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
RLCMRX
Common-mode return loss
CONDITIONS
MIN
f = 150 MHz–300 MHz
5
f = 300 MHz–600 MHz
5
f = 600 MHz–1.2 GHz
2
f = 1.2 GHz–2.4 GHz
1
f = 2.4 GHz–3.0 GHz
TYP
MAX
UNITS
dB
1
VDiffRX
Differential input voltage PP
f = 750 MHz–1.5 GHz
200
IBRX
Impedance balance
f = 150 MHz–300 MHz
30
f = 300 MHz–600 MHz
30
f = 600 MHz–1.2 GHz
20
f = 1.2 GHz–2.4 GHz
10
f = 2.4 GHz–3.0 GHz
2000
mV/pp
dB
4
T20-80RX
Rise/fall time
Rise times and fall times measured between
20% and 80% of the signal
TskewRX
Differential skew
Difference between the single-ended mid-point of
the RX+ signal rising/falling edge, and the
single-ended mid-point of the RX– signal
falling/rising edge
67
136
ps
50
ps
115
Ω
TRANSMITTER AC/DC
ZDiffTX
Pair differential Impedance
85
ZSETX
Single-ended input impedance
40
Ω
RLDiffTX
Differential mode return loss
f = 150 MHz–300 MHz
14
dB
f = 300 MHz–600 MHz
8
f = 600 MHz–1.2 GHz
6
f = 1.2 GHz–2.4 GHz
6
f = 2.4 GHz–3.0 GHz
3
f = 150 MHz–300 MHz
5
f = 300 MHz–600 MHz
5
f = 600 MHz–1.2 GHz
2
f = 1.2 GHz–2.4 GHz
1
RLCMTX
Common-mode return loss
f = 2.4 GHz–3.0 GHz
IBTX
Impedance balance
dB
1
f = 150 MHz–300 MHz
30
f = 300 MHz–600 MHz
20
f = 600 MHz–1.2 GHz
10
f = 1.2 GHz–2.4 GHz
10
f = 2.4 GHz–3.0 GHz
dB
4
DiffVppTX
Differential output voltage PP
f = 1.5 GHz, PE1/PE2 = 0
400
585
700
mV/pp
DiffVppTX_PE
Differential output voltage PP
f = 1.5 GHz, PE1/PE2 = 1
600
790
965
mV/pp
Output pre-emphasis
At 1.5 GHz when enabled
tPE
Pre-emphasis width
At 3 Gbps, See Figure 6
VCMTX
Common-mode voltage
VCMTX_AC
AC CM voltage active mode
Max amount of AC CM signal at TX
T20-80TX
Rise/fall time
Rise times and fall times measured between
20% and 80% of the signal, PE2, PE1 = 0 V
TskewTX
Differential skew
Difference between the single-ended mid-point of
the TX+ signal rising/falling edge, and the
single-ended mid-point of the TX– signal
falling/rising edge
8
2.5
dB
0.5
UI
1.97
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67
V
20
50
mVp-p
83
136
ps
7
20
ps
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
JITTER (with pre-emphasis disabled at device pin+2” loadboard trace)
TJTX
Total jitter (1)
UI = 333 ps, +K28.5 control character,
PE2, PE1 = 0 V, VID = 500 mVp-p
35
67
psp-p
DJTX
Deterministic jitter (1)
UI = 333 ps, +K28.5 control character,
PE2, PE1 = 0 V, VID = 500 mVp-p
10
33
psp-p
RJSD
Random jitter (1)
UI = 333 ps, +K28.7 control character,
PE2, PE1 = 0 V, VID = 500 mVp-p
1.8
2.0
ps-rms
JITTER (with pre-emphasis enabled and measured as shown in Fig 1)
TJTX
Total jitter (1)
UI = 333 ps, +K28.5 control character,
PE2, PE1 = VCC, VID = 500 mVp-p
40
100
psp-p
DJTX
Deterministic jitter (1)
UI = 333 ps, +K28.5 control character,
PE2, PE1 = VCC, VID = 500 mVp-p
15
67
psp-p
RJSD
Random jitter (1)
UI = 333 ps, +K28.7 control character,
PE2, PE1 = VCC, VID = 500 mVp-p
1.8
2.0
ps-rms
(1)
TJ = (14.1×RJSD + DJ) where RJSD is one standard deviation value of RJ Gaussian distribution. TJ measurement is at the SATA
connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect.
Jitter
Measurement
Point
*Signal
Source
10" FR4
6" FR4
*Signal
Source
LVCP412A
*Source Jitter Measurements
Total Jitter
Deterministic Jitter
Random Jitter
Jitter
Measurement
Point
(ps)
32pp
8pp
1.7rms
Figure 2. Jitter Measurement Setup
IN
tPDelay
tPDelay
OUT
Figure 3. Propagation Delay Timing Diagram
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IN+
Vcm
50 mV
INtOOB2
tOOB1
OUT+
Vcm
OUT-
Figure 4. OOB Enter and Exit Timing
1-bit
tPE
2.5 dB
1 to N bits
1-bit
1 to N bits
0dB
Vcm
DiffVPPTX
DiffVPPTX_PE
0dB
tDE
2.5 dB
Figure 5. TX Differential Output with 2.5 dB Pre-Emphasis Step
RX1,2P
VCMRX
RX1,2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY
Power Saving
Mode
Figure 6. Auto Low Power Mode Timing
10
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12
Residual - DJ psp-p
10
8
6
VCC = 3.3 V,
TC = 25°C,
VIN = 275 mVpp,
K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
4
2
0
2
6
10
14
18
4 mill - Input Trace Length - inches
Figure 7. Residual DJ vs Input Trace Length
Output Trace Fixed at 2"
18
16
Residual - DJ psp-p
14
12
VCC = 3.3 V,
TC = 25°C,
VIN = 275 mVpp,
K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
10
8
6
4
2
0
2
6
10
14
18
4 mill - Output Trace Length - inches
Figure 8. Residual DJ vs Output Trace Length
Input Trace Fixed at 2"
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VCC = 3.3 V,
TC = 25°C,
VIN = 275 mVpp,
K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 9. Eye Pattern, 1.5 Gbps, Input = 2", Output = 2"
VCC = 3.3 V,
TC = 25°C,
VIN = 275 mVpp,
K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 10. Eye Pattern, 1.5 Gbps, Input = 2", Output = 6"
12
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VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 11. Eye Pattern, 1.5 Gbps, Input = 2", Output = 10"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1, 4 mil Trace
Figure 12. Eye Pattern, 1.5 Gbps, Input = 2", Output = 14"
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VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 13. Eye Pattern, 1.5 Gbps, Input = 2", Output = 18"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 14. Eye Pattern, 3.0 Gbps, Input = 2", Output = 2"
14
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
SN75LVCP412A
www.ti.com
SLLS991 – DECEMBER 2009
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 15. Eye Pattern, 3.0 Gbps, Input = 2", Output = 6"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 16. Eye Pattern, 3.0 Gbps, Input = 2", Output = 10"
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
15
SN75LVCP412A
SLLS991 – DECEMBER 2009
www.ti.com
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 17. Eye Pattern, 3.0 Gbps, Input = 2", Output = 14"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 18. Eye Pattern, 3.0 Gbps, Input = 2", Output = 18"
16
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
SN75LVCP412A
www.ti.com
SLLS991 – DECEMBER 2009
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 19. Eye Pattern, 1.5 Gbps, Input = 6", Output = 2"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 20. Eye Pattern, 1.5 Gbps, Input = 10", Output = 2"
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
17
SN75LVCP412A
SLLS991 – DECEMBER 2009
www.ti.com
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 21. Eye Pattern, 1.5 Gbps, Input = 14", Output = 2"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 22. Eye Pattern, 1.5 Gbps, Input = 18", Output = 2"
18
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
SN75LVCP412A
www.ti.com
SLLS991 – DECEMBER 2009
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 23. Eye Pattern, 3.0 Gbps, Input = 6", Output = 2"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 24. Eye Pattern, 3.0 Gbps, Input = 10", Output = 2"
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
19
SN75LVCP412A
SLLS991 – DECEMBER 2009
www.ti.com
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 25. Eye Pattern, 3.0 Gbps, Input = 14", Output = 2"
VCC = 3.3 V, TC = 25°C,
VIN = 275 mVpp, K28.5 pattern,
PE1 = 1, PE2 = 1,
4 mil Trace
Figure 26. Eye Pattern, 3.0 Gbps, Input = 18", Output = 2"
20
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
SN75LVCP412A
www.ti.com
SLLS991 – DECEMBER 2009
A
Redriver
SATA Host
PC MB
Suggested Trace Lengths
eSATA
connector
PC MB
B
C
A
B
TYP* (inch) MAX* (inch)
4 to 16
18
2 to 4
6
6 to 20
24
C
Redriver on PC Motherboard
A
B1
SATA Host
Redriver
PC MB
eSATA
connector
DOCK
B2
Redriver on Dock Board
Suggested Trace Lengths
C
DOCK
TYP* (inch) MAX* (inch)
B = (B1+B2)
8 to 14
16
C
2 to 4
6
A
10 to 18
22
A.
Trace lengths are suggested values based on TI lab measurements (taken with output pre-emphasis enabled on both
channels) to meet SATA loss and jitter specifications.
B.
Actual trace length supported by the SN75LVCP412A may be more or less than suggestedvalues and depend on
board layout, number of connectors used in the SATA signal path, and SATA host and esata connector design.
Figure 27. Suggested Trace Length for LVCP412A in PC MB and Dock
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP412A
21
PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN75LVCP412ARTJR
ACTIVE
QFN
RTJ
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 85
CP412A
SN75LVCP412ARTJT
ACTIVE
QFN
RTJ
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 85
CP412A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Nov-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN75LVCP412ARTJR
QFN
RTJ
20
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
SN75LVCP412ARTJT
QFN
RTJ
20
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Nov-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75LVCP412ARTJR
QFN
RTJ
20
3000
367.0
367.0
35.0
SN75LVCP412ARTJT
QFN
RTJ
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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