Texas Instruments | Advanced Universal Serial Bus Transceivers (Rev. E) | Datasheet | Texas Instruments Advanced Universal Serial Bus Transceivers (Rev. E) Datasheet

Texas Instruments Advanced Universal Serial Bus Transceivers (Rev. E) Datasheet
TUSB1105, TUSB1106
www.ti.com
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS
Check for Samples: TUSB1105, TUSB1106
FEATURES
•
1
•
•
•
•
•
•
•
•
Compatible With Universal Serial Bus
Specification Rev. 2.0
Transmit and Receive Serial Data at Both
Full-Speed (12-Mbit/s) and Low-Speed
(1.5-Mbit/s) Data Rates
Integrated Bypassable 5-V to 3.3-V Voltage
Regulator for Powering Via USB VBUS
VBUS Disconnection Indication Through VP and
VM
Used as USB Device Transceiver or USB Host
Transceiver
Stable RCV Output During SE0 Condition
Two Single-Ended Receivers With Hysteresis
Low-Power Operation, Ideal for Portable
Equipment
•
•
Support I/O Voltage Range From 1.65 V to
3.6 V
IEC-61000-4-2 ESD Compliant
– ±9-kV Contact-Discharge Model
(D+, D–, VCC(5.0))
– ±15-kV Human-Body Model
(D+, D–, VCC(5.0))
TUSB1105 Available in Quad Flat No-Lead
(QFN) Package; TUSB1106 Available in QFN
and Thin Shrink Small-Outline Package
(TSSOP)
APPLICATIONS
•
•
•
•
Mobile Phones
Personal Digital Assistants (PDAs)
Information Appliances (IAs)
Digital Still Cameras (DSCs)
DESCRIPTION/ORDERING INFORMATION
The TUSB1105 and TUSB1106 universal serial bus (USB) transceivers are compliant with the Universal Serial
Bus Specification Rev. 2.0. These devices can transmit and receive serial data at both full-speed (12-Mbit/s) and
low-speed (1.5-Mbit/s) data rates. The TUSB1105 and TUSB1106 can be used as USB device transceivers or
USB host transceivers.
The devices allow USB application-specific ICs (ASICs) and programmable logic devices (PLDs), with
power-supply voltages from 1.65 V to 3.6 V, to interface with the physical layer (PHY) of the universal serial bus.
They have an integrated 5-V to 3.3-V voltage regulator for direct powering via the USB supply VBUS.
The TUSB1105 allows single-ended and differential input modes selectable by a mode (MODE) input and is
available in RGT and RTZ packages. The TUSB1106 allows only differential input mode and is available in PW,
RGT, RSV, and RTZ packages.
The TUSB1105 and TUSB1106 are ideal for portable electronic devices, such as mobile phones, personal digital
assistants, information appliances, and digital still cameras.
ORDERING INFORMATION
PACKAGE (1)
TA
QFN – RGT
–40°C to 85°C
(1)
(2)
(2)
Reel of 3000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TUSB1105RGTR
ZYB
TUSB1106RGTR
ZYC
TUSB1105RTZR
ZYB
TUSB1106RTZR
ZYC
QFN – RTZ
Reel of 3000
QFN – RSV
Reel of 3000
TUSB1106RSVR
ZYC
TSSOP – PW
Reel of 2000
TUSB1106PWR
TU1106
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2010, Texas Instruments Incorporated
TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
www.ti.com
TUSB1105 PACKAGES
4
VP
3
10
D+
RCV
2
11
VPO/VO
OE
1
12
VMO/FSE0
16
15
14
13
SO FT CO N
V pu(3.3)
V C C(5.0)
V reg(3.3)
GND
(expo sed die pad)
D−
5
VM
4
VP
3
R CV
2
OE
1
SPE ED
SU SPN D
6
7
8
G ND
(exposed die pad)
16
15
14
V CC (5.0)
VM
9
V CC (I/O )
8
V pu(3.3)
7
MO DE
V C C (I/O )
6
SO FTC O N
M O DE
5
RTZ PACKAGE
(BOTTOM VIEW)
SPE ED
S USPND
RGT PACKAGE
(BOTTOM VIEW)
9
D−
10
D+
11
VPO /VO
12
V MO /F SE0
13
V reg(3.3)
TUSB1106 PACKAGES
4
9
D−
VP
3
10
D+
RCV
2
11
VPO
OE
1
12
VMO
15
14
13
V C C(5.0)
V reg(3.3)
SO FT CO N
16
V pu(3.3)
No Connect
SPEED
VCC(I/O)
SUSPND
VP
D+
VMO
Vreg(3.3)
OE
VCC(5.0)
VPO
VPU(3.3)
RCV
SOFTCON
2
GND
D-
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S PEE D
7
8
D−
4
10
D+
VP
3
11
VPO
RC V
2
12
VM O
OE
1
13
V reg(3.3)
5
VM
RSV PACKAGE
(BOTTOM VIEW)
VM
6
9
SU SP ND
16
15
14
V CC (5.0)
VM
V C C(I/O )
8
V pu(3 .3)
7
GND
V C C (I/O )
6
SO F TC O N
GND
5
RTZ PACKAGE
(BOTTOM VIEW)
SPE ED
S USPND
RGT PACKAGE
(BOTTOM VIEW)
PW PACKAGE
(TOP VIEW)
V p u(3 .3)
1
16 V C C (5 .0 )
SO FTCO N
2
15 V reg (3 .3 )
OE
3
14 V M O
R CV
4
13 V PO
VP
5
12 D +
VM
6
11 D −
S U S PN D
7
10 S PE E D
GN D
8
9
V C C (I /O )
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TUSB1105 TUSB1106
TUSB1105, TUSB1106
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
FUNCTIONAL BLOCK DIAGRAM
3.3 V
VCC(I/O)
Voltage
Regulator
VCC(5.0)
Vreg(3.3)
Vpu(3.3)
SOFTCON
1.5 kΩ(A)
OE
D+
SPEED
VMO/FSE0(B)
33 (1%)
D–
VPO/VO(B)
33 (1%)
MODE(C)
+
Level
Shifter
SUSPND
RCV
–
TUSB1105
TUSB1106
VP
VM
M B L30 1
GND
A.
Connect to D– for low-speed operation and to D+ for high-speed operation.
B.
Pin function depends on device type.
C.
TUSB1105 only
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME (1)
TUSB1105
PIN NO.
TUSB1106
PIN NO.
I/O
DESCRIPTION
RGT
RTZ
PW
RTZ
OE
1
1
3
1
I
Output enable (CMOS level with respect to VCC(I/O), active LOW). Enables
the transceiver to transmit data on the USB bus input pad. Push pull,
CMOS.
RCV
2
2
4
2
O
Differential data receiver (CMOS level with respect to VCC(I/O)). Driven LOW
when input SUSPND is HIGH. The output state of RCV is preserved and
stable during an SE0 condition output pad. Push pull, 4-mA output drive,
CMOS.
VP
3
3
5
3
O
Single-ended D+ receiver (CMOS level with respect to V). For external
detection of single-ended zero (SE0), error conditions, speed of connected
device. Driven HIGH when no supply voltage is connected to VCC(5.0) and
Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS.
VM
4
4
6
4
O
Single-ended D– receiver (CMOS level with respect to VCC(I/O)). For
external detection of single-ended zero (SE0), error conditions, speed of
connected device. Driven HIGH when no supply voltage is connected to
VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS.
SUSPND
5
5
7
5
I
Suspend (CMOS level with respect to VCC(I/O)). A HIGH level enables
low-power state while the USB bus is inactive and drives output RCV to a
LOW-level input pad. Push pull, CMOS.
MODE
6
6
I
Mode (CMOS level with respect to VCC(I/O)). A HIGH level enables the
differential input mode (VPO, VMO), whereas a LOW level enables a
single-ended input mode (VO, FSE0). See Table 5 and Table 6 input pad.
Push pull, CMOS.
(1)
Terminal names with an overscore (e.g., NAME) indicate active LOW signals.
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Product Folder Link(s): TUSB1105 TUSB1106
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TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
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Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME (1)
TUSB1105
PIN NO.
RGT
GND
RTZ
Die pad Die pad
VCC(I/O)
7
7
TUSB1106
PIN NO.
I/O
DESCRIPTION
PW
RTZ
8
6
Ground supply (2)
9
7
Supply voltage for digital I/O pins (1.65 to 3.6 V). When VCC(I/O) is not
connected, the D+ and D– pins are in 3-state. This supply pin is
independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3)
voltage.
Speed selection (CMOS level with respect to VCC(I/O)). Adjusts the slew rate
of differential data outputs D+ and D– according to the transmission speed.
Input pad, push pull, CMOS.
LOW – low speed (1.5 Mbit/s)
HIGH – full speed (12 Mbit/s)
SPEED
8
8
10
8
I
D–
9
9
11
9
AI/O
Negative USB data bus connection (analog, differential). For low-speed
mode, connect to pin Vpu(3.3) via a 1.5-kΩ resistor.
D+
10
10
12
10
AI/O
Positive USB data bus connection (analog, differential). For full-speed
mode, connect to pin Vpu(3.3) via a 1.5-kΩ resistor.
VPO/VO
11
11
VPO
13
VMO/FSE0
12
Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See
Driving Function Table (pin OE = L) using single-ended input data interface
for TUSB1105 (pin MODE = L), and Driving Function Table (pin OE = L)
using differential input data interface for TUSB1105 (pin MODE = H) and
TUSB1106 input pad. Push pull, CMOS.
I
Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See
Driving Function Table (pin OE = L) using single-ended input data interface
for TUSB1105 (pin MODE = L), and Driving Function Table (pin OE = L)
using differential input data interface for TUSB1105 (pin MODE = H) and
TUSB1106 input pad. Push pull, CMOS.
11
12
VMO
I
14
12
Vreg(3.3)
13
13
15
13
Internal regulator option. Regulated supply-voltage output (3 V to 3.6 V)
during 5-V operation. A decoupling capacitor of at least 0.1 mF is required
for the regulator bypass option. Used as a supply-voltage input for
3.3 V ± 10% operation.
VCC(5.0)
14
14
16
14
Internal regulator option. Supply-voltage input (4 V to 5.5 V). Can be
connected directly to USB supply VBUS regulator bypass option. Connect
to Vreg(3.3).
Pullup supply voltage (3.3 V ± 10%). Connect an external 1.5-kΩ resistor on
D+ (full speed) or D– (low speed). Pin function is controlled by input
SOFTCON.
SOFTCON = LOW – Vpu(3.3) floating (high impedance), ensures zero pullup
current
SOFTCON = HIGH – Vpu(3.3) = 3.3 V, internally connected to Vreg(3.3)
Vpu(3.3)
15
15
1
15
SOFTCON
16
16
2
16
(2)
4
I
Software-controlled USB connection. A HIGH level applies 3.3 V to pin
Vpu(3.3), which is connected to an external 1.5-kΩ pullup resistor. This allows
USB connect/disconnect signaling to be controlled by software input pad.
Push pull, CMOS.
TUSB1105 ground terminal is connected to the exposed die pad (heat sink). The package die pad is open on the TUSB1106.
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TUSB1105, TUSB1106
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
FUNCTIONAL DESCRIPTION
Function Selection
Table 2. FUNCTION TABLE
SUSPND
OE
D+, D–
RCV
VP, VM
L
L
Driving and receiving
Active
Active
Normal driving (differential receiver active)
L
H
Receiving (1)
Active
Active
Receiving
H
L
Driving
Inactive (2)
Active
Driving during suspend (3) (differential receiver inactive)
(2)
Active
Low-power state
H
(1)
(2)
(3)
H
High-Z
(1)
Inactive
FUNCTION
Signal levels on D+ and D– are determined by other USB devices and external pullup/pulldown resistors.
In suspend mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always LOW. Out of suspend (K), signaling is
detected via the single-ended receivers VP and VM.
During suspend, the slew-rate control circuit of low-speed operation is disabled. The D+ and D– lines are still driven to their intended
states, without slew-rate control. This is permitted because driving during suspend is used to signal remote wakeup by driving a K signal
(one transition from idle to K state) for a period of 1 ms to 15 ms.
Operating Functions
Table 3. FUNCTION TABLES
xxx
Driving Function (Pin OE = L)
Using Single-Ended Input Data Interface
for TUSB1105 (Pin MODE = L)
FSE0
VO
DATA
L
L
L
H
H
H
DATA STATE
LOW SPEED
FULL SPEED
Differential logic 0
J
K
Differential logic 1
K
J
L
SE0
X
X
H
SE0
X
X
Table 4. Driving Function (Pin OE = L)
Using Differential Input Data Interface
for TUSB1105 (Pin MODE = H) and TUSB1106
VMO
VPO
DATA
L
L
SE0
H
L
L
H
H
H
DATA STATE
LOW SPEED
FULL SPEED
X
X
Differential logic 0
J
K
Differential logic 1
K
J
Illegal state
X
X
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TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
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Table 5. Receiving Function (Pin OE = H)
DATA STATE
RCV
VP (1)
VM (1)
LOW
SPEED
FULL
SPEED
Differential
logic 0
L
L
H
J
K
Differential
logic 1
H
H
L
K
J
RCV* (2)
L
L
X
X
D+, D–
SE0
(1)
(2)
VP = VM = H indicates the sharing mode (VCC(5.0) and Vreg(3.3) are
disconnected).
RCV* denotes the signal level on output RCV just before SE0 state
occurs. This level is stable during the SE0 period.
Power-Supply Configurations
The TUSB1105/1106 can be used with different power-supply configurations, which can be dynamically changed.
An overview is given in Table 7.
• Normal mode – Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. For 5-V operation, VCC(5.0) is
connected to a 5-V source (4 V to 5.5 V). The internal voltage regulator then produces 3.3 V for the USB
connections. For 3.3-V operation, both VCC(5.0) and Vreg(3.3) are connected to a 3.3-V source (3 V to 3.6 V).
VCC(I/O) is independently connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of
the external circuit.
• Disable mode – VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. In this mode, the
internal circuits of the TUSB1105 and TUSB1106 ensure that the D+ and D– pins are in 3-state and the
power consumption drops to the low-power (suspended) state level. Some hysteresis is built into the
detection of VCC(I/O) lost.
• Sharing mode – VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In this mode, the D+ and D–
pins are made 3-state and the TUSB1105 and TUSB1106 allow external signals of up to 3.6 V to share the
D+ and D– lines. The internal circuits of the TUSB1105 and TUSB1106 ensure that virtually no current
(maximum 10 mA) is drawn via the D+ and D– lines. The power consumption through VCC(I/O) drops to the
low-power (suspended) state level. Both the VP and VM pins are driven HIGH to indicate this mode. Pin RCV
is made LOW. Some hysteresis is built into the detection of Vreg(3.3) lost.
Table 6. Pin States in Disable or Sharing Mode
PINS
DISABLE-MODE STATE
VCC(5.0)/Vreg(3.3)
Not present
VCC(I/O)
Not present
1.65-V to 3.6-V input
Vpu(3.3)
High impedance (off)
High impedance (off)
D+, D–
High impedance
High impedance
VP, VM
Invalid (1)
H
(1)
L
RCV
Invalid
Inputs (VO/VPO, FSE0/VMO, SPEED,
MODE (2), SUSPND, OE, SOFTCON)
(1)
(2)
SHARING-MODE STATE
5-V input/3.3-V output, 3.3-V input/3.3-V input
High impedance
High impedance
High impedance or driven LOW
TUSB1105 only
Table 7. Power-Supply Configuration Overview
(1)
6
VCC(5.0) or Vreg(3.3)
VCC(I/O)
CONFIGURATION
Connected
Connected
Normal mode
SPECIAL CHARACTERISTICS
Connected
Not connected
Disable mode
D+, D–, and Vpu(3.3) are in high impedance.
VP, VM, and RCV are invalid. (1)
Not connected
Connected
Sharing mode
D+, D–, and Vpu(3.3) are in high impedance.
VP and VM are driven HIGH. RCV is driven LOW.
High impedance or driven LOW
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
Power-Supply Input Options
The TUSB1105 and TUSB1106 have two power-supply input options.
• Internal regulator – VCC(5.0) is connected to 4 V to 5.5 V. The internal regulator is used to supply the internal
circuitry with 3.3 V (nominal). Vreg(3.3) becomes a 3.3-V output reference.
• Regulator bypass – VCC(5.0) and Vreg(3.3) are connected to the same supply. The internal regulator is bypassed
and the internal circuitry is supplied directly from the Vreg(3.3) power supply. The voltage range is
3 V to 3.6 V to comply with the USB specification.
The supply-voltage range for each input option is specified in Table 8.
Table 8. Power-Supply Input Options
INPUT OPTION
VCC(5.0)
VREG(3.3)
VCC(I/O)
Internal regulator
Supply input for internal regulator
(4 V to 5.5 V)
Voltage-reference output
(3.3 V, 300 mA)
Supply input for digital I/O pins
(1.65 V to 3.6 V)
Regulator bypass
Connected to Vreg(3.3) with
maximum voltage drop of 0.3 V
(2.7 V to 3.6 V)
Supply input
(3 V to 3.6 V)
Supply input for digital I/O pins
(1.65 V to 3.6 V)
Electrostatic Discharge (ESD)
PARAMETER
D+, D–, VCC(5.0), and GND
All other pins
TEST CONDITIONS
TYP
Human-Body Model
±15
IEC-61000-4-2, Contact Discharge
±8
Human-Body Model
7
UNIT
kV
kV
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC(5.0)
Supply voltage range
–0.5
6
V
VI(I/O)
Supply voltage range
–0.5
4.6
V
VCCreg(3.3)
Regulated voltage range
–0.5
4.6
V
VI
DC input voltage
–0.5
VCC(I/O) + 0.5
IIK
Input clamp current
Tstg
Storage temperature range
(1)
VI = –1.8 V to 5.4 V
–40
UNIT
V
100
mA
125
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN
NOM
MAX
4
5
5.5
V
3
3.3
3.6
V
3.6
V
0
VCC(I/O)
V
0
3.6
V
–40
85
°C
VCC(5.0)
Supply voltage, internal regulator option
5-V operation
VCCreg(3.3)
Supply voltage, regulator bypass option
3.3-V operation
VCC(I/O)
I/O supply voltage
1.65
VI
I/O supply voltage
VI/O
Input voltage on analog I/O pins (D+, D–)
Tc
Junction temperature
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7
TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
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Static Electrical Characteristics – Supply Pins
over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Vreg(3.3)
Regulated
supply-voltage output
Internal regulator option, Iload ≤ 300 mA (1)
ICC
Operating supply current
Full-speed transmitting and receiving at 12 Mbit/s,
CL = 50 pF on D+ and D– (3)
ICC(I/O)
Operating I/O supply current
Full-speed transmitting and receiving at 12 Mbit/s (3)
ICC(idle)
Supply current during
full-speed idle and SE0
Full-speed idle:
VD+ > 2.7 V, VD– < 0.3 V
SE0:
VD+ < 0.3 V, VD– < 0.3 V (4)
ICC(I/O)(static)
Static I/O supply current
Full-speed idle, SE0 or suspend
ICC(susp)
Suspend supply current
SUSPND = HIGH (4)
ICC(dis)
Disable-mode supply current
ICC(I/O)(sharing)
(2)
UNIT
3.3
3.6
6
8
mA
2.3
2.5
mA
500
mA
10
22
mA
10
22
mA
VCC(I/O) not connected (4)
10
22
mA
Sharing-mode I/O
supply current
VCC(5.0) or Vreg(3.3) not connected
10
22
mA
IDx(sharing)
Sharing-mode load current
on D+ and D–
VCC(5.0) or Vreg(3.3) not connected,
SOFTCON = LOW, VDx = 3.6 V
10
mA
Vreg(3.3)th
Regulated supply-voltage
detection threshold
1.65 V ≤ VCC(I/O) ≤ Vreg(3.3),
2.7 V ≤ Vreg(3.3) ≤ 3.6 V
Vreg(3.3)hys
Regulated supply-voltage
detection hysteresis
VCC(I/O) = 1.8 V
VCC(I/O)th
I/O supply-voltage
detection threshold
Vreg(3.3) = 2.7 V to 3.6 V
I/O supply-voltage
detection hysteresis
Vreg(3.3) = 3.3 V
VCC(I/O)hys
(1)
(2)
(3)
(4)
(5)
8
3
TYP MAX
Supply lost
during power down
Supply detect
during power up (5)
0.8
V
2.4
0.45
Supply lost
during power down
Supply detect
during power up
V
V
0.5
V
1.4
0.45
V
Iload includes the pullup resistor current via Vpu(3.3).
In suspend mode, the typical voltage is 2.8 V.
Maximum value is characterized only, not tested in production.
Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5-kΩ and 15-kΩ pullup and pulldown resistors (200 mA typ)
When VCC(I/O) < 2.7 V, the minimum value for Vreg(3.3)th (present) is 2 V.
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Product Folder Link(s): TUSB1105 TUSB1106
TUSB1105, TUSB1106
www.ti.com
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
Static Electrical Characteristics – Digital Pins
over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)
PARAMETER
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
TEST CONDITIONS
1.65 V to 3.6 V
IOL = 100 mA
IOL = 2 mA
IOL = 100 mA
VOL
LOW-level output voltage
IOL = 2 mA
IOL = 100 mA
IOL = 2 mA
IOL = 100 mA
IOL = 2 mA
IOH = 100 mA
IOH = 2 mA
IOH = 100 mA
VOH
HIGH-level output voltage
IOH = 2 mA
IOH = 100 mA
IOH = 2 mA
IOH = 100 mA
IOH = 2 mA
ILI
Input leakage current
CIN
Input capacitance
VCC(I/O)
MIN
1.65 V to 3.6 V
0.6 VCC(I/O)
0.4
0.15
0.15
0.4
VCC(I/O) – 0.15
VCC(I/O) – 0.4
1.5
1.25
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TUSB1105 TUSB1106
V
2.15
1.9
2.85
2.6
–1
Pin to GND
V
0.4
3.3 V ± 0.3 V
3.3 V ± 0.3 V
V
0.4
2.5 V ± 0.2 V
2.5 V ± 0.2 V
V
0.15
1.8 V ± 0.15 V
1.8 V ± 0.15 V
UNIT
0.15
1.65 V to 3.6 V
1.65 V to 3.6 V
MAX
0.3 VCC(I/O)
1
mA
3.5
pF
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TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
www.ti.com
Static Electrical Characteristics – Analog I/O Pins
over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V,
VGND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDI
Differential input sensitivity
|VI(D+) – VI(D–)|
0.2
VCM
Differential common-mode voltage
Includes VDI range
0.8
2.5
V
VIL
LOW-level input voltage, single-ended receiver
2
0.8
V
VIH
HIGH-level input voltage, single-ended receiver
0.4
Vhys
Hysteresis voltage, single-ended receiver
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
ILZ
OFF-state leakage current
CIN
Transceiver capacitance
ZDRV
Driver output impedance
ZINP
Input impedance
RSW
Internal switch resistance at Vpu(3.3)
VTERM
(1)
(2)
(3)
(4)
10
V
V
RL = 1.5 kΩ to 3.6 V
RL = 1.5 kΩ to GND
2.8
(1)
Pin to GND
Steady-state drive
34
(2)
39
0.7
V
0.3
V
3.6
V
1
mA
25
pF
44
10
Termination voltage for upstream port pullup (RPU)
3
(3) (4)
Ω
MΩ
13
Ω
3.6
V
VOH(min) = Vreg(3.3) – 0.2 V
Includes external resistors of 33 Ω ±1% on both D+ and D–
This voltage is available at Vreg(3.3) and Vpu(3.3).
In suspend mode, the minimum voltage is 2.7 V.
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
Dynamic Electrical Characteristics – Analog I/O Pins (D+, D–) (1)
Driver Characteristics, Full-Speed Mode
(2)
over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V,
VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
4
20
ns
tFR
Rise time
CL = 50 pF to 125 pF,
10% to 90% of |VOH – VOL| (see Figure 1)
tFF
Fall time
CL = 50 pF to 125 pF,
90% to 10% of |VOH – VOL| (see Figure 1)
4
20
ns
FRFM
Differential rise/fall time matching
(tFR/tFF)
Excluding the first transition from idle state
90
111.1
%
VCRS
Output signal crossover voltage
Excluding the first transition from idle state (see Figure 10)
1.3
2
V
(1)
(2)
Test circuit, see Figure 13
Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
Dynamic Electrical Characteristics – Analog I/O Pins (D+, D–) (1)
Driver Characteristics, Low-Speed Mode
(2)
over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V,
VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
75
300
ns
tLR
Rise time
CL = 200 pF to 600 pF,
10% to 90% of |VOH – VOL| (see Figure 1)
tLF
Fall time
CL = 200 pF to 600 pF,
90% to 10% of |VOH – VOL| (see Figure 1)
75
300
ns
LRFM
Differential rise/fall time matching
(tLR/tLF)
Excluding the first transition from idle state
80
125
%
VCRS
Output signal crossover voltage
Excluding the first transition from idle state (see Figure 10)
1.3
2
V
(1)
(2)
Test circuit, see Figure 13
Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
Dynamic Electrical Characteristics – Analog I/O Pins (D+, D–) (1)
Driver Timing, Full-Speed Mode
(2)
over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V,
VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C
(unless otherwise noted)
PARAMETER
tPLH(drv)
tPHL(drv)
tPHZ
tPLZ
tPZH
tPZL
(1)
(2)
TEST CONDITIONS
Driver propagation delay
(VO/VPO, FSE0/VMO to D+, D–)
Driver disable delay (OE to D+, D–)
Driver enable delay (OE to D+, D–)
MIN
MAX
LOW to HIGH (see Figure 4)
18
HIGH to LOW (see Figure 4)
18
HIGH to OFF (see Figure 2)
15
LOW to OFF (see Figure 2)
15
OFF to HIGH (see Figure 2)
15
OFF to LOW (see Figure 2)
15
UNIT
ns
ns
ns
Test circuit, see Figure 13
Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
Copyright © 2006–2010, Texas Instruments Incorporated
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11
TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
www.ti.com
Dynamic Electrical Characteristics for Analog I/O Pins (D+, D–) (1)
Receiver Timing, Full-Speed and Low-Speed Mode, Differential Receiver
over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V,
VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C
(unless otherwise noted)
PARAMETER
tPLH(rcv)
Propagation delay (D+, D– to RCV)
tPHL(rcv)
(1)
TEST CONDITIONS
MIN MAX
LOW to HIGH (see Figure 3)
15
HIGH to LOW (see Figure 3)
15
UNIT
ns
Test circuit, see Figure 13
Dynamic Electrical Characteristics for Analog I/O Pins (D+, D–) (1)
Receiver Timing, Full-Speed and Low-Speed Mode, Single-Ended Receiver
over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V,
VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C
(unless otherwise noted)
PARAMETER
tPLH(se)
Propagation delay (D+, D– to VP, VM)
tPHL(se)
(1)
TEST CONDITIONS
MAX
18
HIGH to LOW (see Figure 3)
18
UNIT
ns
Test circuit, see Figure 13
tFR,tLR
VOH
1.8 V
tFF,tLF
90%
0.9 V
Logic Input 0.9 V
90%
0V
10%
10%
VOL
MGS96 3
tPZH
tPZL
VOH
Figure 1. Rise and Fall Times
2.0 V
Differential
Data Lines
tPHZ
tPLZ
VOH − 0.3 V
Differential
Data Lines
VOL
VCRS
VOL + 0.3 V
MG S96 6
Figure 2. OE to D+, D–
1.8 V
VCRS
0.8 V
Logic Output
Logic Output 0.9 V
VCRS
tPLH(rcv)
tPLH(se)
VOH
Differential
Data Lines
MGS965
Figure 3. D+, D– to RCV, VP, VM
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tPLH(drv)
VOH
0.9 V
0.9 V
0.9 V
0V
tPHL(rcv)
tPHL(se)
VOL
12
MIN
LOW to HIGH (see Figure 3)
VCRS
tPHL(drv)
VCRS
VOL
MGS9 64
Figure 4. VO/VPO, FSE0/VMO to D+, D–
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TUSB1105 TUSB1106
TUSB1105, TUSB1106
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
APPLICATION INFORMATION
Test Point
33 Ω
500 Ω
D.U.T.
+
50 pF
V
–
MBL142
Figure 5. Load for Enable and Disable Times
A.
V = 0 V for tPZH, tPHZ
B.
V = Vreg(3.3) for tPZL, tPLZ
Test Point
25 pF
D.U.T.
MGS968
Figure 6. Load for VM, VP, and RCV
VPU(3.3)
1.5 kΩ
D.U.T.
D+/D–
33 Ω
CL
15 kΩ
Test Point
Figure 7. Load for D+, D–
A.
Full-speed mode: connected to D+
B.
Low-speed mode: Connected to D–
C.
Load capacitance:
A.
•
CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing)
•
CL = 200 pF or 600 pF (low-speed mode, minimum or maximum timing)
Only for TUSB1105
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TUSB1105 TUSB1106
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13
TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
www.ti.com
1.65 V to 3.6 V
3.3 V
0.1 µF
GND
V
V
OE
CC
CC(I/O)
V
reg(3.3)
SPEED
0.1 µF
SOFTCON
V
CC(5.0)
SUSPND
1.5 kW
V
(A)
MODE
System ASIC
V
GND
pu(3.3)
33 W
RCV
BUS
0.1 µF
GND
D+
VMO/FSE0
33 W
VPO/VO
D–
VP
TUSB1105/1106
VM
GND
GND
Figure 8. Peripheral-Side (Full-Speed) Regulator Bypass Mode
Peripheral-Side (Full-Speed) Regulator Bypass Mode
This mode is applicable when there is a 3.3-V supply already available on the board. The VBUS pin of the USB
connector, if left unused at the peripheral side, should be terminated with a 0.1-mF capacitor. While operating at
full speed, the 1.5-kΩ resistor must be connected between the D+ line and VPU(3.3) or an external 3.3-V supply.
When the VCC(5.0) and the Vreg(3.3) are connected together, the device operates at regulator bypass mode. This
enables power savings since the regulator is turned off.
A.
14
Only for TUSB1105
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
1.65 V to 3.6 V
3.3 V
0.1 µF
GND
V
V
OE
CC
CC(I/O)
V
reg(3.3)
SPEED
0.1 µF
SOFTCON
V
CC(5.0)
SUSPND
GND 1.5 kW
V
(A)
MODE
V
pu(3.3)
BUS
0.1 µF
RCV
System ASIC
33 W
GND
D+
VMO/FSE0
33 W
VPO/VO
D–
VP
TUSB1105/1106
VM
GND
GND
Figure 9. Peripheral-Side (Low-Speed) Regulator Bypass Mode
Peripheral-Side (Low-Speed) Regulator Bypass Mode
This mode is applicable when there is a 3.3-V supply already available on the board. The VBUS pin of the USB
connector, if left unused at the peripheral side, should be terminated with a 0.1-mF capacitor. While operating at
low speed, the 1.5-kΩ resistor must to be connected between the D– line and VPU(3.3) or an external 3.3-V
supply. When the VCC(5.0) and the Vreg(3.3) are connected together, the device operates at regulator bypass mode.
This enables power savings since the regulator is turned off.
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Product Folder Link(s): TUSB1105 TUSB1106
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TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
www.ti.com
1.65 V to 3.6 V
0.1 µF
GND
V
V
OE
CC
CC(I/O)
V
reg(3.3)
SPEED
0.1 µF
SOFTCON
V
CC(5.0)
SUSPND
GND
1.5 kW
(A)
MODE
System ASIC
V
V
0.1 µF
BUS
PU(3.3)
RCV
33 W
VMO/FSE0
D+
VPO/VO
D–
GND
33 W
VP
TUSB1105/1106
VM
GND
GND
Figure 10. Peripheral-Side (Full-Speed) Internal Regulator Mode
A.
Only for TUSB1105
Peripheral-Side (Full-Speed) Internal Regulator Mode
The USB side of the TUSB1105/1106 can be powered from the VBUS line directly if a 3.3-V supply is not present
on board. In this case, the internal regulator can be used to provide the 3.3-V supply for USB signaling. The
VCC(5.0) is connected to the VBUS, which receives 5-V supply from the host, and generates the 3.3-V output at the
Vreg(3.3) pin. In this mode, it is important that both VCC(5.0) and Vreg(3.3) pins have individual bypass capacitors in
the range of 0.1 mF. Powering VCC(5.0) through the VBUS port of the USB connector realizes significant power
saving for portable applications, such as cell phones, PDAs, etc. In this operating mode, the ICC(5.0) current is fed
from the host. The USB-side power consumption, ICC(5.0 ) is 4 mA (with the regulator active), as opposed to
logic-side ICC(IO) of 1 mA under full-speed operation. While operating at full speed, the 1.5-kΩ resistor must be
connected between the D+ line and the VPU(3.3) or an external 3.3-V supply.
16
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
1.65 V to 3.6 V
0.1 µF
GND
V
V
OE
CC
CC(I/O)
V
reg(3.3)
0.1 µF
SPEED
SOFTCON
GND
V
CC(5.0)
SUSPND
1.5 kW
(A)
MODE
V
V
BUS
PU(3.3)
RCV
System ASIC
0.1 µF
33 W
GND
D+
VMO/FSE0
33 W
D–
VPO/VO
VP
TUSB1105/1106
VM
GND
GND
Figure 11. Peripheral-Side (Low-Speed) Internal Regulator Mode
A.
Only for TUSB1105
Peripheral-Side (Low-Speed) Internal Regulator Mode
The USB side of the TUSB1105/1106 can be powered from the VBUS line directly if a 3.3-V supply is not present
on board. In this case, the internal regulator can be used to provide the 3.3-V supply for the USB signaling. The
VCC(5.0) is connected to the VBUS, which receives 5-V supply from the host, and generates the 3.3-V output at the
Vreg(3.3) pin. In this mode, it is important that both VCC(5.0) and Vreg(3.3) pins have individual bypass capacitors in
the range of 0.1 mF. Powering VCC(5.0) through the VBUS port of the USB connector realizes significant power
saving for portable applications, such as cell phones, PDAs, etc. In this operating mode, the ICC(5.0) current is fed
from the host side. The USB-side power consumption, ICC(5.0) is 4 mA (with the regulator active), as opposed to
logic-side ICC(IO) of 1 mA under full-speed operation. While operating at low speed, the 1.5-kΩ resistor must be
connected between the D- line and the VPU(3.3) or an external 3.3-V supply.
A.
Only for TUSB1105
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TUSB1105 TUSB1106
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TUSB1105, TUSB1106
SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
www.ti.com
1.65 V to 3.6 V
0.1 µF
GND
V
CC(I/O)
5V
5V
0.1 µF
V
reg(3.3)
SOFTCON
CC(5.0)
SUSPND
0.1 µF
V
CC
SPEED
GND
V
V
OE
V
BUS
pu(3.3)
MODE
GND
33 W
(A)
RCV
D+
System ASIC
VMO/FSE0
33 W
D–
VPO/VO
15 kW
VP
15 kW
TUSB1105/1106
VM
GND
GND
GND
GND
Figure 12. Host Side (VCC(5.0) Supplied From VBUS Pin)
Host Side (VCC(5.0) Supplied From VBUS Pin)
If there is no 3.3-V supply on board, an external 5-V supply can support the USB-side power needs. When the
VCC(5.0) is connected to an external 5-V supply, the on-chip regulator generates the 3.3-V internal supply rail,
which is used to drive the USB signaling levels at the USB side of the TUSB1105/1106. The logic-side I/Os can
operate at any voltage range from 1.65 V to 3.6 V.
A.
18
Only for TUSB1105
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TUSB1105, TUSB1106
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SCAS818E – MAY 2006 – REVISED SEPTEMBER 2010
1.65 V to 3.6 V
0.1 µF
3.3 V
GND
V
CC(I/O)
OE
V
CC
5V
V
reg(3.3)
SPEED
0.1 µF
SOFTCON
V
CC(5.0)
SUSPND
GND
V
BUS
V
pu(3.3)
(A)
MODE
33 W
RCV
D+
System ASIC
VMO/FSE0
33 W
D–
VPO/VO
15 kW
VP
15 kW
TUSB1105/1106
VM
GND
GND
GND
GND
Figure 13. Host-Side (3.3-V Supply Present) Internal Regulator Bypass Mode
Host-Side (3.3-V Supply Present) Internal Regulator Bypass Mode
If a 3.3-V supply supports the USB-side power, VCC(5.0) and Vreg(3.3) must to be tied together and connected to a
3.3-V supply. It also makes the regulator inactive.
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TUSB1105 TUSB1106
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB1105RGTR
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZYB
TUSB1105RGTRG4
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZYB
TUSB1105RTZR
ACTIVE
WQFN
RTZ
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ZYB
TUSB1106PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TU1106
TUSB1106PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TU1106
TUSB1106RGTR
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZYC
TUSB1106RSVR
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZYC
TUSB1106RTZR
ACTIVE
WQFN
RTZ
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ZYC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TUSB1106 :
• Automotive: TUSB1106-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TUSB1105RGTR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TUSB1105RTZR
WQFN
RTZ
16
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TUSB1106PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TUSB1106RGTR
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TUSB1106RSVR
UQFN
RSV
16
3000
180.0
12.4
2.1
2.9
0.75
4.0
12.0
Q1
TUSB1106RTZR
WQFN
RTZ
16
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB1105RGTR
VQFN
RGT
16
3000
346.0
346.0
35.0
TUSB1105RTZR
WQFN
RTZ
16
3000
346.0
346.0
35.0
TUSB1106PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
TUSB1106RGTR
VQFN
RGT
16
3000
346.0
346.0
35.0
TUSB1106RSVR
UQFN
RSV
16
3000
203.0
203.0
35.0
TUSB1106RTZR
WQFN
RTZ
16
3000
346.0
346.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016B
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.6 0.05
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
13
16
SYMM
16X
0.3
0.2
0.1
0.05
C A B
0.5
0.3
4219033/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.6)
SYMM
16
13
16X (0.6)
1
12
16X (0.25)
17
SYMM
(2.8)
(0.55)
TYP
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219033/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.47)
16
13
16X (0.6)
1
12
16X (0.25)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219033/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
SCALE 5.000
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
B
A
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
5
(0.13) TYP
8
15X
4
0.45
0.35
9
SYMM
2X 1.2
12X 0.4
1
12
16
0.55
0.45
16X
0.25
0.15
0.07
0.05
C A B
13
PIN 1 ID
(45 X 0.1)
4220314/B 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
1
16X (0.2)
SYMM
12X (0.4)
(R0.05) TYP
(2.4)
9
4
15X (0.6)
8
5
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4220314/B 05/2019
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
13
16
16X (0.2)
12
1
SYMM
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/B 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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