Texas Instruments | 5-V Dual Differential PECL Buffer-to-TTL Translator | Datasheet | Texas Instruments 5-V Dual Differential PECL Buffer-to-TTL Translator Datasheet

Texas Instruments 5-V Dual Differential PECL Buffer-to-TTL Translator Datasheet
SN65ELT23
www.ti.com....................................................................................................................................................................................................... SLLS925 – JUNE 2009
5-V Dual Differential PECL Buffer-to-TTL Translator
FEATURES
1
•
•
•
•
•
•
•
•
•
Dual 5-V Differential PECL-to-TTL Buffer
24-mA TTL Ouputs
Operating Range
– PECL VCC = 4.75 V to 5.25 V with
GND = 0 V
Support for Clock Frequencies of 250 MHz
(TYP)
3.5-ns Typical Propagation Delay
Output Default Low with Inputs Left Open or
<1.3 V
Internal Input 50-kΩ Pull-Down Resistor
Built-In Temperature Compensation
Drop-In Compatible to the MC100ELT23
PIN ASSIGNMENT
D or DGK PACKAGE
(TOP VIEW)
8 VCC
D0 2
7
Q0
D1 3
6
Q1
D1 4
5
GND
PECL
Data and Clock Transmission Over Backplane
Signaling Level Conversion for Clock or Data
DESCRIPTION
PIN
FUNCTION
D0, D0, D1, D1
PECL inputs
Q0, Q1
TTL outputs
VCC
Positive supply
GND
Ground
The SN65ELT23 is a low power dual PECL-to-TTL
translator device. The device includes circuitry to
maintain a known logic low level when inputs are in
an open condition. The SN65ELT23 is housed in an
industry standard SOIC-8 package and is also
available in an optional TSSOP-8 package.
ORDERING INFORMATION (1) (2)
(1)
(2)
TTL
Table 1. Pin Descriptions
APPLICATIONS
•
•
D0 1
PART NUMBER
PART MARKING
PACKAGE
LEAD FINISH
SN65ELT23D
SN65ELT23DGK
ELT23
SOIC
NiPdAu
SIKI
MSOP
NiPdAu
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Leaded device options are not initially available; contact a sales representative for further details.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN65ELT23
SLLS925 – JUNE 2009....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
PARAMETER
CONDITIONS
VALUE
UNIT
6
V
0 to 6
V
mA
Absolute supply voltage, VCC
Absolute input voltage, VI
GND = 0 and VI ≤ VCC
Output current
Continuous
50
Surge
100
Operating temperature range
–40 to 85
°C
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
CIRCUIT BOARD
MODEL
POWER RATING
TA < 25°C
(mW)
THERMAL RESISTANCE,
JUNCTION-TO-AMBIENT
NO AIRFLOW
DERATING FACTOR
TA > 25°C
(mW/°C)
POWER RATING
TA = 85°C
(mW)
SOIC
Low-K
719
139
7
288
High-K
840
119
8
336
Low-K
469
213
5
188
High-K
527
189
5
211
MSOP
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
θJB
Junction-to-board thermal resistance
θJC
Junction-to-case thermal resistance
MIN
TYP
SOIC
79
MSOP
120
SOIC
98
MSOP
74
MAX
UNIT
°C/W
°C/W
KEY ATTRIBUTES
CHARACTERISTICS
PARAMETER
Moisture sensitivity level
VALUE
Level 1
Flammability rating (oxygen index: 28 to 34)
UL 94 V-0 at 0.125 in
Internal pull down resistor
50 KΩ
Electrostatic discharge
Human body model
2 KV
Charged-device model
1.5 KV
Machine model
200 V
Meets or exceeds JEDEC Spec EIA/JESD78 latchup test
2
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Product Folder Link(s): SN65ELT23
SN65ELT23
www.ti.com....................................................................................................................................................................................................... SLLS925 – JUNE 2009
PECL INPUT DC CHARACTERISTICS
At VCC = 5.0 V, GND = 0.0 V (unless otherwise noted) (1) (2)
TEST
CONDITIONS
PARAMETER
VIH
High-level input voltage, single-ended
VIL
Low-level input voltage, single-ended
VIHCMR
High-level input voltage
common-mode range, differential
IIH
High-level input current
IIL
Low-level input current
(1)
(2)
(3)
(4)
See
(3)
See
(4)
TA = –40°C
MIN
TA = 25°C
TYP MAX
TA = 85°C
TYP MAX
UNIT
MIN
TYP MAX
4120 3835
4120
mV
3190 2280 3525 3190 2280 3525 3190 2280 3525
mV
3835
MIN
4120 3835
2.2
5.0
2.2
5.0
255
0.5
2.2
175
0.5
5.0
V
175
µA
µA
0.5
The device meets the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
Input and output parameters vary 1:1 with VCC. VCC can vary ±0.25 V.
TTL output RL = 500 Ω to GND
VIHCMR(min) varies 1:1 with GND, VIHCMR(max) varies 1:1 with VCC.
TTL OUTPUT DC CHARACTERISTICS
At VCC = 4.75 V to 5.25 V, TA = –40°C to 85°C (unles otherwiase noted) (1)
TYP
MAX
ICCH
Power supply current
PARAMETER
20
25
mA
ICCL
Power supply current
21
27
mA
IOS
Output short circuit current
–150
–50
mA
2.4
VCC – 0.7V
V
0.5
V
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
(2)
TEST CONDITIONS
(2)
MIN
IOH = –3.0 mA
IOL = 24 mA
UNIT
The device meets the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
Max level is assured by design
AC CHARACTERISTICS
At VCC = 5.0 V, GND = 0.0 V (unless otherwise noted) (1) (2) (3)
TEST
CONDITIONS
PARAMETER
TA = –40°C
MIN
fMAX
Max switching frequency
at Vol < 0.5V
and Voh >
2.4V (see
Figure 5)
tPLH/tPHL
Propagation delay times to output
At 1.5 V
tJITTER
Random clock jitter (RMS)
VPP
Input voltage swing
tr/tf
Output rise times (10%–90%)
1.0
Output fall times (10%–90%)
0.5
(1)
(2)
(3)
(4)
(4)
TA = 25°C
TYP MAX
MIN
250
2.0
MIN
250
3.5
5.0
4.1
10
200
TA = 85°C
TYP MAX
2.0
1000
200
1.7
3.0
1.0
1.0
1.6
0.5
TYP MAX
250
3.7
5.0
3.7
10
2.0
UNIT
MHz
3.9
5.0
3.7
10
ps
1000
mV
ns
1000
200
1.8
3.0
1.0
1.9
3.0
1.1
1.6
0.5
1.3
1.6
ns
The device meets the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
VCC can vary ±0.25 V.
TTL output RL = 500 Ω to GND and CL = 20 pF to GND, see Figure 1.
VPP(min) is the minimum input swing for which AC parameters are assured.
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Product Folder Link(s): SN65ELT23
3
SN65ELT23
SLLS925 – JUNE 2009....................................................................................................................................................................................................... www.ti.com
Typical Output Loading Used for Device Evaluation
Application
TTL Receiver
RL
*CL
*Includes fixture
Capacitance
AC TEST LOAD
GND
Figure 1. TTL Output Loading Used for Device Evaluation
90%
10%
tf
tr
Figure 2. Output Rise and Fall Times
IN
IN
1.5 V
1.5 V
OUT
tPLH
tPHL
Figure 3. Output Propagation Delay
D
VPP(min)
VPP(max)
D
Figure 4. Input Voltage Swing
4
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT23
SN65ELT23
www.ti.com....................................................................................................................................................................................................... SLLS925 – JUNE 2009
OUTPUT VOLTAGE
vs
FREQUENCY
5
VCC = 5 V
VOH @ TA = −40°C
VOL @ TA = 25°C
PO − Output Voltage − V
4
VOH @ TA = 85°C
3
VOH @ TA = 25°C
2
VOL @ TA = 85°C
1
VOL @ TA = −40°C
0
0
50
100
150
200
250
300
350
400
450
500
f − Frequency − MHz
G001
Figure 5.
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT23
5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN65ELT23D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ELT23
SN65ELT23DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SIKI
SN65ELT23DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SIKI
SN65ELT23DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ELT23
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65ELT23DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65ELT23DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65ELT23DGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
SN65ELT23DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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