Texas Instruments | 5-V PECL-to-TTL Translator | Datasheet | Texas Instruments 5-V PECL-to-TTL Translator Datasheet

Texas Instruments 5-V PECL-to-TTL Translator Datasheet
SN65ELT21
www.ti.com....................................................................................................................................................................................................... SLLS923 – JUNE 2009
5-V PECL-to-TTL Translator
FEATURES
1
•
•
•
•
•
•
3ns (TYP) Propagation Delay
Operating Range: VCC = 4.2 V to 5.7 V with
GND = 0 V
24-mA TTL Output
Deterministic Output Value for Open Input
Conditions or When Inputs < 1.3 V
Built-In Temperature Compensation
Drop-In Compatible to the MC10ELT21,
MC100ELT21
PIN ASSIGNMENT
D or DGK PACKAGE
(TOP VIEW)
APPLICATIONS
•
•
Data and Clock Transmission Over Backplane
Signaling Level Conversion for Clock or Data
NC
1
8
VCC
D
2
7
Q
D
3
6
NC
VBB
4
5
GND
DESCRIPTION
The SN65ELT21 is a differential PECL-to-TTL
translator. It operates on +5-V supply and ground
only. The device includes circuitry to maintain Q to a
low logic level when inputs are in an open condition
or < 1.3 V.
The VBB pin is a reference voltage output for the
device. When the device is used in single-ended
mode, the unused input should be tied to VBB. This
reference voltage can also be used to bias the input
when it is ac coupled. When it is used, place a
0.01µF decoupling capacitor between VCC and VBB.
Also limit the sink/source current to < 0.5 mA to VBB.
Leave VBB open when it is not used.
Table 1. Pin Descriptions
PIN
FUNCTION
D, D
PECL data inputs
Q
TTL output
VCC
Positive supply
VEE
Negative supply
VBB
Reference voltage output
The SN65ELT21 is housed in an industry standard
SOIC-8 package and is also available in an optional
TSSOP-8 package.
ORDERING INFORMATION (1) (2)
(1)
(2)
PART NUMBER
PART MARKING
PACKAGE
LEAD FINISH
SN65ELT21D
ELT21
SOIC
NiPdAu
SN65ELT21DGK
SIII
SOIC-TSSOP
NiPdAu
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Leaded device options are not initially available; contact a sales representative for further details.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN65ELT21
SLLS923 – JUNE 2009....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
PARAMETER
CONDITIONS
Absolute PECL mode supply voltage
VALUE
VCC (GND = 0 V)
Sink/source current, VBB
GND = 0 V, VI ≤ VCC
PECL input voltage
UNIT
6
V
±0.5
mA
6
V
Operating temperature range
–40 to 85
°C
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
CIRCUIT BOARD
MODEL
POWER RATING
TA < 25°C
(mW)
THERMAL RESISTANCE,
JUNCTION-TO-AMBIENT
NO AIRFLOW
DERATING FACTOR
TA > 25°C
(mW/°C)
POWER RATING
TA = 85°C
(mW)
SOIC
SOIC-TSSOP
Low-K
719
139
7
288
High-K
840
119
8
336
Low-K
469
213
5
188
High-K
527
189
5
211
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
θJB
Junction-to-board thermal resistance
SOIC
SOIC-TSSOP
θJC
Junction-to-case thermal resistance
MIN
TYP
MAX
79
UNIT
°C/W
120
SOIC
98
SOIC-TSSOP
74
°C/W
KEY ATTRIBUTES
CHARACTERISTICS
VALUE
Internal input pull-down resistor
50 kΩ
Moisture sensitivity level
Level 1
Flame ability rating (oxygen index: 28 to 34)
Electrostatic discharge
UL 94 V-0 at 0.125 in
Human body model
Charged-device model
2 kV
1.5 kV
Meets or exceeds JEDEC Spec EIA/JESD78 latchup test
2
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT21
SN65ELT21
www.ti.com....................................................................................................................................................................................................... SLLS923 – JUNE 2009
PECL DC CHARACTERISTICS
At VCC = 5.0 V, GND = 0.0 V (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
TA = –40°C
MIN
TA = 25°C
TYP MAX
MIN
TA = 85°C
TYP MAX
MIN
TYP
MAX
UNIT
VIH
High-level input voltage,
single-ended
3835
4120 3835
4120 3835
4120
mV
VIL
Low-leveI input voltage,
single-ended
3190
3525 3190
3525 3190
3525
mV
VBB
Output reference voltage
3.74
V
VIHCMR
High-level input voltage,
common-mode range,
differential
5.0
V
IIH
High-level input current
150
µA
IIL
Low-level input current
(1)
(2)
(3)
3.62
See
(3)
3.69
2.2
3.74
3.62
5.0
2.2
3.69
150
0.5
3.74
3.62
5.0
2.2
3.69
150
0.5
µA
0.5
The device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
Input parameters vary 1:1 with VCC. VCC can vary +0.7 V / –0.8 V.
VIHCMR(min) varies 1:1 with GND, VIHCMR(max) varies 1:1 with VCC.
TTL DC CHARACTERISTICS
At VCC = 4.2 V to 5.7 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICCH
Power supply current
20
mA
ICCL
Power supply current
20
mA
VOH
High-level output voltage
IOH = –3.0 mA
(2)
V
VOL
Low-level output voltage
IOL = 24 mA
IOS
Output short circuit current
(1)
(2)
2.4
See
–150
0.5
V
–60
mA
The device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
VOH(max) level is VCC – 0.7.
AC CHARACTERISTICS
At VCC = 4.2 V to 5.7 V, GND = 0.0 V (unless otherwise noted) (1) (2)
TEST
CONDITIONS
PARAMETER
fMAX
Maximum switching
frequency
At Vol < 0.5V
(See Figure 4)
tPLH/tPHL
Propagation delay times
At 1.5 V
tJITTER
Random clock jitter (RMS)
Input swing
See
tr/tf
Output rise/fall times
Q (10%–90%)
(2)
(3)
MIN
200
200
TA = 85°C
TYP MAX
MIN
200
4.5
5
(3)
TA = 25°C
TYP MAX
2
VPP
(1)
TA = –40°C
MIN
2
20
1000
750
200
4.5
5
200
2
20
1000
780
TYP MAX
5
200
UNIT
MHz
4.5
ns
20
ps
1000
mV
910
ps
The device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
RL = 500 Ω to GND and CL = 20 pF to GND. See Figure 1.
VPP(min) is minimum input swing for which ac parameters are assured.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT21
3
SN65ELT21
SLLS923 – JUNE 2009....................................................................................................................................................................................................... www.ti.com
TTL Output
CL Includes Test
Fixture Capacitance
CL
RL
AC Test Load
GND
Figure 1. TTL Output AC Test Loading Condition
IN
IN
1.5 V
1.5 V
OUT
tPLH
tPHL
Figure 2. Output Propagation Delay
90%
10%
tr
tf
Figure 3. Output Rise and Fall Times
4
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT21
SN65ELT21
www.ti.com....................................................................................................................................................................................................... SLLS923 – JUNE 2009
OUTPUT VOLTAGE
vs
FREQUENCY
5
VOH 85
Output Voltage - V
4
VOH 25
VOH -40
3
VOL 85
VOL 25
2
VOL -40
1
VCC = 5.0V
0
0
50 100 150 200 250 300 350 400 450 500
Frequency - MHz
Figure 4.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT21
5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN65ELT21D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ELT21
SN65ELT21DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SIII
SN65ELT21DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SIII
SN65ELT21DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ELT21
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65ELT21DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65ELT21DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65ELT21DGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
SN65ELT21DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising