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Texas Instruments TMDS181 Schematic Checklist Application notes
Application Report
SLAA893 – April 2019
TMDS181 Schematic Checklist
ABSTRACT
This schematic checklist provides a brief explanation of each TMDS181 device pin and the recommended
configuration of TMDS181 device pins for default operation. The TMDS181 is a digital video interface
(DVI) or high-definition multimedia interface (HDMI) retimer. The TMDS181 supports four TMDS channels,
audio return channel (SPDIF_IN/ARC_OUT), and digital display control (DDC) interfaces. The TMDS181
has the ability to be configured via pin strap or I2C. Use this information to check the connectivity for each
TMDS181 device on a system schematic.
This document is intended to aid design at the system level for general applications but must not be the
only resource used. In addition to this list, use the information from the TMDS181x 6 Gbps TMDS Retimer
Data Sheet, TMDS181RGZ Evaluation Module User's Guide, and associated documents to gain a full
understanding of device functionality.
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2
Contents
TMDS181 Schematic Checklist ............................................................................................ 1
References ................................................................................................................... 5
List of Figures
...............................................................
1
External Termination Network for AC-coupled Interface
2
Audio Channel Implementation ............................................................................................ 5
5
List of Tables
1
TMDS181 Schematic Checklist for Default Operation .................................................................. 1
2
Enable (OE) Pin Timing Based on Capacitance ......................................................................... 4
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1
TMDS181 Schematic Checklist
Table 1. TMDS181 Schematic Checklist for Default Operation
PIN NAME
PIN DESCRIPTION
RECOMMENDATION
8, 9, 5, 6, 2, 3
Main link differential
input
Direct connection from
connector/GPU to
TMDS181
11, 12
Main link clock
differential input
Direct connection from
connector/GPU to
TMDS181
PIN NUMBER(S)
ADDITIONAL
COMMENT
MAIN LINK INPUT PINS
IN_D[0:2]p/n
IN_CLKp/n
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TMDS181 Schematic Checklist
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Table 1. TMDS181 Schematic Checklist for Default Operation (continued)
PIN NAME
PIN NUMBER(S)
PIN DESCRIPTION
RECOMMENDATION
ADDITIONAL
COMMENT
TMDS data differential
output
Direct connection from
TMDS181 to
connector/receiver
Output can be ACcoupled, but require
external termination
network, see Figure 1.
TMDS181 output
amplitude needs to be
increased to
compensate for the
double termination.
TMDS clock differential
output
Direct connection from
TMDS181 to
connector/receiver
Output can be ACcoupled, but require
external termination
network, see Figure 1.
TMDS181 output
amplitude needs to be
increased to
compensate for the
double termination.
Source side TMDS
bidirectional DDC data
line
Snoop mode, tie it to
GND
Source side TMDS
bidirectional DDC clock
line
Snoop mode, tie it to
GND
Sink side TMDS
bidirectional DDC data
line
SDA/SCL from the
source is connected
directly to theSDA/SCL
sink. The TMDS181 will
need its SDA_SNK and
SCL_SNK pins
connected to this link in
order to correctly
configure the
TMDS_CLOCK_RATIO_
STATUS bit.Sink
application: 47k pull-ups
to 5V Source
application: 2k pull-ups
to 5V
Consider adding an
external I2C buffer for
DDC capacitance
isolation
Sink side TMDS
bidirectional DDC clock
line
SDA/SCL from the
source is connected
directly to theSDA/SCL
sink. The TMDS181 will
need its SDA_SNK and
SCL_SNK pins
connected to this link in
order to correctly
configure the
TMDS_CLOCK_RATIO_
STATUS bit.Sink
application: 47k pull-ups
to 5V Source
application: 2k pull-ups
to 5V
Consider adding an
external I2C buffer for
DDC capacitance
isolation
MAIN LINK OUTPUT PINS
OUT_D[0:2]p/n
28, 29, 31, 32, 34, 35
OUT_CLKp/n
26, 25
DDC PINS
SDA_SRC
47
SCL_SRC
46
SDA_SNK
39
SCL_SNK
2
38
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Table 1. TMDS181 Schematic Checklist for Default Operation (continued)
PIN NAME
PIN NUMBER(S)
PIN DESCRIPTION
RECOMMENDATION
ADDITIONAL
COMMENT
Connect to HPD output
for the display and
connector. For snoop
mode: Connect directly
to Sink’s/GPU’s(Check
GPU supported voltage)
directly connected HPD
line HPD_SNK has
internal 190 k pull-down.
Consider adding an
external switch to isolate
potential leakage
voltage from sink HPD
when sink is off
HOT PLUG DETECT PINS
HPD_SNK
33
Hot plug detect input
from sink side
HPD_SRC
4
Hot plug detect output to If HPD_SRC goes to the
source side
source connector a level
shifter from 3.3 V to 5 V
is needed. If HPD_SRC
goes to GPU, check
supported GPU
voltages. If HPD snoop
mode is implemented,
leave HPD_SRC floated.
AUDIO RETURN CHANNEL PINS
SPDIF_IN
45
SPDIF signal input
If not needed: 500 k
pull-down.
Implementation
dependent, see Figure 2
SPDIF_IN -> HDMI sink
SPDIF_IN_2 ->
TMDS181
ARC_OUT
44
Audio return channel
output
if not needed: NC
Implementation
dependent,see Figure 2
OE
42
Enable/reset pin
Start with 0.2uF, tune
depending on the RC
time constant delay (Tr)
requirement in regard to
power ramp up time
Vsadj
22
TMDS-compliant voltage Start with 7.06 k resistor
swing control resistor
to ground, resistor value
tuning depends on
compliance result
SCL_CTL
15
I2C clock signal
2 k pull-ups to 3.3 V or
value required by I2C
master
SDA_CTL
16
I2C data signal
2 k pull-ups to 3.3 V or
value required by I2C
maste
I2C_EN/PIN
10
I2C control mode
65 k pull-down for pin
strap mode
65 k pull-up for I2C
mode
EQ_SEL/A0
21
Input receive
equalization
NC for adaptive EQ in
pin strap mode
65 k pull-up or pull-down
in I2C mode
A1
27
Input receive
equalization
NC in pin strap mode
65 k pull-up or pull-down
in I2C mode
SIG_EN
17
High address I2C bit for
I2C programming
65 k pull-down or pullup
to enable/disable signal
detector
Recommend 65 k pulldown to disable signal
detect circuit
CONTROL PINS
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See Table 2 for different
timing values based on
capacitance.
TMDS181 Schematic Checklist
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TMDS181 Schematic Checklist
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Table 1. TMDS181 Schematic Checklist for Default Operation (continued)
PIN NAME
PIN NUMBER(S)
PRE_SEL
PIN DESCRIPTION
RECOMMENDATION
ADDITIONAL
COMMENT
Signal detector circuit
enable
PRE_SEL = L: -2dB
PRE_SEL = NC: 0dB
PRE_SEL = H:
Reserved
Leave it floating when
I2C_EN/PIN = high,
control through I2C
20
TX_TERM_CTL
36
Transmit termination
control
NC for automatic Tx
termination
SWAP/POL
1
Input lane SWAP and
polarity control
Default NC, 65 k pull-up
or pull-down if needed
VCC
13, 43
3.3 V power supply
One 100 nF cap on
each power pin.
4.7 pF and 10 pF on
each power node. One
bulky cap per power
node
VDD
12, 23, 24, 37, 48
1.1 V power supply
One 100nF cap on each
power pin.
4.7pF and 10pF on each
power node. One bulky
cap per power node
7, 19 ,41, 30
Ground
Connect to board
ground
49
Ground
Connect to board
ground
POWER PINS
Thermal Pad
Table 2. Enable (OE) Pin Timing Based on Capacitance
RISE TIME (Tr) (ms)
4
CAPACITOR VALUE (µF)
25
0.1
50
0.2
100
0.4
200
0.8
500
2
TMDS181 Schematic Checklist
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References
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Figure 1. External Termination Network for AC-coupled Interface
Figure 2. Audio Channel Implementation
2
References
•
•
TMDS181x 6 Gbps TMDS Retimer Data Sheet
TMDS181RGZ Evaluation Module User's Guide
SLAA893 – April 2019
Submit Documentation Feedback
TMDS181 Schematic Checklist
Copyright © 2019, Texas Instruments Incorporated
5
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