Texas Instruments | TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E Implementation (Rev. A) | Application notes | Texas Instruments TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E Implementation (Rev. A) Application notes

Texas Instruments TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E Implementation (Rev. A) Application notes
Application Report
SLLA403A – May 2018 – Revised December 2018
TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment
C and E Implementation
David Liu
ABSTRACT
The TUSB564 is a VESA USB Type-C™ Alt Mode redriving switch supporting USB 3.1 data rates up
to 5 Gbps and DisplayPort 1.4 up to 8.1 Gbps for upstream facing port (DisplayPort Sink). The device is
used for UFP pin assignments C, D, and E from the VESA DisplayPort Alt Mode on USB Type-C
Standard. For DisplayPort Sink that does not natively support assignment E, this document is intended to
describe how to use the TUSB564, HD3SS460 and TS3USBCA410 to implement such user case.
Trademarks
All trademarks are the property of their respective owners.
1
Overview
VESA defines different pin assignments on the USB Type-C connector when sending and receiving
DisplayPort signaling. Six possible pin assignments are defined for USB Type-C configured to perform as
a Display Source (DFP_D) – A, B, C, D, E, or F. Five possible pin assignments are defined for USB TypeC configured to perform as a Display Sink (UFP_D) – A, B, C, D, or E.
Pin Assignments A, B, C, and D are intended for use with:
• USB Type-C to USB Type-C Cables
• Adaptors from USB Type-C to other video standards such as VGA, DVI, HDMI.
Pin Assignments E and F are intended for use with adaptors from USB Type-C to DisplayPort plugs or
receptacles. For additional details on pin assignment, refer to the DP_Alt_Mode_on_USB_Type-C
specification.
With UFP_D Pin Assignment E, the polarity of both the main link and AUX signals is inverted on the TypeC receptacle pins relative to Pin Assignment C.
Assignment E normal plug orientation main link signal:
• Lane 0 → DP1
• Lane 1 → DP0
• Lane 2 → DP3
• Lane 3 → DP2
Assignment E normal plug orientation AUX signal:
• SBU1 — AUXP
• SBU2 — AUXN
For DisplayPort sink that has the capability to handle the main link ordering and polarity swap, but does
not have the ability to handle pullup/pulldown on AUX, TI proposes the use of TUSB564 and
TS3USBCA410. TS3USBCA410 with polarity flip capability will ensure correct pull up/down alignment to
enable both Assignment C & E can be supported in the system.
SLLA403A – May 2018 – Revised December 2018
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TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E
Implementation
Copyright © 2018, Texas Instruments Incorporated
1
Overview
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Figure 1. USB-C Block Diagram with Scaler
For DisplayPort sink that cannot perform the main link and AUX inversion. TI proposes the use of
TUSB564 and HD3SS460 to support Assignment E implementation. In all these configurations, the
TUSB564 passes the polarity of the Main Link signals as received. The DisplayPort sink must change the
polarity inversion of those signals.
2
TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E
Implementation
SLLA403A – May 2018 – Revised December 2018
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Copyright © 2018, Texas Instruments Incorporated
www.ti.com
2
TUSB564 and HD3SS460 Pin Assignment C Normal Plug Orientation Implementation
TUSB564 and HD3SS460 Pin Assignment C Normal Plug Orientation Implementation
Figure 2 shows the pin assignment C normal plug orientation implementation.
Figure 2. Assignment C Normal Plug Orientation Implementation
3
TUSB564 and HD3SS460 Pin Assignment C Flip Plug Orientation Implementation
Figure 3 shows the pin assignment C flip plug orientation implementation.
Figure 3. Assignment C Flip Plug Orientation Implementation
SLLA403A – May 2018 – Revised December 2018
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TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E
Implementation
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3
TUSB564 and HD3SS460 Pin Assignment E Normal Plug Orientation Implementation
4
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TUSB564 and HD3SS460 Pin Assignment E Normal Plug Orientation Implementation
Figure 4 shows the pin assignment E normal plug orientation implementation.
Figure 4. Assignment E Normal Plug Orientation Implementation
5
TUSB564 and HD3SS460 Pin Assignment E Flip Plug Orientation Implementation
Figure 5 shows the pin assignment E flip plug orientation implementation.
Figure 5. Assignment E Flip Plug Orientation Implementation
4
TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E
Implementation
SLLA403A – May 2018 – Revised December 2018
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Copyright © 2018, Texas Instruments Incorporated
TUSB564 and HD3SS450 Assignment C and E Implementation Reference Schematic
www.ti.com
6
TUSB564 and HD3SS450 Assignment C and E Implementation Reference Schematic
3.3V
C30
C29
C28
C27
10uF
0.1uF
01.uF
0.1uF
C_SSTXN
C25
0.1uF
SSTXN
C_SSTXP
C26
0.1uF
SSTXP
USB2_DN
VBUS
3.3V
C23
C24
0.1uF
10uF
CC1
EQ1
14
RX2N C11
0.22uF
C_RX2N
15
RX2P C12
0.22uF
C_RX2P
16
18
19
A11
A10
I2C_EN
B2
B3
TX2N
C13
0.22uF
C_TX2N
TX2P
C14
0.22uF
C_TX2P
B11
B10
17
20
TO PD CONTROLLER
FLIP
CTL0
CTL1
SBU1
SBU2
R9
R10
R11
22
DP1N
TUSB564
DPEQ0/A1
RX2n
DP2P
RX2p
DP2N
I2C_EN
HPDIN
TX2n
TX2p
VCC
DP3P
DP3N
EN
VCC
2
3
4
5
6
1
NC
DPEQ1
SSEQ1
SSRXp
SSRXn
RX1n
A1
A12
B1
B12
TypeC_Receptacle_DualSMT_TOP
7
8
DP1P
EQ1
U2
39
38
SSEQ0
37
DP0_P
DP0_N
1
2
DP1_P
DP1_N
4
5
DP3P
DP3N
6
7
DP2_P
DP2_N
9
10
36
35
DPEQ0
34
33
32
SSTXN
SSTXP
CRX1P
CRX1N
SSRXN
SSRXP
CTX1P
CTX1N
LNAN
LNAP
CTX2P
CTX2N
LNBN
LNBP
CRX2P
CRX2N
LNCN
LNCP
TO PD CONTROLLER AND
DP SINK
HPDIN
31
30
29
POL
AMSEL
EN
11
12
TO DP SINK
EN
LNDN
LNDP
CSBU1
CSBU2
SBU1
SBU2
3
8
17
POL
AMSEL
EN
TO PD CONTROLLER
25
26
27
28
15
16
C15
C16
0.1uF
0.1uF
DP2_N
DP2_P
18
19
C17
C18
0.1uF
0.1uF
DP3_N
DP3_P
20
21
C19
C20
0.1uF
0.1uF
DP1_N
DP1_P
23
24
C21
C22
0.1uF
0.1uF
DP0_N
DP0_P
13
14
TO DP SINK
3.3V
PAD
A2
A3
SSEQ0/A0
RX1p
40
29
B6
B7
EQ0
VCC
13
AUXn
12
C_RX1N
41
28
C_RX1P
0.22uF
AUXp
0.22uF
C10
27
11
C9
RX1N
26
EQ0
RX1P
DP0P
DP0N
SBU2
A7
A6
PAD/GND
TX1n
SBU1
A8
B8
TX1p
VCC
10
SSTXp
9
C_TX1N
SSTXn
C_TX1P
0.22uF
25
Shield10 SSTXP2
Shield9 SSTXN2
Shield8
Shield7 SSRXP1
Shield6 SSRXN1
Shield5
Shield4
GND0
Shield3
GND1
Shield2
GND2
Shield1
GND3
0.22uF
C8
CTL1
SSTXP1
SSTXN1
SSRXP2
SSRXN2
C7
TX1N
24
DP2
DN2
TX1P
23
DN1
DP1
A5
B5
U1
CTL0/SDA
SBU1
SBU2
CC2
FLIP/SCL
CC1
CC2
TO PD CONTROLLER
A4
A9
B4
B9
21
VBUS1
VBUS2
VBUS3
VBUS4
22
J1
10
9
8
7
6
5
4
3
2
1
USB 3.1
SSRXN
SSRXP
SSEQ1
DPEQ1
USB2_DP
HD3SS460
R1
1M
0 FLIP_SCL
0 CTL0_SDA
0
AUXP
AUXN
UNPOPULATE R9, R10, AND R11 FOR I2C MODE
C5
0.1uF
AUXP
C6
0.1uF
AUXN
R2
1M
R3
2M
R4
2M
VCC_BAR
3.3V
564_SCL
564_SDA
R6
R5
2K
2K
R7
R8
0
0
FLIP_SCL
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R12
R13
R14
R15
R16
R17
R18
1K
1K
1K
1K
1K
1K
1K
R19
R20
R21
R22
R23
R24
R25
1K
1K
1K
1K
1K
1K
1K
I2C_EN
EQ0
EQ1
DPEQ0
DPEQ1
SSEQ0
SSEQ1
CTL0/SDA
TUSB564 I2C ACCESS
UNPOPULATE R7 AND R8 FOR GPIO MODE
TUSB564 CONTROL PIN IN GPIO MODE
MAIN LINK SETTING
CTL1
CTL0
FLIP
ASSIGNMENT C NORMAL
H
L
L
POL
L
AMSEL
H
H
EN
ASSIGNMENT C FLIP
H
L
H
L
H
H
ASSIGNMENT E NORMAL
H
L
L
H
H
H
ASSIGNMENT E FLIP
H
L
H
H
H
H
A
Figure 6. Reference Schematic
SLLA403A – May 2018 – Revised December 2018
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TUSB564, HD3SS460 and TS3USBCA410 Pin Assignment C and E
Implementation
Copyright © 2018, Texas Instruments Incorporated
5
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2018) to A Revision ........................................................................................................... Page
•
6
Added information on using TUSB564, HD3SS460 and TS3USBCA410 in a USB-C application with pin assignment C and
E implemented. ........................................................................................................................... 1
Revision History
SLLA403A – May 2018 – Revised December 2018
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Copyright © 2018, Texas Instruments Incorporated
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