Texas Instruments | Configuring Ethernet Devices With 4-Level Straps (Rev. A) | Application notes | Texas Instruments Configuring Ethernet Devices With 4-Level Straps (Rev. A) Application notes

Texas Instruments Configuring Ethernet Devices With 4-Level Straps (Rev. A) Application notes
Application Report
SNLA258A – July 2016 – Revised September 2018
4-Level Strap Device Configuration
Robert Rodrigues
ABSTRACT
4-Level Strap Device Configuration serves as a guide to configure Texas Instruments Ethernet PHYs that
feature 4-level strap pins.
4-level straps require more consideration than simple 2-level straps. This configuration note guides a
design engineer through implementation of a 4-level strap, and evaluation of the strap in worst case
conditions.
Some of the items covered are resistor tolerance considerations, resistor temperature coefficient
consideration, and PHY and MAC leakage current.
1
2
3
Contents
Introduction ................................................................................................................... 2
Using 4-Level Straps ........................................................................................................ 2
Analysis of a 4-Level Strap Pin Voltage .................................................................................. 5
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4-Level Strap Device Configuration
1
Introduction
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(1)
1
Introduction
Current generation Ethernet PHYs contain many more configurable features than earlier PHYs. The
number of features configured at start-up, like multiple MAC interfaces, MAC interface timing, PHY
address, EEE capability, and reference clock frequency, can outnumber the I/O pins available on a PHY.
To configure more options than I/O pins, 4-level straps have been introduced to allow a single I/O pin to
configure 2 features.
4-level straps require a resistive divider to implement, compared to 2-level straps that use a single
resistor. 4-level straps must reliably create a voltage on the I/O pin that corresponds to a defined band.
Careful consideration of resistor tolerance and temperature coefficient is key to ensuring proper voltage on
the strap at the time of latch-in. This application note details how to use 4-level straps and how to analyze
a 4-level strap for reliable operation.
2
Using 4-Level Straps
Texas Instruments' 4-level and 2-level straps are configured at power-up, or by hardware reset (RESET_N
pin). The PHY will sample the voltage at each of its designated strap pins once the supply has ramped or
post reset deassertion. This process is called latch-in. The ratio of Rhi, the resistor located between the
VDDIO supply and the I/O pin, and of Rlo, the resistor placed between ground and the I/O pin, can be
modified to configure the PHY for different modes of operation.
VDDIO
Rhi
V
I/O Pin
Rpull
Rlo
Figure 1. Generic 4-Level Strap Diagram (Internal Pull-Down)
VDDIO
VDDIO
Rpull
Rhi
V
I/O Pin
Rlo
Figure 2. Generic 4-Level Strap Diagram (Internal Pull-Up)
(1)
2
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Using 4-Level Straps
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See the appropriate device data sheet for details on strap options for that device.
2.1
Determining Strap Mode From Datasheet
The following example details what is needed to determine the desired strap mode and the correct way to
implement the 4-level strap.
The PHY's address will be set to 0x0002 for this example. Below is an example strap pin table containing
PHY Address (PHY_ID) bits [3:0]. There are four PHY_ID pin straps that allow for PHY Address
configurations between 0x0000 and 0x000F.
Table 1. Strap Function Table (Pull-Down)
PIN NAME
PIN #
RX_D0 /
SGMII_COP
DEFAULT
33
RX_D2 /
SGMII_CON
STRAP FUNCTION
MODE
PHY_ADD1
PHY_ADD0
1
0
0
2
0
1
3
1
0
4
1
1
MODE
PHY_ADD3
PHY_ADD2
1
0
0
2
0
1
3
1
0
4
1
1
[00]
35
[00]
To achieve a PHY ID of 0x2, PHY ID bit [1] should be set, and all other bits cleared. Referencing the
above table, RX_D0 pin will be strapped to mode three, and RX_D2 pin must be strapped to mode 1. Note
that the default setting of both of these pins is 0b00. The default setting is the value that will be strapped
into the PHY if no strap resistors are present during latch-in. Because the default setting for RX_D2 is
acceptable, RX_D2 will not be connected to any external resistors.
To strap pin RX_D0 to mode three, the strap resistor ratio table of the device is referenced. See the
example table below.
Note: Strap pins have internal pull-up or pull-down resistors. This will change which table is referenced
when dealing with devices that feature strap pins with both pull types. Ensure that the proper resistor ratio
table is referenced based on resistor pull type.
Table 2. 4-Level Strap Resistor Ratios (Pull-Down)
TARGET VOLTAGE
MODE
Vmin (V)
Vtyp (V)
Vmax (V)
IDEAL Rhi (kΩ)
IDEAL Rlo (kΩ)
1
0
0
0.098 × VDDIO
OPEN
OPEN
2
0.140 × VDDIO
0.165 × VDDIO
0.191 × VDDIO
10
2.49
3
0.225 × VDDIO
0.255 × VDDIO
0.284 × VDDIO
5.76
2.49
4
0.694 × VDDIO
0.783 × VDDIO
0.888 × VDDIO
2.49
OPEN
Table 3. 4-Level Strap Resistor Ratios (Pull-Up) (1)
MODE
(1)
TARGET VOLTAGE
Vmin (V)
Vtyp (V)
Vmax (V)
IDEAL Rhi (kΩ)
IDEAL Rlo (kΩ)
1
0
0
0.182
OPEN
1.96
2
0.475
0.528
0.598
13
1.96
3
0.772
0.858
0.944
6.20
1.96
4
1.782
1.98
2.178
OPEN
OPEN
VDDIO = 3.3 V
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Using 4-Level Straps
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To place RX_D0 strap in mode three, when RX_D0 contains an internal pull-down resistor, Table 2 should
be referenced for the strap voltage requirements.
In a typical application, the ideal resistor values for the desired mode can be used. In special cases, the
strap’s resistive divider should be analyzed to ensure it falls into the voltage range for the mode. Special
cases include having an external pull resistor attached to the pin or use with MACs that have excessive
leakage current (greater than 15 µA).
2.2
2.2.1
Considerations for 4-Level Strap Use
Resistor Tolerance
Resistor tolerance is the largest factor for meeting the voltage requirements of the strap pin modes.
Resistors should be no more than 1% tolerance for reliable performance.
2.2.2
External Pull Resistors
A common challenge to strap resistive dividers is the presence of a pull-up or pull-down resistor inside of
the attached MAC. When using a strap with a resistor internal to the connected MAC, the ideal resistor
values cannot be used and a full analysis must be performed.
2.2.3
Leakage Current
Leakage current poses a source of error in the voltage presented to the strap pin. When the leakage
current of a MAC’s pins exceeds 15 µA, it may be necessary to perform a detailed analysis of the strap
pins.
2.2.4
Temperature Variation
System ambient temperatures can be higher than the ideal room temperature of 25ºC when PHY straps
are latched-in. During those cases the temperature coefficient of resistance (TCR) of a resistor can have a
large impact on the strap’s divider.
For example, a resistor with a 100 ppm/ºC TCR may vary as much as 0.8% at 105ºC from its resistance at
25ºC. This effect is compounded with the tolerance of the resistor to create an error of up to 1.8%. TCR is
treated in the detailed analysis section. TCR is assumed to be negative when considering minimum
tolerance, positive when treating maximum tolerance, and linear. This assumption provides a worst case
scenario.
2.2.5
Capacitance External to the Strap Pin
4-level strap pins are latched-in quickly during device power up and reset. As such, a large capacitance
should not be connected to the strap pin without a shunt resistor. If this is ignored, the capacitor may not
charge or discharge completely before the voltage is sampled on the pin. This leads to strapping
unintended values into the PHY.
2.2.6
SGMII Impedance Balancing
When placing a strap resistor divider on a pin that is used for an SGMII interface, like the DP83867E’s
SGMII_SOP pin, an identical resistor divider must be placed on the corresponding pin of the differential
pair, in this case the SGMII_SON pin. This ensures the high-speed LVDS interface has balanced
impedance on both lines, preserving the 100R differential characteristic impedance of the pair.
4
4-Level Strap Device Configuration
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VDDIO
Rhi
V
0.1 F
SGMII_xxP Pin
Rlo
Rpull
VDDIO
Rhi
V
SGMII_xxN Pin
0.1 F
Rlo
Figure 3. SGMII 4-Level Strap Diagram
3
Analysis of a 4-Level Strap Pin Voltage
Analysis of a strap pin’s voltage divider will take into account the first four effects described in section 2.2:
resistor tolerance, external pull resistors, leakage current, and TCR.
It must be ensured that the resistive divider provides a voltage greater than the Vmin value published in the
data sheet, this is referred to as Vmin analysis in this application note. Conversely, the voltage created by
the divider must not exceed the Vmax voltage, this is referred to as Vmax analysis. Both cases must be
checked, and satisfied, for the divider to be considered a proper configuration for reliable operation.
The ideal case is ignored in the analysis because the ideal resistor values have already been calculated
for all devices and provided in the data sheet.
3.1
Example with Internal Pull-Down Resistor
The below figure shows the equivalent circuit when considering a strap pin that has an internal pull-down
resistor and a MAC connected with an internal pull-down resistor. In the case that the internal resistors are
of a different pull type, the analysis should be adjusted accordingly.
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Analysis of a 4-Level Strap Pin Voltage
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PHY
MAC
VDDIO
Ileak_phy
Ileak_ mac
Rhi
Rint_phy
Rlo
Rint_mac
Figure 4. 4-Level Strap Voltage Analysis Model (Internal Pull-Down)
3.1.1
Vmax Analysis
Vm ax ´ VDDIO ³
Req+
Req+ + Rhi-
´ VDDIO + (I leak _ ma c + + I leak _ phy + ) ´ Rstrap +
where:
(1)
Rstrap + = Req+ || RhiR eq + = R int_ phy + || R lo + || R int_ ma c + =
R hi- = R hi ´ (1 - R hi _ tol R lo + = R lo ´ (1 + R lo _ tol +
R hi _ TCR
106
R lo _ TCR
106
R int_ phy + ´ R lo + ´ R int_ ma c +
(R int_ phy + ´ R lo + )+ (R lo + ´ R int_ ma c + )+ (R int_ ma c + ´ R int_ phy + )
´ éëSystem _ max_ temp - Nominal _ R _ temp ùû )
´ éëSystem _ max_ temp - Nominal _ R _ temp ùû )
R int_ phy + = R int_ phy ´ (1 + R int_ phy _ tol )
R int_ mac + = R int_ mac ´ (1 + R int_ mac _ tol )
6
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3.1.2
Vmin Analysis
Vmin ´ VDDIO £
ReqReq- + Rhi+
´ VDDIO + (I leak _ ma c - + I leak _ phy - ) ´ Rstrap -
where:
(2)
Rstrap - = Req- || Rhi+
R eq + = R int_ phy + || R lo + || R int_ ma c + =
R hi+ = R hi ´ (1 + R hi _ tol +
R lo - = R lo ´ (1 - R lo _ tol -
R hi _ TCR
106
R lo _ TCR
106
R int_ phy + ´ R lo + ´ R int_ ma c +
(R int_ phy + ´ R lo + )+ (R lo + ´ R int_ ma c + )+ (R int_ ma c + ´ R int_ phy + )
´ ëéSystem _ max_ temp - Nominal _ R _ temp ùû )
´ éëSystem _ max_ temp - Nominal _ R _ temp ûù )
R int_ phy - = R int_ phy ´ (1 - R int_ phy _ tol )
R int_ mac - = R int_ mac ´ (1 - R int_ mac _ tol )
3.1.3
Example Analysis
As an example, using the equations above and Table 2, calculate Vmax and Vmin of the resistive divider for
an internal pull-down strap pin in mode three.
Given:
System_max_temp = 85 ºC
Nominal_R_temp = 25 ºC
TCR = 100 ppm/ºC
Rhi = 5.76 kΩ
Rhi_tol = ±1%
Rlo = 2.49 kΩ
Rlo_tol = ±1%
Rint_phy = 9 kΩ
Rint_phy_tol = ±25%
Rint_mac = 1 MΩ (open)
Rint_mac_tol = ±0%
Ileak_mac = ±10 µA
Ileak_phy = 0 µA / +5 µA
VDDIO = 3.3 V
For the hypothetical device from section 2, mode three has the following voltage requirements:
VDDIO × Vmin = 0.743 V and VDDIO × Vmax = 0.937 V.
Solving for the right side of Equation 1, the result is 0.904 V. Solving for the right side of Equation 2, the
result is
0.762 V.
In the example configuration, we satisfy the condition for Vmax : 0.937 V ≥ 0.904 V. Vmin is also satisfied:
0.743 V ≤ 0.762 V
The chosen values for Rhi and Rlo in the example meet both conditions for mode three and are a valid
solution.
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Analysis of a 4-Level Strap Pin Voltage
3.2
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Example with Internal Pull-Up Resistor
The below figure shows the equivalent circuit when considering a strap pin that has an internal pull-up
resistor and a MAC connected with an internal pull-down resistor.
PHY
VDDIO
MAC
VDDIO
Ileak_ mac
Rint_phy
Rhi
Ileak_phy
Rlo
Rint_mac
Figure 5. 4-Level Strap Voltage Analysis Model (Internal Pull-Up)
Vmax Analysis
Vm ax ´ VDDIO ³
Rlo _ eq+
Rlo _ eq+ + Rhi _ eq-
´ VDDIO + (I leak _ ma c + + I leak _ phy + ) ´ Rstrap +
where:
(3)
Rstrap + = Rlo _ eq+ || Rhi _ eqR lo + ´ R int_ ma c +
Rlo _ eq+ = R lo + || R int_ ma c + =
Rhi - ´ Rint_ phy -
Rhi _ eq - = Rhi - || Rint_ phy - =
R hi- = R hi ´ (1 - R hi _ tol R lo + = R lo ´ (1 + R lo _ tol +
R lo + + R int_ ma c +
Rhi - + Rint_ phy -
R hi _ TCR
106
R lo _ TCR
106
´ éëSystem _ max_ temp - Nominal _ R _ temp ùû )
´ éëSystem _ max_ temp - Nominal _ R _ temp ùû )
R int_ phy - = R int_ phy ´ (1 - R int_ phy _ tol )
R int_ mac + = R int_ mac ´ (1 + R int_ mac _ tol )
8
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3.2.1
Vmin Analysis
Vmin ´ VDDIO £
Rlo _ eqRlo _ eq- + Rhi _ eq+
´ VDDIO + (I leak _ ma c - + I leak _ phy - ) ´ Rstrap -
where:
(4)
Rstrap - = Rlo _ eq- || Rhi _ eq+
R lo - ´ R int_ ma c -
Rlo _ eq- = R lo - || R int_ ma c - =
R lo - + R int_ ma c Rhi + ´ Rint_ phy +
Rhi _ eq + = Rhi + || Rint_ phy + =
R hi+ = R hi ´ (1 + R hi _ tol +
R lo - = R lo ´ (1 - R lo _ tol -
Rhi + + Rint_ phy +
R hi _ TCR
106
R lo _ TCR
106
´ ëéSystem _ max_ temp - Nominal _ R _ temp ûù )
´ éëSystem _ max_ temp - Nominal _ R _ temp ùû )
R int_ phy + = R int_ phy ´ (1 + R int_ phy _ tol )
R int_ mac - = R int_ mac ´ (1 - R int_ mac _ tol )
3.2.2
Example Analysis
As an example, using the equations above and Table 3 , calculate Vmax and Vmin of a resistive divider for
an internal pull-up strap pin in mode two.
Given:
System_max_temp = 85 ºC
Nominal_R_temp = 25 ºC
TCR = 100 ppm/ºC
Rhi = 13 kΩ
Rhi_tol = ±1%
Rlo = 1.96 kΩ
Rlo_tol = ±1%
Rint_phy = 50 kΩ
Rint_phy_tol = ±25%
Rint_mac = 1 MΩ (open)
Rint_mac_tol = ±0%
Ileak_mac = ±10 µA
Ileak_phy = 0 µA / +5 µA
VDDIO = 3.3 V
For the hypothetical device from section 2, mode two has the following voltage requirements:
VDDIO × Vmin = 0.475 V and VDDIO × Vmax = 0.598 V.
Solving for the right side of Equation 3, the result is 0.595 V. Solving for the right side of Equation 4, the
result is
0.480 V.
In the example configuration, we satisfy the condition for Vmax : 0.598 V ≥ 0.595 V. Vmin is also satisfied:
0.475 V ≤ 0.480 V
The chosen values for Rhi and Rlo in the example meet both conditions for mode two and are a valid
solution.
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2016) to A Revision ........................................................................................................... Page
•
10
Fixed typos ................................................................................................................................. 1
Revision History
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