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Texas Instruments LMH12xx MADI Compatibility Application Note Application notes
User's Guide
SNLA299 – August 2018
LMH12xx MADI Compatibility Application Note
This document gives the MADI (Multichannel Audio Digital Interface) specification requirements and
necessary changes to enable LMH12xx device family to achieve compatibility with this specifications.
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Contents
MADI Specification Requirements .........................................................................................
LMH12xx Device Family ....................................................................................................
Summary ......................................................................................................................
References ...................................................................................................................
2
3
9
9
List of Figures
1
100-m B1694A 6-ns Minimum Eye Opening ............................................................................. 2
2
150-m 5.5CUHD 6-ns Minimum Eye Opening ........................................................................... 2
3
120-m 5.5CFB 6-ns Minimum Eye Opening ............................................................................. 2
4
LMH1297/LMH0397 Block Diagram ....................................................................................... 4
5
LMH1297 Family Application Schematic ................................................................................. 6
6
LMH1297/LMH0397 MADI-Compatible Transmit Waveform........................................................... 7
7
LMH1297/LMH0397 MADI-Compatible Output Eye Diagram.......................................................... 7
8
LMH1218 Block Diagram ................................................................................................... 8
Trademarks
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1
MADI Specification Requirements
1
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MADI Specification Requirements
The MADI Specification standard describes the 125-Mbps NRZI, 4/5-bit coded serial data frame format
and electrical characteristics for a multichannel audio digital interface. This specification governs
requirements for serial digital transmission over coax or fiber-optic lines of 28, 56, or 64 channels
represented at a common sampling frequency of 32 KHz to 96 KHz with a resolution of up to 24-bits per
channel. Only a single-point interface from one transmitter to a receiver is supported. This document
describes electrical parameters and changes necessary to make the LMH12xx device family compatible
with these requirements.
1.1
MADI Transmitter Electrical Requirements
Same as SDI (Serial Digital Interface), the transmission media can either be over a 75-Ω coax cable or a
fiber-optic cable. The following sections list the MADI specification electrical parameter requirements:
1.1.1
Line Driver Impedance
Output impedance should be 75-Ω ±2 Ω.
1.1.2
Mean Output Voltage
MADI data pattern is DC-balanced and thus the average voltage of the terminated output should be 0 V
±0.1 V
1.1.3
Maximum Output Voltage
After a 75-Ω termination, the output voltage should be within 0.3 to 0.6 V.
1.1.4
Terminated Signal Rise and Fall Time
After a 75-Ω termination, the 20/80% rise/fall time should be within 1 nS and 3 nS
1.2
MADI Receiver Electrical Requirements
MADI specification—unlike SDI—calls for minimum eye opening of 6 ns or 0.75 UI. Also, minimum vertical
eye opening is 150 mV. Figure 1 through Figure 3 show a 6-ns horizontal eye opening. a variety of 75-Ω
cables.
NOTE: For these eye diagrams, a MADI cable driver with 1-nS rise/fall time and 600-mV output
swing was used. Thus, the cable lengths noted below are the maximum reach for each cable
model or cable type with a 6-ns minimum vertical eye opening. For other cable types, it is
proportional to the insertion loss at Nyquist frequency.
2
LMH12xx MADI Compatibility Application Note
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Figure 1. 100-m B1694A 6-ns Minimum Eye Opening
Figure 2. 150-m 5.5CUHD 6-ns Minimum Eye Opening
Figure 3. 120-m 5.5CFB 6-ns Minimum Eye Opening
2
LMH12xx Device Family
The LMH12xx device family consists of the following devices: the LMH1297 device family (the LMH1297,
LMH1228, LMH1208, and LMH0397), the LMH1219 device family (the LMH1219 and LMH0324), and the
LMH1218 device family (the LMH1218 and LMH0318). TI expects that the user is familiar with these
devices. For more information on these devices, go to ti.com.
NOTE: At 125-MBps MADI data rate, these devices operate in bypass or raw mode—no retiming or
reclocking.
2.1
LMH12xx Device Family
The LMH1297 and LMH0397 device families are 75-Ω bidirectional IOs, which means the devices can be
configured either as adaptive cable equalizers or as dual cable drivers. When the user configures one of
the devices as an adaptive cable equalizer, there is an additional loop-through port that can be used as an
SDI or MADI cable driver, if needed. The LMH1297 device family can be controlled either through a
register or pin. Through register control, the cable driver output amplitude can be controlled in 5-mV
resolution or per step. Figure 4 shows these configurations.
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SDI_IO±
75-Ÿ 7HUP
RL Network
LMH12xx Device Family
www.ti.com
Cable
EQ
M
U
X
TX_RX
CDR
M
U
X
100-Ÿ
Driver
OUT0±
Cable
Driver
75-Ÿ 7HUP
RL Network
LMH1297/LMH0397
SPI_CTRL
Serial
Interface
SMBus_CTRL
Pin_CTRL
Control Logic
VDD_CDR
Power
Management
VIN
VDD_LDO
LDO
IN0±
Cable
Driver
VSS
SDI_OUT±
PCB
EQ
Figure 4. LMH1297/LMH0397 Block Diagram
2.1.1
LMH1297 MADI Modes of Operation
The LMH1297 device family provides four potential different modes of operation.
2.1.1.1
Dual MADI Cable Driver
The SDI_IO and SDI_OUT can operate in cable driver mode and provide two MADI cable drivers.
2.1.1.2
SDI Bidirectional IO and MADI Cable Driver
In this mode, the SDI_IO is used as a regular SDI bidirectional IO, and the SDI_OUT as a MADI output
(when enabled). The LMH0397 is used for 3G-SDI while the pin/register-compatible LMH1297 is used for
12G SDI_IO.
2.1.1.3
Bidirectional MADI Port and SDI MADI Cable Driver
The SDI_IO is used either as a MADI cable driver or a MADI equalizer, and the SDI_OUT is used as a
MADI driver.
2.1.1.4
Bidrectional MADI Port and SDI Cable Driver
The SDI_IO is used either as a MADI cable driver or a MADI equalizer, and the SDI_OUT is used as a
regular SDI driver.
These four configurations provide flexibility to configure the ports, as needed.
4
LMH12xx MADI Compatibility Application Note
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2.1.2
LMH1297 Device Family Register Changes for MADI Compatibility
After a 75-Ω termination, output voltage should be within 0.3 V to 0.6 V. In default mode, LMH1297 device
family supports SDI amplitude dynamic range. To support MADI output voltage range through SMBus or
SPI interface, the following register settings are necessary:
RAW
FF
05
07
//enable config_io register set
RAW
61
80
80
//sdi_io vod ov enable
RAW
61
32
7F
//sdi_io vod equal to 0x32
RAW
68
80
80
//sdi_out vod override enable
RAW
68
32
7F
//sdi_out vod equal to 0x32
RAW
60
20
20
//force sdi_io slew rate
RAW
60
00
18
//select sd slew rate for sdi_io
RAW
68
20
20
//force sdi_out slew rate
RAW
68
00
18
//select sd slew rate for sdi_out
RAW
FF
04
07
//retimer register set enable
RAW
3F
08
08
//override out_ctrl pin
RAW
09
00
20
//disable independent control
RAW
1C
0C
0C
//raw sdi_out and out0
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LMH12xx Device Family
2.1.3
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LMH1297 Device Family Hardware Changes for MADI Compatibility
The LMH1297 device family meets SMPTE SDI slew rates. MADI requires 80%/20% rise/fall time to be
within 1 nS to 3 nS. To meet this requirement, a 10-pF capacitor was added across SDI_OUT± or
SDI_IO± as shown in Figure 5.
BNC
MISO
4.7 µF
1 µF
0.1 µF
HOST_EQ0
SDI_OUT-
OUT0_SEL*
BNC
EQ/CD_SEL**
SDI_OUT+
ENABLE*
LOCK_N
Line-Side Output
Coupled Trace
RX+
RX-
4.7 µF
Host-Side FPGA/
Video Processor
EP
VSS
VSS
VSS
MODE_SEL
Level F (SPI Mode)
LED
LMH1297
OUT_CTRL
200 Ÿ
RSV1
RSV2
RSV3
RSV4
RSV5
SCK
MOSI
SDI_VOD
VIN
100-
VDD_LDO
(1.8 V) OUT0+
OUT0-
SDI_OUT_SEL*
75 Ÿ
75-
0.1 µF
0.1 µF
VIN
SDI_IOSS_N
SPI Interface
75-
VDD_CDR
SDI_IO+
Place 0.1-µF Capacitors
close to each supply pin
No Connect
4.7 µF
Line-Side I/O
1 µF
10 µF
2.5 V
100-
Coupled Trace
TX+
IN0+
TX-
IN04.7 µF
75 Ÿ
VIN
VIN
Optional pullup or pulldown
resistors for 2-Level Strap
Configuration Pins
Level H = 1 NŸ WR 9,1
Level L = 1 NŸ WR 966
VIN
VIN
VIN
VIN
VIN
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
or
20 k
1k
or
20 k
1k
or
20 k
*Internally pulled high
**Internally pulled low
Optional pullup or pulldown
resistors for 4-Level Strap
Configuration Pins
Level H = 1 NŸ WR 9,1
Level F = No Connect
Level R = 20 NŸ WR 966
Level L = 1 NŸ WR 966
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Figure 5. LMH1297 Family Application Schematic
6
LMH12xx MADI Compatibility Application Note
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Figure 6. LMH1297/LMH0397 MADI-Compatible Transmit Waveform
Figure 7. LMH1297/LMH0397 MADI-Compatible Output Eye Diagram
2.2
LMH1218 Device Family Hardware Changes to Support MADI Compatibility
The LMH1218 and LMH0318 devices were first-generation, 12G-SDI cable drivers designed to meet SDI
SMPTE requirements. Thus amplitude was designed to be within 800 mV ±10%. Therefore to meet the
MADI 300-mV to 600-mV output amplitude, a 6-dB passive attenuator block can be used. If the user
wanted to slow down the slew rate in a similar way to the LMH1297 device changes shown in
Section 2.1.3, a 10-pF capacitor can be added across OUT0± (see Figure 8).
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LMH12xx Device Family
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LMH1218
100
OUT0+
4.7 µF
7525.0
BNC
25.0
10 pF
4.7 µF
25.0
25.0
OUT0100
Figure 8. LMH1218 Block Diagram
The following register settings forces raw or CDR bypass for the LMH1218 device:
2.3
RAW
FF
04
07
//enable retimer registers
RAW
09
00
20
//enable override
RAW
1C
0C
0C
//out0 and out1 raw data
LMH1219 Device Family Recommended Register Settings
When operating as a MADI receiver, the LMH1219 and LMH0324 use the same register settings. The
following register settings were used to bypass retimer because the LMH1219 does not lock to 125-Mbps
MADI rate.
8
RAW
FF
05
07
//enable eq core
RAW
31
20
30
//enable override
RAW
33
20
30
//out1 powered up
RAW
FF
04
07
//enable retimer register table
RAW
3F
04
04
//Override reference rate
RAW
2F
00
C0
//Enable CDR lock to SMPTE
rate
LMH12xx MADI Compatibility Application Note
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Summary
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3
RAW
3F
10
10
//Override IN_OUT_SEL pin
RAW
31
00
03
//Select IN0 to OUT0 and OUT1
RAW
3F
08
08
///Override OUT_CTRL
RAW
09
00
20
//Disable independent output
control
RAW
1C
0C
0C
//0x0C = forced raw data 0x08 =
retimed data
RAW
0A
0C
0C
//Reset CDR
RAW
0A
00
0C
//Release CDR Reset
Summary
the LMH1297 device family provides different options to meet MADI requirements. These options are:
• Dual MADI Cable Drivers
• SDI_IO bidirectional SDI plus MADI cable driver
• SDI_IO bidirectional MADI with MADI cable driver
• SDI_IO bidirectional IO MADI with SDI cable driver
To meet these requirements, new register settings and a 10-pF capacitor must be added across SDI
positive and negative pins.
The LMH1219 and LMH0324 require register settings to bypass retimer and thus reducing power
consumption, and the LMH1218 MADI compatibility requires hardware changes and register settings to
bypass retime function.
4
References
For more information on MADI specifications, see the following:
AES10-2008 AES Recommended Practice for Digital Audio Engineering - Serial Multichannel Audio
Digital Interface (MADI), Audio Engineering Society
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