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Texas Instruments TPS6598x PD Power Negotiations Application notes
Application Report
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USB PD Power Negotiations
ABSTRACT
This document describes the Power Delivery (PD) contract negotiation in USB Type-C connections per the
USB-IF PD specification, and its implementation using Texas Instruments TPS65982 USB Type-C and
USB PD controller. USB PD is required in USB Type-C systems for power levels above 15 W (5 V at 3 A)
up to 100 W (20 V at 5 A) according to the specification. This application report describes the digital
communication between the transmitter and receiver ends of a connection support USB PD, the flow of
USB PD power negotiation, as well as the procedure for implementing and debugging USB PD
negotiations using the TPS65982 device and associated software tools.
The TPS65982 device is referred to throughout this application report, but the document also applies to
the TPS65981 and TPS65986 USB Type-C and USB PD controllers.
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5
6
Contents
Introduction ................................................................................................................... 3
USB Power Delivery Specification for Sink and Source Capabilities ................................................. 3
2.1
USB PD Specification for Source Capabilities .................................................................. 4
2.2
USB PD Specification for Sink Capabilities (PDOs) ........................................................... 5
2.3
USB PD Specification for Sink RDO ............................................................................. 6
Tx Sink and Source Capabilities Mode Host-Interface Registers ..................................................... 6
3.1
Tx Source Capabilities Example Settings ....................................................................... 6
3.2
Tx Sink Capabilities Example Settings ........................................................................... 8
Power Negotiation Flow ..................................................................................................... 9
4.1
USB Power Delivery Specification for Power Negotiation Flow .............................................. 9
4.2
PD Trace Analysis of Power Negotiation Flow ................................................................ 11
Rx Sink and Source Capabilities and Active PDO/RDO Host Interface Registers ................................ 12
5.1
Modifying Tx Sink Capabilities to Negotiate Power Based on Actual System Needs .................... 15
5.2
Using Received Data and System Information to Renegotiate Power Contracts ......................... 17
Debugging Common Power Negotiation Issues ....................................................................... 18
6.1
Failure Type 1—PDO1 Accepted With no Mismatch When High-Voltage PDO Available .............. 18
6.2
Failure Type 2—PDO3 Accepted With Capability Mismatch = 1 ........................................... 19
6.3
Failure Type 3—Rx Sink Capabilities Register (0x31) Reads all Zeros (0) ............................... 19
List of Figures
1
Tx Source Capabilities Register of TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl ........................... 7
2
PD Trace of Tx Source Capabilities ....................................................................................... 7
3
Tx Sink Capabilities Register of TPS65982_HD3SS460_UFP_Full_2_8.tpl......................................... 8
4
PD Trace of Sink Capabilities after GSkC Command from Source ................................................... 8
5
Successful Power Negotiation Flow from USB PD Specification .................................................... 10
6
PD Trace of Successful PD Power Negotiation ........................................................................ 11
7
Status Register Read from TPS65982 Acting as Source ............................................................. 12
8
PD Status Register Read from TPS65982 Acting as Sink............................................................ 13
9
Rx Source Capabilities Register Read from TPS65982 Acting as Sink
13
10
Rx Sink Capabilities Register Read from TPS65982 Acting as Source
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11
12
............................................
............................................
Active PDO Register Read from TPS65982 Acting as Sink ..........................................................
Active RDO Register Read from TPS65982 Acting as Source ......................................................
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1
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13
New Set of Five Sink PDOs in Modified Snk_35-50W.pjt Project ................................................... 16
14
New Initial Power Negotiation Between Source and Snk_35-50W.pjt Sink ........................................ 17
15
New Sink Capabilities in Reply to GSkC PD Command from Source
16
New Source PDO3 of TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl Source ............................... 18
17
Final Power Negotiation Between Source and Sink after SSrC Command is Sent ............................... 18
18
Failure Type 1: PDO1 Accepted With no Mismatch When High-Voltage PDO Available ........................ 18
19
Failure Type 2: PDO3 Accepted With Capability Mismatch = 1
19
20
Failure Type 3: Rx Sink Capabilities Register (0x31) Reads all Zeros (0)
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21
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.........................................
Failure Type 3 Solution: Execute GSkC Command from Source ....................................................
17
20
Trademarks
All trademarks are the property of their respective owners.
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Introduction
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1
Introduction
The USB Power Delivery (PD) Specification describes a standard negotiation process for establishing all
PD power contracts. Although the USB Type-C standard allows for providing 5 V at up to 15 W of power,
following the PD protocol is critical for offering or receiving any voltage higher than 5 V. As a result, any
product that requires or delivers power from 5 to 20 V (15 to 100 W of power) must negotiate according to
a specific set of standardized rules.
The TPS65982 device is the USB Type-C and PD port controller with the highest level of integration
available on the market. The TPS65982 device can automatically detect a Type-C port connection,
negotiate a PD contract, and control a set of integrated power switches without the involvement of any
other ICs in the system. Because the firmware (FW) of the TPS65982 device, is configurable, any source,
sink, or dual-role port (DRP) product possible can be created on top of the core-firmware base of the
TPS65982 device, which is compliant to the USB PD protocol. The core FW also prevents problematic
situations with noncompliant products and recovers from PD messaging errors with a robust policy engine.
This chapter includes the following:
• A review of the rules and flow of power negotiation following the USB PD Specification
• Steps to set up and modify examples of PD sink and source capabilities used by the TPS65982 FW
throughout the negotiation process
• Steps to verify the correct power negotiation flow with the following:
– Understanding the power negotiation flow of the USB PD Specification
– Analyzing the results of the PD power negotiation in real-time using decoded PD traces that
capture the communication between two products
• Steps to modify the source and sink capabilities of the TPS65982 device instantly using the host
interface
• Steps to debug common issues and achieve a successful PD power negotiation
2
USB Power Delivery Specification for Sink and Source Capabilities
The USB PD Specification explicitly describes the format of data that will be sent between the source and
sink during a power negotiation. Although knowing the meaning of each bit in the specification is not
always necessary, the PD-related registers (received and transmitted) and PD analyzers of the device
follow the specification exactly and these similarities are integrated in this chapter.
The source must organize the capabilities of the power supply into a list of power-data objects (PDOs).
Table 1. Generic PDO
Bits
Value
Parameter
31-30
00b
Fixed supply
01b
Battery
10b
Variable supply
11b
Reserved
29-0
Specific power capabilities are described by the PDOs in the following tables.
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USB Power Delivery Specification for Sink and Source Capabilities
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Table 2. Fixed-Supply PDO—Source
Bits
Parameter
31-30
Fixed supply
29
Dual-role power
28
USB suspend supported
27
Externally powered
26
USB communications capable
25
Dual-role data
24-22
Reserved – Shall be set to zero
21-20
Peak current
19-10
Voltage in 50-mV units
9-0
Maximum current in 10-mA units
Table 3. Variable-Supply (Nonbattery) PDO—Source
Bits
Parameter
31-30
Variable supply (nonbattery)
29-20
Maximum voltage in 50-mV units
19-10
Minimum voltage in 50-mV units
9-0
Maximum current in 10-mA units
Table 4. Battery-Supply PDO—Source
2.1
Bits
Parameter
31-30
Battery
29-20
Maximum voltage in 50-mV units
19-10
Minimum voltage in 50-mV units
9-0
Maximum allowable power in 250-mW units
USB PD Specification for Source Capabilities
The sink has a similar set of PDOs that contain the same information describing the power input
requirements.
Table 5. Fixed-Supply PDO—Sink
4
Bits
Parameter
31-30
Fixed supply
29
Dual-role power
28
Higher capability
27
Externally powered
26
USB communications capable
25
Dual-role data
24-20
Reserved – Shall be set to zero
19-10
Voltage in 50-mV units
9-0
Operational current in 10-mA units
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USB Power Delivery Specification for Sink and Source Capabilities
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Table 6. Variable-Supply (Nonbattery) PDO—Sink
Bits
Parameter
31-30
Variable supply (non-battery)
29-20
Maximum voltage in 50-mV units
19-10
Minimum voltage in 50-mV units
9-0
Operational current in 10-mA units
Table 7. Battery-Supply PDO—Sink
2.2
Bits
Parameter
31-30
Battery
29-20
Maximum voltage in 50-mV units
19-10
Minimum voltage in 50-mV units
9-0
Operational power in 250-mW units
USB PD Specification for Sink Capabilities (PDOs)
More common is for the PD source to be unaware of the capabilities of the sink. The source advertises the
capabilities and, if a match occurs, the sink returns a request-data object (RDO). Unless a mismatch
occurs or the source must limit the power given to a sink partner, the sink PDOs are never explicitly
transmitted. A sink RDO is more common than a sink PDO. The following tables list the sink-RDO data
structure.
Table 8. Fixed and Variable RDO
Bits
Parameter
31-30
Reserved – Shall be set to zero
29
Object position (000b is reserved and shall not be used)
28
GiveBack flag = 0
27
Capability mismatch
26
USB communications capable
25
No USB suspend
24-20
Reserved – Shall be set to zero
19-10
Operating current in 10-mA units
9-0
Maximum operating current in 10-mA units
Table 9. Battery RDO
Bits
Parameter
31-30
Reserved – Shall be set to zero
29
Object position (000b is Reserved and shall not be used)
28
GiveBack flag = 0
27
Capability mismatch
26
USB communications capable
25
No USB suspend
24-20
Reserved – Shall be set to zero
19-10
Operating power in 250-mW units
9-0
Maximum operating power in 250-mW units
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USB Power Delivery Specification for Sink and Source Capabilities
2.3
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USB PD Specification for Sink RDO
The most important concept in the RDO is as follows: the value in the object-position field indicates which
object is referred to by the RDO in the Source_Capabilities message. A value of 1 always indicates the 5V fixed-supply PDO because it is the first object following the Source_Capabilities message header. A
value of 2 refers to the next PDO and so forth. For more information, see TPS65982D USB Type-C and
USB-PD Controller, Power Switch, and High-Speed Multiplexer (SLVSDB1).
3
Tx Sink and Source Capabilities Mode Host-Interface Registers
The configuration registers for these modes are the transmit (Tx) source capabilities register (address
0x32) and the transmit (Tx) sink capabilities register (address 0x33).
The USB-PD power capabilities are configured using the Application Customization Tool GUI. The
capabilities of the transmitted source are configured using the Tx source capabilities register (0x32). The
capabilities of the transmitted sink are configured using the Tx sink capabilities register (0x33). In some
cases, a design can have both sink and source capabilities. For example, a laptop can source at least 5 V
to charge accessories from the laptop battery but can also charge the battery at up to 20 V. This type of
application is called a dual-role port (DRP) and must sometimes initiate or accept power role swaps. This
chapter only describes the initial PD power negotiation, and therefore the hardware that sources power is
only a source and DFP, and the hardware that sinks power is only a Sink and UFP that operates in dead
battery mode.
If the user is developing a source-only design, such as an AC-DC wall adapter, the Type-C port is set to
use a pullup resistor (Rp) only, and the PD policy is set to reject power role swaps from the far end. For
the source, this chapter only describes how to analyze and modify the Tx source capabilities register
(0x32), and that the TPS65982-EVM receives external power from a traditional 20-V DC power supply.
If the user is developing a sink-only design, such as a bus-powered external hard drive, the Type-C port is
set to use a pulldown resistor (Rd) only, and the PD policy is set to reject power role swaps from the far
end. The TPS6598x FW automatically rejects power role swaps to become the source if the device is
operating in dead battery or no battery mode. For the sink, this chapter only describes how to analyze and
modify the Tx sink capabilities register (0x32), and that the TPS65982-EVM always operates in dead
battery or no battery mode.
3.1
Tx Source Capabilities Example Settings
The TPS6598x Firmware Configuration tool, version 2.8, contains many example projects with different
settings for sink and source capabilities that are transmitted to the far end of the Type-C cable during a
PD negotiation. For this example, select the project template named
TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl which is accessed by clicking the Project menu and
selecting the New Project option from the drop-down menu of the configuration GUI.
The configuration of the transmitted source capabilities is set in the Tx source capabilities register at
address 0x32.
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Tx Sink and Source Capabilities Mode Host-Interface Registers
Figure 1. Tx Source Capabilities Register of TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl
Figure 1 shows the Tx source capabilities register (0x32) for the
TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl example template. This example uses three source
PDOs which are displayed in the Source PDO 1, Source PDO 2, and Source PDO 3 section of the
Register tab . To show exactly 3 PDOs, the Number of Source PDOs field at the top of the Register tab
must be set to decimal 3. Figure 2 shows a captured PD trace which verifies that the data in the Tx source
capabilities register is transmitted to the sink when a valid Type-C connection is made.
Figure 2. PD Trace of Tx Source Capabilities
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Tx Sink and Source Capabilities Mode Host-Interface Registers
3.2
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Tx Sink Capabilities Example Settings
The configuration of the transmitted sink capabilities is set in the Tx sink capabilities register at address
0x33.
Figure 3. Tx Sink Capabilities Register of TPS65982_HD3SS460_UFP_Full_2_8.tpl
Figure 3 shows the Tx sink capabilities register (0x33) for the TPS65982_HD3SS460_UFP_Full_2_8.tpl
example template. This example uses two sink PDOs, which are displayed in the Sink PDO 1 and Sink
PDO 2 section of the Register tab. To show exactly 2 PDOs, the Number of Sink PDOs field at the top of
the Register tab must be set to decimal 2. Figure 4 shows a captured PD trace which verifies the data in
the Tx sink capabilities register is transmitted to the source in response to a Get Sink Capabilities (GSkC)
message.
Figure 4. PD Trace of Sink Capabilities after GSkC Command from Source
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Power Negotiation Flow
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4
Power Negotiation Flow
4.1
USB Power Delivery Specification for Power Negotiation Flow
Figure 5 shows the official flow of a successful USB PD power negotiation from both the source and sink.
The only portion of the power negotiation that can easily be analyzed are the PD messages, or what is
sent from the source PHY to the sink PHY and from the sink PHY to the source PHY. Therefore, the focus
is on steps 3, 7, 12, 16, 21, 25, 30, and 34 in Figure 5.
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Power Negotiation Flow
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Source
:Protocol
:Source Policy Engine
:PHY
Sink
:Protocol
:PHY
:Sink Policy Engine
Cable Capabilities detected
Plug type detected
1: Send Capabilities
2: Capabilities
3: Capabilities + CRC
4: Capabilities
Start CRC Receive Timer
Check MessageID against local copy
Store copy of MessageID
6: GoodCRC
5: Capabilities received
7: GoodCRC + CRC
8: GoodCRC
Check and Increment MessageIDCounter
stop CRCReceiveTimer
9: Capabilities Sent
Evaluate Capabilities
Detect Plug Type
Start SenderResponseTimer
10: Send Request
11: Request
12: Request + CRC
13: Request
Start CRCReceiveTimer
Check MessageID against local copy
Store copy of MessageID
14: Request received
15: GoodCRC
16: GoodCRC + CRC
Stop SenderResponseTimer
17: GoodCRC
Check and Increment MessageIDCounter
Stop CRCReceiveTimer
18: Request sent
Start SenderResponseTimer
Evaluate Request
19: Send Accept
20: Accept
21: Accept + CRC
Start CRCReceiveTimer
22: Accept
Check MessageID against local copy
Store copy of MessageID
24: GoodCRC
25: GoodCRC + CRC
23: Accept received
Start SenderResponseTimer
Start PSTransitionTimer
Reduce current
26: GoodCRC
Check and Increment MessageIDCounter
Stop CRCReceiveTimer
27: Accept sent
Power supply adjusted to negotiated output
Send Ping if required to maintain activity
Prepare for new power
28: Send PS_RDY
29: PS_RDY
30: PS_RDY + CRC
31: PS_RDY
Start CRCReceiveTimer
Check MessageID against local copy
Store copy of MessageID
33: GoodCRC
32: PS_RDY received
34: GoodCRC + CRC
35: GoodCRC
Stop PSTransitionTimer
Start SinkActivityTimer
(If ping required)
Check and Increment MessageIDCounter
Stop CRCReceiveTimer
36: PS_RDY sent
Start SourceActivityTimer
(If ping required)
New Power level
Figure 5. Successful Power Negotiation Flow from USB PD Specification
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Power Negotiation Flow
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The USB PD Specification Revision 2.0, Version 1.2 lists 36 successful steps for a successful power
negotiation. Because the specification assumes the protocol layer, physical layer, and electrical
characteristics are ideal, all steps involving evaluation of available power, timers, and building or
evaluating CRC messages have been removed in this discussion of a successful power negotiation.
After these steps are removed, the resulting list is a total of eight steps required to successfully complete
a USB PD power negotiation which are as follows:
Step 1. Source detects the cable capabilities or plug type if these are not already known. Source
sends a Source_Capabilities message that represents the present capabilities of the power
supply with an appended CRC.
Step 2. Sink generates and sends a GoodCRC message.
Step 3. Sink policy engine evaluates the Source_Capabilities message sent by the source, detects
the plug type if this is required and selects which power supply to use. The sink forms the
data (such as a power-data object) that represents the request into a message and sends the
request message.
Step 4. Source generates and sends a GoodCRC message.
Step 5. Source policy engine evaluates the request message sent by the sink and decides if it can
complete the request. The source forms and sends an accept message with an appended
CRC, and the following occurs:
• The sink enters the SnkStandby period and pulls less than 500 mA.
• The source begins to transition the voltage on the VBUS from VBUS_old to VBUS_new,
which is from 5 to 20 V in this case.
Step 6. Sink generates and sends a GoodCRC message.
Step 7. Source device-policy manager informs the policy engine that the power supply has settled at
the new operating condition and sends a PS_RDY message with an appended CRC.
Step 8. Sink generates and sends a GoodCRC message.
4.2
PD Trace Analysis of Power Negotiation Flow
Referring to the steps in Section 4.1, this section analyzes an actual PD trace of a power negotiation
captured between two TPS65982-EVMs and verifies that it is successful.
The following PD message trace was taken with a Teledyne LeCroy PD analyzer between two TPS65982EVMs, one loaded with a binary created from the source example template,
TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl, and the other loaded with the sink example template,
TPS65982_HD3SS460_UFP_Full_2_8.tpl.
Figure 6. PD Trace of Successful PD Power Negotiation
Figure 6 shows the expected sequence of PD messages for this example and provides specific details on
the eight steps introduced in Section 4.1:
Step 1. In packets 32 to 35, the source makes a few attempts to determine if an active or e-marked
cable is connected before moving on to sending the source capabilities in packet 36 in the
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Rx Sink and Source Capabilities and Active PDO/RDO Host Interface Registers
Step
Step
Step
Step
Step
2.
3.
4.
5.
6.
Step 7.
Step 8.
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form of PDOs.
In packet 37, the sink sends a GoodCRC to confirm the PDOs were received successfully.
In packet 38, the sink sends its power needs to the Source in the form of a RDO.
In packet 39, the source sends a GoodCRC to confirm the RDO was received successfully.
In packet 40, the source accepts the RDO from the sink.
In packet 41, the sink sends a GoodCRC to confirm that the source successfully accepted the
RDO.
In packet 42, the source sends PS_Ready to indicate 20 V is available on VBUS.
In packet 43, the sink sends a GoodCRC to confirm PS_Ready was received successfully.
Rx Sink and Source Capabilities and Active PDO/RDO Host Interface Registers
Section 4.2 explains how a PD analyzer can be used to confirm that a successful PD power negotiation
occurred. This information can also be extracted from the host interface registers of the TPS65982 device.
These registers include the following:
• Status registers
– 0x40, PD status
• Runtime registers:
– 0x30, received (Rx) source capabilities
– 0x31, recieved (Rx) sink capabilities
– 0x34, active PDO
– 0x35, active RDO
Reading the previously listed registers provides an indication of the power negotiation that occurred, even
if a USB PD analyzer is not available in a lab. The TPS6598x Host Interface Utilities Tool provides a lowcost way to analyze, debug, and test to modify the sink and source capabilities of a real system in a
couple different ways. Multiple systems can be tested relatively quickly, and this information can be used
to determine how much power a source or sink actually can provide or consume. This information can
then be used to modify the FW settings in the TPS6598x Configuration Tool to reprogram the SPI flash of
the TPS65982 device with new capabilities. Or this information can be used to modify the sink or source
capabilities instantly over I2C to try a variety of new settings very rapidly and see the results in real-time to
make correct new FW with less SPI writing, prepare to write code for an I2C system controller in a
multiport system, or both.
The PD status register (0x40) was read from the source side and the results are displayed in Figure 7,
showing that this TPS65982-EVM is indeed acting as a source and that the Type-C role indicates that this
port is not acting in sink mode and that an Rd pulldown resistor is activated on the CC1/2 pin. In addition,
the power negotiation was successful on the first attempt (no soft or hard resets occurred, which would
indicate error recovery was attempted).
Figure 7. Status Register Read from TPS65982 Acting as Source
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The PD status register (0x40) was read from the sink side and the results are displayed in Figure 8,
showing that this TPS65982-EVM is indeed acting as a sink and the source advertised 3 A of Type-C
current before the PD power negotiation occurred.
Figure 8. PD Status Register Read from TPS65982 Acting as Sink
The Rx source capabilities register (0x30) was read from the sink side and the results are displayed in
Figure 9, showing that the source advertised three PDOs and matches the default template source
settings in Figure 1 and the capture PD trace in Figure 6.
Figure 9. Rx Source Capabilities Register Read from TPS65982 Acting as Sink
The Rx sink capabilities register (0x31) was read from the source side and the results are displayed in
Figure 10, showing that the source has two sink PDOs which matches the default template sink settings in
Figure 3. This data are not shown in the capture PD trace Figure 6. Section 6 explains why and how to
populate this register with usable data.
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Rx Sink and Source Capabilities and Active PDO/RDO Host Interface Registers
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Figure 10. Rx Sink Capabilities Register Read from TPS65982 Acting as Source
The active PDO register (0x34) was read from the sink side and the results are displayed in Figure 11,
showing that the active PDO matches the default template source settings in Figure 1 and the capture PD
trace in Figure 6.
Figure 11. Active PDO Register Read from TPS65982 Acting as Sink
The active RDO register (0x35) was read from the source side and the results are displayed in Figure 12,
showing that the active requested data object matches the default template sink settings in Figure 3 and
the captured PD trace in Figure 6.
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Rx Sink and Source Capabilities and Active PDO/RDO Host Interface Registers
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Figure 12. Active RDO Register Read from TPS65982 Acting as Source
Now that all of the status and runtime registers have been introduced and verified to match the initial
settings and actual data captured in the PD trace, this information can be used to modify the default
templates to match the power requirements of a real system and add more functionality to complex
systems. In the final system, these same registers will be used to debug simple problems encountered
when testing interoperability of new products being developed with products available in the market.
5.1
Modifying Tx Sink Capabilities to Negotiate Power Based on Actual System Needs
This section explains how to modify the Tx sink Capabilities in the TPS6598x Configuration Tool to match
the needs of a system. Although the templates are a great starting point to verify that the FW is
successfully negotiating USB PD power contracts, the real system being designed will have very specific
power needs.
After determining these exact power needs through lab testing, the FW must be modified to successfully
negotiate as many Source PDOs as possible. Consider an example where the sink system was measured
to need 15 W of power for PDO1 at 5 V to power up the application processor and other critical
components on the board.
At 15 W though, the battery of the system cannot be charged. After additional testing, it is determined that
the system requires at least 35 W to charge the battery and more than 50 W are not necessary.
To ensure the minimum power will be received at standard USB-PD voltage rails (12 V, 15 V, 20 V), fixed
sink PDOs are used to get the exact current required. Assuming the source is a mobile computer or
multiport system sharing a limited amount of power, the operating current is calculated shown in
Equation 1.
Operating Current = (Minimum Power / Voltage Rail)
(1)
Furthermore, the 12-V and 15-V contracts attempt to request a maximum current of up to 3 A, but the 20V sink PDO will only request a maximum current of 2.5 A for exactly 50 W. To capture as many
nonstandard PD voltages and variable source PDOs as possible, a wide-voltage variable sink PDO is
used with a minimum current of 3 A. Figure 13 shows the exact settings used for all five sink PDOs. The
project name of TPS65982_HD3SS460_UFP_Full_2_8.tpl was renamed to Snk_35-50W.pjt in Figure 13
and is no longer a default template.
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Figure 13. New Set of Five Sink PDOs in Modified Snk_35-50W.pjt Project
Figure 14 shows a capture PD trace after loading the new Snk_35-50W.pjt binary FW image on the
TPS65982-EVM and connecting it to the unchanged TPS65982-EVM acting as the source and loaded with
a binary file from the example TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl template project.
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Rx Sink and Source Capabilities and Active PDO/RDO Host Interface Registers
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NOTE: Object 3 (20-V fixed) is still the active RDO but now the operating current and maximum
current fields are 2.5 A.
Figure 14. New Initial Power Negotiation Between Source and Snk_35-50W.pjt Sink
5.2
Using Received Data and System Information to Renegotiate Power Contracts
The USB-PD source may sometimes be mobile computers operating off of battery power or multiport
systems sharing a fixed amount of power trying to allocate resources to PD sinks on a case-by-case
basis.
If the total power available in a USB-PD dock acting as a source is 100 W and 50 W is being used by the
sink on port A, then a standard 60-W contract cannot be offered to port B.
After reading the Rx sink Capabilities Register, it is determined that the sink using FW from the “Snk_3550W.pjt” project only requires 35 W on Port A, so a 60-W contract could be offered to Port B.
In this example, source PDO3 will be reduced to 20 V, 1.75 A and then the TPS65982-EVM acting as the
source will send the Send Source Capabilities (SSrC) message to attempt to renegotiate the PD power
contract at a lower power setting.
NOTE: In Figure 14, the operating current and maximum current fields are now 2.5 A but the new
sink capabilities have been modified and the PD source can determine this information.
Figure 15 shows the sink capabilities processed by the source after issuing a Get sink
Capabilities (GSkC) PD command.
Figure 15. New Sink Capabilities in Reply to GSkC PD Command from Source
Figure 16 shows the source PDO3 being modified on the TPS65982-EVM acting as a source before the
SSrC command is issued to the TPS65982 device to resend the Source Capabilities PD Message.
Modifying the Rx source capabilities register (0x32) and issuing the SSrC command are both performed in
the TPS6598x Utilities Tool GUI.
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Figure 16. New Source PDO3 of TPS65982_HD3SS460_DRP_Source_Full_2_8.tpl Source
Figure 17 shows a PD trace from an analyzer that was recording USB PD traffic before the SSrC
command was issued to the source and captures the renegotiation between the two TPS65982-EVMs.
This PD trace confirms that the sink is still accepting with the 20 V, 1.75-A contract offered by the source
and the power negotiation is successful again.
Figure 17. Final Power Negotiation Between Source and Sink after SSrC Command is Sent
6
Debugging Common Power Negotiation Issues
The previous sections discuss what happens when a power negotiation or renegotiation is successful. The
following sections discuss debugging options for when the first attempt to establish a power contract is
unsuccessful.
6.1
Failure Type 1—PDO1 Accepted With no Mismatch When High-Voltage PDO Available
The most common problem with power contracts is that all eight steps that make up a successful power
negotiation (see Section 4.1) are usually completed successfully, with the sequence ending in a
PS_Ready message sent from the source. Sometimes the accepted PDO is Object 1, meaning that the
source provides only 5 V. If the sink has higher voltage capabilities (9, 12, 15, or 20 V) then none of the
source PDOs 2 through X matched any of the sink PDOs 2 through Y. Figure 18 shows this type of failure
with the source capabilities modified on the TPS65982-EVM acting as a source to recreate the issue.
Figure 18. Failure Type 1: PDO1 Accepted With no Mismatch When High-Voltage PDO Available
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If the sink capabilities have been well characterized, then the source should be put on a list of PD power
supplies that are not compatible with the sink system. If the sink capabilities are not known yet, then the
TPS6598x Host Interface Utilities Tool can be used to modify the Tx sink capabilities register (0x33) and
lower the current at one of the fixed-source voltages to accept a high-voltage PDO. The system must be
retested to ensure it can operate correctly with lower input power, even in Dead Battery Mode.
If the problem continues, the high-voltage source PDO is most likely a variable type and the voltage
window is very large. Modifying variable- and battery-type sink PDOs is not strictly defined by the USB
specification and debugging this type of problem is outside the scope of this document.
6.2
Failure Type 2—PDO3 Accepted With Capability Mismatch = 1
Another similar problem that can occur is a capability mismatch. Sometimes a PDO is accepted even
though no matches occurred. In other words, source PDOs 1 through X did not match any of the sink
PDOs 1 through Y. If this issue occurs, the capabilities mismatch bit in the RDO is set to 1. Figure 19
shows this type of failure with the source capabilities modified on the TPS65982-EVM acting as a source
to recreate the issue.
Figure 19. Failure Type 2: PDO3 Accepted With Capability Mismatch = 1
The solution to this failure is the same as the solution to failure 1 (see Section 6.1), but the fact that this
failure occurred may not be as obvious because Object 2-X could be requested to get the most power
(Object 1 not requested) and VBUS may be higher than 5 V.
6.3
Failure Type 3—Rx Sink Capabilities Register (0x31) Reads all Zeros (0)
The final failure discussed in this section is when the Rx sink capabilities register (0x31) has no data and
reads all 0. In previous sections, the Rx sink capabilities register of the source is assumed to always
contain the same data as the Tx sink capabilities register of the sink, but this is not entirely true. The data
in any received (Rx) register can only display information sent through PD communication. As can be
seen in all of the successful power-negotiation PD traces, the sink is never required to send capabilities
but is only required to send a request.
Figure 20 shows this failure. The solution is simple and has been explained previously in Section 6.1.
Figure 20. Failure Type 3: Rx Sink Capabilities Register (0x31) Reads all Zeros (0)
Figure 21 shows how to send a Get Sink Capabilities PD message from the source using the TPS6598x
Host Interface Utilities Tool GUI to populate register 0x31 of the source with real data from the sink.
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Figure 21. Failure Type 3 Solution: Execute GSkC Command from Source
Figure 21 shows the exact same data as Figure 10, but the data shown in Figure 10 is not populated until
a GSkC command is executed.
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