Texas Instruments | SN65DSI86 and SN65DSI96 Hardware Implementation | Application notes | Texas Instruments SN65DSI86 and SN65DSI96 Hardware Implementation Application notes

Texas Instruments SN65DSI86 and SN65DSI96 Hardware Implementation Application notes
Application Report
SLLA343 – October 2013
SN65DSI86 and SN65DSI96 Hardware Implementation
Guide
Michael Campbell
Consumer Computer Interface
ABSTRACT
This document includes guidelines and recommendations for implementing SN65DSI86 or
SN65DSI96 in system hardware. These recommendations are only guidelines and it is the
designer’s responsibility to consider all system characteristics and requirements. Refer to
the datasheet (SLLSEH2) for technical details such as device operation, terminal
description, and so forth.
1
2
3
Contents
Overview ....................................................................................................................................... 2
1.1 What are SN65DSI86 and SN65DSI96? ................................................................................. 2
HW Implementation Guidelines ................................................................................................... 2
2.1 Power Supplies (VCC, VCCA, VCCIO, VPLL) .................................................................................. 2
2.1.1 VCC Supply .................................................................................................................. 2
2.1.2 VCCA supply ................................................................................................................. 2
2.1.3 VPLL Supply ................................................................................................................. 2
2.1.4 VCCIO Supply ................................................................................................................ 3
2.2 MIPI DSI Interface .................................................................................................................. 3
2.2.1 DSI Critical Route Rules.............................................................................................. 3
2.2.2 Unused DSI Channels or lanes ................................................................................... 4
2.3 DisplayPort Interface .............................................................................................................. 4
2.3.1 Main Link..................................................................................................................... 4
2.3.2 AUX ............................................................................................................................ 7
2.3.3 HPD ............................................................................................................................ 8
2.4 REFCLK ................................................................................................................................. 9
2.5 RESET Implementation .......................................................................................................... 9
2.6 I2C
.................................................................................................................................... 9
2.7 ADDR .................................................................................................................................... 9
2.8 GPIOS .................................................................................................................................... 9
2.9 TEST Pins .............................................................................................................................. 9
2.10 Land Pattern Configuration ................................................................................................... 10
References .................................................................................................................................. 10
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figures
DSI Channel Routing Example........................................................................................ 4
Default Configuration Lane Assignment Example ........................................................ 5
Custom Lane Assignment Example ............................................................................... 5
DisplayPort Main Link Routing Example........................................................................ 7
AUX Implementation ........................................................................................................ 8
1
SLLA343
Figure 6.
Figure 7.
HPD Implementation ........................................................................................................ 8
Recommended Land Pattern Configurations .............................................................. 10
Table 1.
Tables
SN65DSIX6 Features Summary ...................................................................................... 2
1
Overview
1.1
What are SN65DSI86 and SN65DSI96?
The SN65DSI86 and SN65DSI96 devices will be referred to as SN65DSIX6 in this document.
SN65DSIX6 is an MIPI DSI-to-eDP bridge device that supports video modes in forward direction.
The SN65DSIX6 is primarily targeted for portable applications such as tablets and smart phones
that utilize the MIPI DSI video format. The SN65DSIX6 can be used between a GPU with DSI
output and a video panel with DisplayPort inputs.
Both devices share the same pin out and package.
Table 1 presents a summary of the feature sets on these devices
Table 1.
SN65DSIX6 Features Summary
Part Name
Description
SN65DSI86
SN65DSI96
Dual Channel DSI to 4 eDP lanes
Dual Channel DSI to 4 eDP lane with Assertive Display Technology
Note: Each DSI channel has 4 DSI data lanes and 1 CLK lane.
2
HW Implementation Guidelines
2.1
Power Supplies (VCC, VCCA, VCCIO, VPLL)
2.1.1 VCC Supply
The 1.2-V VCC supply feeds the digital core for the SN65DSIX6. These supply pins should be
connected to a power plane and each pin should have a 100-nF decoupling capacitor.
2.1.2 VCCA supply
The 1.2-V VCCA supply feeds the analog circuits for the DSI and DisplayPort interface. These
supply pins should be connected to a power plane and each pin should have a 100-nF or 10-nF
decoupling capacitor.
2.1.3 VPLL Supply
The 1.8-V VPLL supply provides power to the DisplayPort PLL. For optimal performance, it is
critical this pin is well filtered. A 1-µF, 100-nF, and 10-nF decoupling capacitor is recommended.
2
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
SLLA343
2.1.4 VCCIO Supply
The 1.8-V VCCIO supply provides power to the LVCOM 1.8-V I/Os (GPIO[4:1], ADDR, and so
forth). Using a 100-nF capacitor on each VCCIO pin is recommended.
2.2
MIPI DSI Interface
2.2.1 DSI Critical Route Rules
1. DA*P/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance
(±20%) or 50-Ω single-ended impedance (±15%).
2. Keep away from other high-speed signals.
3. Keep lengths to within 5 mils of each other.
4. Length matching should be near the location of mismatch. Refer to Figure 4 for an
example.
5. Each pair should be separated at least by 3 times the signal trace width.
6. The use of bends in differential traces should be kept to a minimum. When bends are
used, the number of left and right bends should be as equal as possible and the angle of
the bend should be ≥ 135º. This will minimize any length mismatch caused by the bends
and therefore minimize the impact bends have on EMI.
7. Route all differential pairs on the same layer.
8. The number of VIAS should be kept to a minimum. Keeping the VIAS count to 2 or less
is recommended.
9. Keep traces on layers adjacent to the ground plane.
10. Do not route differential pairs over any plane split.
11. Adding test points will cause impedance discontinuity, therefore, negatively impacting
signal performance. If test points are used, they should be placed in series and
symmetrically. They must not be placed in a manner that causes a stub on the
differential pair.
12. The maximum trace length over FR4 between SN65DSIX6 and the GPU is 25 – 30 cm.
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
3
SLLA343
Figure 1.
DSI Channel Routing Example
2.2.2 Unused DSI Channels or lanes
Leave unused DSI input terminals (DA*N/P, DB*N/P) unconnected or driven to LP11 state.
2.3
DisplayPort Interface
The SN65DSIX6 is compliant to DisplayPort 1.2a and eDP 1.4 and supports up to four lanes at
data rates up to 5.4 Gbps (HBR2).
2.3.1 Main Link
2.3.1.1
AC Coupling Capacitors
All physical DisplayPort pins require AC coupling capacitors between the SN65DSIX6 and the
DisplayPort Sink as depicted in Figure 2. It is recommended these capacitors are placed close
to the eDP receptacle. The AC coupling capacitor must be in the range of 75 nF to 200 nF. A
value of 100 nF is recommended. A package size of 0201 is recommended but a 0402 is
acceptable.
2.3.1.2
Lane Assignment Feature
The SN65DSIX6 has four physical DisplayPort lanes and each physical lane can be assigned to
one specific logical lane. By default, physical lanes 0 thru 3 are mapped to logical lanes 0 thru
3, as depicted in Figure 2. When routing between the SN65DSIX6 and a non-standard eDP
receptacle, this Lane Assign feature, along with polarity inversion, can greatly ease routing. By
reprogramming the lane assignments, trace crossing on PCB can be eliminated and layer count
may be reduced. Figure 3 shows an example of the logical lane to physical lane assignments to
interface to a non-standard eDP receptacle.
4
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
SLLA343
Standard
eDP
Receptacle
SN65DSIX6
LOGICAL
PHYSICAL
ML3N
ML3N
ML3P
ML3P
ML2N
ML2N
ML2P
ML2P
ML1N
ML1N
ML1P
ML1P
ML0N
ML0N
ML0P
ML0P
LN3_ASSIGN
LN2_ASSIGN
LN1_ASSIGN
LN0_ASSIGN
Figure 2.
Default Configuration Lane Assignment Example
Non-Standard
eDP
Receptacle
SN65DSIX6
LOGICAL
PHYSICAL
ML3N
ML0N
ML3P
ML0P
ML2N
ML1N
ML2P
ML1P
ML1N
ML2N
ML1P
ML2P
ML0N
ML3N
ML0P
ML3P
LN0_ASSIGN
LN1_ASSIGN
LN2_ASSIGN
LN3_ASSIGN
Figure 3.
Custom Lane Assignment Example
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
5
SLLA343
2.3.1.3
Polarity Inversion Feature
The SN65DSIX6 provides the ability to swap the polarity of any DisplayPort lane. By default, the
polarity of each lane is not inverted but by setting the appropriate MLx_POLR bit, the polarity of
that specific physical lane will be inverted. This feature is very useful in eliminating crossing
within a pair when routing traces across a PCB.
2.3.1.4
Main Link Critical Routes Rules
1.
ML*P/N pairs should be routed with controlled 100-Ω differential impedance (±20%) or
50-Ω single-ended impedance (±15%).
2.
Keep away from other high-speed signals.
3.
Intra-pair skew should be kept as small as possible. It is recommended to keep lengths
to within 5 mils of each other.
4.
Length matching should be near the location of mismatch. Refer to Figure 4 for an
example.
5.
Each pair should be separated by at least 3 times the signal trace width.
6.
The use of bends in differential traces should be kept to a minimum. When bends are
used, the number of left and right bends should be as equal as possible and the angle of
the bend should be ≥ 135º. This will minimize any length mismatch caused by the bends,
therefore, minimizing the impact bends have on EMI.
7.
Route all differential pairs on the same layer.
8.
The number of VIAS should be kept to a minimum. Keeping the VIAS count to 2 or less
is recommended.
9.
Keep traces on layers adjacent to the ground plane.
10. Do not route differential pairs over any plane split.
11. Adding test points will cause impedance discontinuity, therefore, negatively impacting
signal performance. If test points are used, they should be placed in series and
symmetrically. They must not be placed in a manner that causes a stub on the
differential pair.
12. The maximum trace length over FR4 between SN65DSIX6 and the eDP receptacle is 4
inches for data rates ≤ HBR (2.7 Gbps) and 2 inches for HBR2 (5.4 Gbps).
6
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
SLLA343
Figure 4.
2.3.1.5
DisplayPort Main Link Routing Example
Unused DisplayPort Lanes
Leave unused DisplayPort terminals unconnected.
2.3.2 AUX
The SN65DSIX6 supports a Manchester-II encoded 1-Mbps AUX interface. FAUX (Fast AUX )
is not supported.
2.3.2.1
AUX Implementation
AUXP/N pins require AC coupling capacitors between the SN65DSIX6 and the DisplayPort sink.
Place these capacitors close to the eDP receptacle. The AC-coupling capacitor must be in the
range of 75 nF to 200 nF. A value of 100 nF is recommended. A package size of 0201 is
recommended but a 0402 is acceptable.
Source detection pull-up and pull-down resistors are optional. Some DisplayPort sinks will
require source detection resistors while others will not.
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
7
SLLA343
DP_PWR
SN65DSIX6
100 kΩ
Optional
100 nF
AUXN
AUXN
100 nF
AUXP
Optional
Figure 5.
2.3.2.2
eDP
Receptacle
AUXP
100 kΩ
AUX Implementation
AUX Routing Rules
AUXP/N pairs should be routed with controlled 100-Ω differential impedance (±20%) or 50-Ω
single-ended impedance (±15%).
2.3.3 HPD
The HPD I/O cell has an internal 60-kΩ pull-down resistor. The HPD pin requires a series
external 51-kΩ 1% resistor as depicted in Figure 6. According to the VESA Embedded
DisplayPort standard, use of HPD is optional for a DisplayPort transmitter. If the system
designer chooses to not use HPD, then software must disable HPD by setting the
HPD_DISABLE bit.
51K 1%
HPD_i
HPD
60K
15%
Figure 6.
8
DNI
HPD Implementation
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
SLLA343
2.4
REFCLK
The SN65DSIX6 supports the following frequencies: 12 MHz, 19.2 Mhz, 26 MHz, 27 MHz, and
38.4 MHz. The REFCLK frequency must be specified by either configuration of GPIO[3:1] pins
at rising edge of EN or through setting the appropriate value of the REFCLK_FREQ field in the
configuration registers.
A series resistor is recommended near the RECLK source to reduce EMI. If possible, bury the
REFCLK trace in the inner layer or minimize the trace length from the REFCLK terminal to CLK
source by placing the source near the SN65DSIX6 REFCLK terminal.
When DSI_CLKA is used instead of REFCLK for the DisplayPort PLL, then the REFCLK pin
must be tied or pulled down to GND.
2.5
RESET Implementation
The SN65DSIX6 is reset by controlling the EN terminal. The reset implementation defined in the
datasheet should be followed for correct operation of the device after the reset.
2.6
I2C
The I2C interface (SDA and SCL pins) requires external pull-up resistors to VCCIO for proper
operation. If the I2C interface is not used, then it should be pulled-down or tied directly to GND.
2.7
ADDR
The ADDR determines the least significant bit of the I2C ADDR for the SN65DSIX6. This bit
should be pulled high or low through a resistor depending on the I2C address the system
chooses to use for the SN65DSIX6. When this pin is pulled low, the device address is 0x2C.
When this pin is pulled high, the device address is 0x2D.
IMPORTANT:
When it is pulled high, ADDR must be tied to the device VCCIO such that this pin
does not remain high when the device power is removed.
2.8
GPIOS
The GPIO[4:1] are used for various purposes. Please refer to the SN65DSIX6 datasheet for
functional details of each GPIO. The GPIO[4:1] do not have any internal pull-up or pull-down
resistors. When a GPIO is pulled-up, it should be pulled-up to the VCCIO supply. Unused
GPIOs should be pulled-down or tied to GND.
2.9
TEST Pins
TEST1, TEST2 and TEST3 are reserved pins and are intended for Texas Instruments use only.
TEST1 should be left unconnected or tied to GND. TEST2 should be left unconnected or tied to
GND. TEST2 must be pulled up to VCCIO when performing DisplayPort compliance testing.
TEST3 should be left unconnected or tied to GND through a 0.1-µF capacitor.
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
9
SLLA343
2.10 Land Pattern Configuration
The SN65DSIX6 package has a ball pitch of 0.5 mm. Follow the solder-mask defined land and
non-solder mask defined land for a 0.5-mm ball pitch detailed in Figure 7.
Figure 7.
3
Recommended Land Pattern Configurations
References
SN65DSIX6 Datasheet (SLLSEH2).
10
SN65DSI86 and SN65DSI96 Hardware Implementation Guide
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising