Texas Instruments | Understanding the Pwr Sup Require of PCI Bus Stnd-How to Protect the Dig Compnts (Rev. B) | Application notes | Texas Instruments Understanding the Pwr Sup Require of PCI Bus Stnd-How to Protect the Dig Compnts (Rev. B) Application notes

Texas Instruments Understanding the Pwr Sup Require of PCI Bus Stnd-How to Protect the Dig Compnts (Rev. B) Application notes
Application Report
SNVA002B – July 1997 – Revised May 2013
AN-1077 Understanding the Power Supply Requirements
of PCI Bus Standard-How to Protect the Digital
Components
.....................................................................................................................................................
ABSTRACT
This application report provides an analog design guide to the PCI system designers.
1
2
Contents
Introduction .................................................................................................................. 2
Analog Requirements for PCI Specification 2.1 ......................................................................... 2
List of Figures
1
Possible Current Diode Path From 5 V to 3.3 V via 3.3 V Clamp Diode ............................................ 3
2
Possible Current Diode Path From 3.3 V to 5 V When 5 V is Crowbarred.......................................... 4
3
Typical Application Circuit Using the LMC6953 on a Motherboard
4
..................................................
Using LMC6953 to Monitor Three Different Voltages ..................................................................
5
5
List of Tables
1
Analog Requirements Found in PCI Specification Revision 2.1 ...................................................... 2
2
Safe and Unsafe Conditions in Mixed Voltage PCI Systems
.........................................................
4
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SNVA002B – July 1997 – Revised May 2013
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AN-1077 Understanding the Power Supply Requirements of PCI Bus
Standard-How to Protect the Digital Components
Copyright © 1997–2013, Texas Instruments Incorporated
1
Introduction
1
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Introduction
Until recently, PCI systems primarily used 5 V components. But as submicron process technology
advances, the trend is to support mixed voltage components in the newer PCI systems. As a result, power
supply requirements on mixed voltage PCI systems are getting increasing attention from the design
community. Understanding and designing to these requirements will prevent any power supply variations
from damaging PCI components. These requirements are defined in the analog portion of the PCI
Specification Revision 2.1. They specifically deal with 5 V and 3.3 V mixed-voltage environment.
The analog portion of the PCI 2.1 is scattered in various sections of the document. This article compiles all
the analog requirements in Table 1 and explains the requirements in detail.
Inside a typical computer, there are ±12 V, ±5 V and +3.3 V power supplies. The analog portion of PCI
Specification Revision 2.1 focuses on the +5 V and +3.3 V power supply requirements, because the PCI
local bus and add-in cards may run on either or both voltages. The requirements outline what actions must
be taken when the supply voltages are out of tolerance, as in Section 4.3.2 of PCI 2.1. It also describes
possible behaviors of supply voltages that may destroy PCI components. Real danger exists if these
requirements are ignored. Therefore, building a robust PCI system demands a solution to address the
issues discussed above. This responsibility falls on the PCI system architecture designers and system
design engineers.
2
Analog Requirements for PCI Specification 2.1
Table 1 lists the sections in the PCI Specification Revision 2.1 that cover the analog requirements. Specs I
and II establish the ±5% initial tolerance for 5 V supply. Specs III and IV establish ±9% initial tolerance for
3.3 V supply.
Table 1. Analog Requirements Found in PCI Specification Revision 2.1
Where to Find
Spec
PCI Local Bus Specification Revision 2.1
Page No
I
Maximum for 5 V Supply Voltage 5.25 V *see Spec V
Section 4.2.1.1
Table 4.1
123
II
Minimum for 5 V Supply Voltage 4.75 V *see Spec V
Section 4.2.1.1
Table 4.1
123
III
Maximum for 3.3 V Supply Voltage 3.6 V *see Spec V
Section 4.2.2.1
Table 4.3
128
IV
Minimum for 3.3 V Supply Voltage 3.0 V *see Spec V
Section 4.2.2.1
Table 4.3
128
V
The value of Tfail is the minimum of
500 ns (maximum) from either power rail going out of specifications *(exceeding specified
tolerances by more than 500 mV).
100 ns (maximum) from the 5 V rail failing below 3.3 V rail by more than 500 mV.
Section 4.3.2
Reset Section
139
VI
Anytime RST is asserted, all PCI output signals must be driven to their benign state. In
general, this means they must be asynchronously tri-stated.
Section 2.2.1
RST Section
9
VII
Clamping directly to the 3.3 V rail with a simple diode must never be used in the 5 V
signaling environment. When dual power rails are used, parasitic diode paths can exist
from one supply to another. These diode paths can become significantly forward biased
(conducting) if one of the power rails goes out of spec momentarily. Diode clamps to a
power rails as well as to output pull-up devices, must be able to wthstand short circuit
current until drivers can be tri-stated. Refer to Section 4.3.2 for more information.
Section 4.2.1.2
(refer to the article
for more
information)
126
VIII
There is no specified sequence in which the four power rails (12 V, -12 V, 5 V and 3.3 V)
are activated or deactivated. They may come up and go down in any order. The system
must assert RST both at power up and whenever either the 5 V or 3.3 V rails go out of
spec (per Section 4.3.2). During reset, all PCI signals are driven to a “safe” state, as
described in Section 4.3.2.
Section 4.3.4.2
(refer to the article
for more
information)
142
Spec V establishes an additional ±500 mV on both of the 5 V and 3.3 V supplies for noise margin
consideration. Moreover, Spec V states that if either the 5 V supply or the 3.3 V supply is out of limit, a
RST signal has to be asserted within 500 ns. For example, if 5 V supply is over 5.75 V, RST has to be
asserted within 500 ns. The worst case in Spec V, and a potentially destructive case, is if 5 V supply falls
below 3.3 V supply by more than 300 mV. RST signal has to be asserted within 100 ns when this occurs.
2
AN-1077 Understanding the Power Supply Requirements of PCI Bus
Standard-How to Protect the Digital Components
Copyright © 1997–2013, Texas Instruments Incorporated
SNVA002B – July 1997 – Revised May 2013
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Analog Requirements for PCI Specification 2.1
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Spec VI requires that all PCI output signals be tri-stated once RST is asserted. Tri-stating the PCI devices
will prevent any current flowing from the PCI devices to damage other PCI devices connected to the PCI
bus.
Spec VII describes possible dangers of protection diodes being turned on in mixed voltage environment.
In the event that a protection diode is clamped directly to 3.3 V supply in an 3.3 V I/O device, it will be
forwarded biased when the input of the I/O is coming from 5 V devices. This is shown in Figure 1.
Possibly, a large amount of current will flow from 5 V outputs into the 3.3 V device through the protection
diode, damaging the 3.3 V device. Consequently, Spec VII advises never to clamp a diode directly to 3.3
V supply in 5 V signaling environment.
Specs VII describes another situation where the current flow is from 3.3 V supply to 5 V supply. In the
case when 5 V supply is accidently crowbarred to ground, a current path exists between 3.3 V supply and
5 V supply (now ground), shown in Figure 2. The current flows from the 3.3 V device through the PCI bus
into the 5 V device. Since the 5 V supply is now ground, the input protection diode inside the 5 V device
becomes forward biased, allowing the large current to pass through, possibly damaging the 5 V device.
Spec V and VI protect the 5 V device by asserting RST in 100 ns when the 5 V falls below 3.3 V by more
than 300 mV. Upon RST assertion, all PCI output signals will be tri-stated.
The 5 V and the 3.3 V devices in Figure 2 can be part of a discrete logic, chipset, or ASIC.
Spec VIII points out another threat that mixed voltage supplies have on PCI components. PCI 2.1 does not
guarantee power-up and power-down sequences. As as example of Spec VIII, consider the instance
where 3.3 V supply comes up before 5 V supply. If 5 V rises slowly, staying under 3.3 V, there can be a
current path from 3.3 V supply to 5 V supply through the protection diode inside the 5 V logic. Destruction
can happen. The same principle applies when 3.3 V power supply goes to ground slower than 5 V. Spec
V prevents disasters by asserting RST until supplies are within their limits.
A second example on Spec VIII is the case where 5 V and 3.3 V supplies are independently regulated
from the main power supply. If the 5 V supply momentarily fails, 5 V devices can suffer from electrical
overstress resulting from current flowing from 3.3 V to 5 V through the 5 V device input protection diodes.
Again, Spec V saves the situation by asserting RST when 5 V is out of limit.
A third example of Spec VIII is the case where 3.3 V is generated from 5 V via a linear regulator either in
the main power supply or add-in cards. Some regulators do not provide current limiting on 3.3 V output.
Electrical overstress can damage the pass transistor inside the regulator, allowing the 3.3 V to rise to 5 V.
This would exceed the operating voltage range on the 3.3 V devices. PCI 2.1 provides over-voltage
protection by asserting RST to tri-state outputs in this situation.
Mixed voltage environment presents a new challenge to the PCI system architecture designers. With so
many different power supply sources using various implementations, it is very difficult to ensure that a
power supply complies with PCI 2.1 at all times. Many believe that PCI voltage monitoring is the
responsibility of the power supply section. Today, this is not the case. A PCI system designer has no
control of power supplies and add-in cards. However, he does have control of the motherboard. Therefore,
it is far better to design the protection function that will monitor all types of power supplies and add-in
cards on the motherboard. As a reference, Table 2 shows some safe and unsafe conditions in mixed
voltage PCI systems.
Figure 1. Possible Current Diode Path From 5 V to 3.3 V via 3.3 V Clamp Diode
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Standard-How to Protect the Digital Components
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Analog Requirements for PCI Specification 2.1
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Figure 2. Possible Current Diode Path From 3.3 V to 5 V When 5 V is Crowbarred
Table 2. Safe and Unsafe Conditions in Mixed Voltage PCI Systems
UNSAFE CONDITIONS:
3.3 V supply coming up before 5 V supply.
5 V and 3.3 V power supplies are independently regulated from the main power supply.
3.3 V is generated from 5 V via linear regulator.
Any 3.3 V logic IC that is not 5 V tolerant and does not use buffers that are 5 V tolerant to drive directly on the PCI bus.
SAFE CONDITIONS:
PCI bus is 5 V only or 3.3 V only. This includes PCI add-in cards.
3.3 V logic is 5 V tolerant. This includes any I/O being directly connected to the PCI bus. Mixed 5 V and 3.3 V have compatible
logic levels.
Any 3.3 V logic IC's that are not 5 V tolerant use buffers that are 5 V tolerant to drive directly on the PCI bus. This applies to
motherboard as well as add-in cards.
Texas Instruments recognizes the need for monitoring power supplies in PCI environment to ensure
system integrity and safety. The LMC6953 PCI power supply monitor IC is designed to comply with PCI
2.1, meeting all the analog requirements. It fully addresses all the specs discussed.
There are five comparators inside the LMC6953. Two of them monitor over-voltage and under-voltage on
the 5 V supply; two other monitor the over-voltage and under-voltage on the 3.3 V supply. The fifth one is
a differential comparator monitoring for power failure - 5 V going 300 mV below 3.3 V. The LMC6953 also
has a 5 V/3.3 V logic compatible interrupt pin. During power-up, the LMC6953 holds RST low for 100 ms
(as required by Section 4.3.2, Figure 4.12 of PCI 2.1) after both 5 V and 3.3 V supplies are within their
specified windows. It asserts RST within 490 ns when an over-voltage or an under-voltage is detected. In
case of power failure or momentary fault where the 5 V supply falls below 3.3 V supply by 300 mV
maximum, RST is asserted within 90 ns.
RST also can be instantly asserted by sending a CMOS logic low to the manual interrupt pin. Each time
RST is asserted, it holds low for 100 ms after all fault conditions are recovered. The 100 ms delay is
generated by the 0.01 µF CEXT capacitor, and can be adjusted by changing the value of CEXT.
4
AN-1077 Understanding the Power Supply Requirements of PCI Bus
Standard-How to Protect the Digital Components
Copyright © 1997–2013, Texas Instruments Incorporated
SNVA002B – July 1997 – Revised May 2013
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Analog Requirements for PCI Specification 2.1
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The LMC6953 is designed for desktop PC motherboards or add-in cards. Figure 3 shows the LMC6953
monitoring the 5 V and 3.3 V power supplies from the power supplies and asserting RST to the system
controllers in case of a fault condition. RST from the LMC6953 has an open-drain output and can be
ORed to different system controllers. If monitoring a third voltage is desired, for example, 12 V, it can be
achieved by voltage dividing the 12 V down to 2.5 V and connecting it to the manual reset input.
Furthermore, the manual reset input can, at the same time, accept a logic output and the divided-down 12
V, as shown in Figure 4.
Figure 3. Typical Application Circuit Using the LMC6953 on a Motherboard
Figure 4. Using LMC6953 to Monitor Three Different Voltages
Power supplies do not provide any functions defined in PCI 2.1. In fact, power supplies have such diverse
designs that the only sure way to design a PCI-compliant system is to include the power supply monitoring
functions on the motherboard. The LMC6953 is designed for that purpose. It offers an integrated solution
that completely covers the power supply requirements in PCI 2.1. Designing the LMC6953 into a mixed
voltage PCI system will protect the digital components in that system. The LMC6953 asserts RST to the
system controllers when there is a fault condition on the supply voltages. The RST in turn drives all PCI
output signals to their benign state, preventing destructive events due to any of the conditions listed in
Table 1.
There are data sheets, demonstration boards and powerpoint presentations to aid designers and the sales
force to learn more about the LMC6953 as well as gaining further insight into this subject.
SNVA002B – July 1997 – Revised May 2013
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AN-1077 Understanding the Power Supply Requirements of PCI Bus
Standard-How to Protect the Digital Components
Copyright © 1997–2013, Texas Instruments Incorporated
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