Texas Instruments | AN-1499 DP83846 to DP83848C/I/YB PHYTER System Rollover Document (Rev. B) | Application notes | Texas Instruments AN-1499 DP83846 to DP83848C/I/YB PHYTER System Rollover Document (Rev. B) Application notes

Texas Instruments AN-1499 DP83846 to DP83848C/I/YB PHYTER System Rollover Document (Rev. B) Application notes
Application Report
SNOA473B – May 2006 – Revised April 2013
AN-1499 DP83846 to DP83848C/I/YB PHYTER™ System
Rollover Document
.....................................................................................................................................................
ABSTRACT
This is an informational document detailing points to be considered when updating an existing 10/100
Mb/s Ethernet design, using Texas Instruments DP83846 Ethernet Physical Layer (PHY) product, to the
new DP83848C/I/YB PHYTER product. Although the basic functions of the device are similar, differences
include feature set, pin functions, package and pinout, and possibly register operation. The impact to a
design is dependant on which, and how, features of the previous device are used or implemented.
Contents
Required Changes .......................................................................................................... 2
1.1
Package ............................................................................................................. 2
1.2
Pinout ................................................................................................................ 2
1.3
PCB Modification ................................................................................................... 2
2
Potential Changes .......................................................................................................... 4
2.1
TX_ER ............................................................................................................... 5
2.2
MII Interface ........................................................................................................ 5
2.3
PHY Address ....................................................................................................... 5
2.4
Flow Control ........................................................................................................ 5
2.5
Physical Layer ID Register ........................................................................................ 5
2.6
Software Reset ..................................................................................................... 6
3
Informational Changes ..................................................................................................... 6
3.1
Auto-Negotiation and LED Pins .................................................................................. 6
3.2
RMII Interface ...................................................................................................... 7
3.3
SNI Mode ........................................................................................................... 7
3.4
AUTO_MDIX Setting ............................................................................................... 8
3.5
Energy Detect ...................................................................................................... 8
3.6
CLK_to_MAC Output .............................................................................................. 8
3.7
Power Down/Interrupt ............................................................................................. 8
4
References ................................................................................................................... 9
Appendix A
Pinmap ............................................................................................................. 10
Appendix B
Register Differences ............................................................................................. 12
1
List of Figures
5
..................................................................................
DP83848C/I/YB PMD Connections (Termination and Biasing) .......................................................
DP83846 PMD Connections (Termination and Biasing) ...............................................................
RMII Selection on DP83848C/I/YB .......................................................................................
Auto_MDIX Operation in DP83848C/I/YB ...............................................................................
1
Packaging Differences
1
2
3
4
Special Connection in DP83848C/I/YB
3
4
4
7
8
List of Tables
2
.....................................................................................................
Bias Resistor Values .......................................................................................................
2
3
PHYTER is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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Required Changes
3
Termination and Biasing Differences ..................................................................................... 3
4
Register Change for Vendor Model Numbers ........................................................................... 5
5
New Features of DP83848C/I/YB ......................................................................................... 6
6
DP83848C/I/YB Pin for Auto-Negotiation and LED
7
8
9
1
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....................................................................
DP83848C/I/YB Auto-Negotiation Modes ................................................................................
Pinmap ......................................................................................................................
Register Bit Definitions....................................................................................................
6
6
10
12
Required Changes
This section documents the hardware changes required to transition to DP83848C/I/YB. There are three
minor but required circuit changes, which are required for proper operation of the device.
1.1
Package
DP83848C/I/YB uses 48LQFP package. The differences in package between DP83848C/I/YB and
DP83846 are shown in Table 1. For more information on the 48LQFP package, please visit
http://www.ti.com
Table 1. Packaging Differences
DP83848C/I/YB
1.2
DP83846
Package
48-LQFP
80-LQFP
Footprint
7x7mm
12x12mm
Package Drawing
VBH48A
VHG80A
Pinout
DP83846 has 80 pins while DP83848C/I/YB has 48 pins. For the list of pins not applicable in
DP83848C/I/YB and the pinmap from DP83846 to DP83848C/I/YB, see Appendix A.
1.3
PCB Modification
This section describes the DP83846 circuit design modification required to use the DP83848C/I/YB in a
similar PCB.
1.3.1
PFBOUT
Parallel capacitors (10 µF Tantalum capacitor and 0.1 µF) should be placed close to pin 23 (PFBOUT, the
output of the regulator) in DP83848C/I/YB. In DP83848C/I/YB, pin 18 (PFBIN1) and 37 (PFBIN2) should
be externally connected to pin 23 as shown in Figure 1. A small 0.1 µF capacitor should be placed close
to pin 18 and pin 37. DP83846 does not require a similar connection.
2
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Figure 1. Special Connection in DP83848C/I/YB
1.3.2
Bias Resistor
Internal circuitry biasing of the DP83848C/I/YB has changed from previous devices.
Table 2. Bias Resistor Values
Bias Resistor Value
1.3.3
DP83848C/I/YB
DP83846
4.87K Ohm
9.31K Ohm
Termination and PMD Biasing
Termination of the PMD receive pair (TPRD±) on the previous physical layer devices consisted of a pair of
54.9 Ω, AC biased to GND. This value, when seen in parallel with the internal receiver circuitry, provided
an equivalent of 100 Ω impedance. In DP83848C/I/YB, the internal receiver circuitry has changed and now
requires a pair of 49.9 Ω resistors, biased to VDD of the device.
This matching of the termination resistors and common biasing between the receiver and transmitter of
the DP83848C/I/YB allows the addition of the Auto-MDIX feature to the device.
Table 3. Termination and Biasing Differences
DP83848C/I/YB
DP83846
TX Termination
49.9 Ω
49.9 Ω
TX Bias
3.3 V
3.3 V
RX Termination
49.9 Ω
54.9 Ω
RX Bias
3.3 V
AC to GND
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Potential Changes
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For a graphic explanation of this, see Figure 2 and Figure 3.
Figure 2. DP83848C/I/YB PMD Connections (Termination and Biasing)
Figure 3. DP83846 PMD Connections (Termination and Biasing)
2
Potential Changes
The following section describes the specific changes that may be implemented in DP83848C/I/YB
depending on the application.
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2.1
TX_ER
Older designs using the DP83846 may use the TX_ER pin. This signal allows the system MAC to force
DP83846 to deliberately corrupt the transmitted packet by inserting bad symbol codes. A similar function
can be accomplished by having the MAC signal the PHY to stop transmission mid-packet. By stopping
mid-packet, the receiving node will interpret the packet as having a bad CRC. Upper layers can then
decide to receive or reject the packet in question. Since the function on the TX_ER pin can be more easily
attained with the latter method, the TX_ER pin was not included on the DP83848. If the TX_ER pin is
used as an input to any device, the pin should be pulled low to ensure that it does not float.
2.2
MII Interface
The MII interface is used to connect the PHY to the MAC in 10/100 Mbps systems. For a 5 V MII
application, it is recommended to use 33 Ω series resistor between the MAC and DP83848C/I/YB. The MII
interface is a nibble-wide interface that consists of a transmit interface, receive interface and control
signals. The transmit interface is comprised of the following signals:
• Transmit data bus, TXD[0:3] (pins 3,4,5 and 6 in DP83848C/I/YB)
• Transmit enable signal, TX_EN (pin 2 in DP83848C/I/YB)
• Transmit clock, TX_CLK (pin 1 in DP83848C/I/YB) that runs at 2.5 MHz in 10 Mbps mode and 25 MHz
in 100 Mbps mode
The receive interface is comprised of the following signals:
• Receive data bus, RXD[0:3] (pin 43, 44, 45 and 46 in DP83848C/I/YB)
• Receive error signal, RX_ER (pin 41 in DP83848C/I/YB)
• Receive data valid, RX_DV (pin 39 in DP83848C/I/YB)
• Receive clock, RX_CLK (pin 38 in DP83848C/I/YB) for synchronous data transfer that runs at 2.5 MHz
in 10 Mbps mode and 25 MHz in 100 Mbps mode
2.3
PHY Address
In a given system, multiple PHYs can be controlled by a single MII management interface. In order to
support this, each PHY must have a unique address. DP83848C/I/YB facilitates this with PHY address
strap options.
In DP83848C/I/YB, RXD0:3 and COL are used to set the PHY address. While DP83846 requires external
5K Ω pull-ups or pull-downs to set the PHY address, pin COL has a weak internal pullup and RXD0:3
have weak internal pull_downs in DP83848C/I/YB. Hence, the default setting for PHY address in
DP83848C/I/YB is 01h. External 2.2K Ω pull_ups and pull_downs can be added to change the PHY
address from the default.
2.4
Flow Control
In DP83846, pin RX_ER can be strapped low to indicate full duplex flow control support and left floating
otherwise. Since flow control is a function of MAC layer, the MAC must set the bit in the ANAR register in
order to indicate full duplex flow control support in DP83848C/I/YB.
2.5
Physical Layer ID Register
The PHYsical Layer ID (PHYID) register allows system software to determine applicability of device
specific software based on the vendor model number. The vendor model number is represented by bits 9
to 4 in PHYIDR2. The vendor model number in DP83848C/I/YB is 001001b. In DP83846, the vendor
model number is 000010b.
Table 4. Register Change for Vendor Model Numbers
Register
Address
Register
Name
Register Description
Hex
03h
PHYIDR2
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PHY ID 2
Device
DP83848C/I/YB
DP83846
5C90h
5C23h
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Informational Changes
2.6
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Software Reset
A soft reset in the DP83848C/I/YB by setting bit 15 in the BMCR, resets the device and sets all the
registers to their default or strapped settings. This includes Power Down, bit 11 in the BMCR, unless the
PWR_DOWN/INT pin is externally strapped. For previous TI devices, such as the DP83847 and DP83846,
asserting software reset, by setting BMCR, bit 15, the Power Down register setting, BMCR, bit 11, does
not get reset.
3
Informational Changes
This section describes the new features offered in DP83848C/I/YB and the changes required to implement
them.
Table 5. New Features of DP83848C/I/YB
DP83848C/I/YB
DP83846
RMII
Yes
No
SNI
Yes
No
Available in DP83848I and DP83848YB
No
Auto-MDIX
Yes
No
Energy Detect
Yes
No
3
No
CLK-to-MAC Output
Yes
No
Power Down/Interrupt
Yes
No
Yes
Yes
-40_to_85°C
Available in DP83848I
No
-40_to_125°C
Available in DP83848YB
No
264mW
495mW
System_Interfaces
JTAG
LED Outputs
Temperature Range
0_to_70°C
Power Consumption
Active Power (Typ)
3.1
Auto-Negotiation and LED Pins
DP83846 has dedicated AN0, AN1 and AN_EN (pins 25, 26 and 27) for enabling and configuring
auto_negotiation. In addition, LED pins 28 to 33 were used to indicate Speed, Receive, Transmit, Link,
Collision and Duplex status. DP83848C/I/YB has only three pins multiplexed for auto-negotiation function
and LED status indication. Pin 26 has multiple functions, indicating Activity and Collision status, combined
with enabling auto_negotiation. Pin 28 indicates link status and controls the advertised and forced mode
(AN0) of DP83848C/I/YB. Pin 27 indicates speed status and controls the advertised and forced mode
(AN1) of DP83848C/I/YB. DP83848C/I/YB does not have separate pins to indicate transmit and receive
activity status.
Table 6. DP83848C/I/YB Pin for Auto-Negotiation and LED
DP83848C/I/YB Pin Number
Auto-Negotiation function
LED function
26
Auto-Negotiation enable
Activity and collision status
27
Controls the advertised and forced mode (AN1)
Speed status
28
Controls the advertised and forced mode (AN0)
Link status
Table 7. DP83848C/I/YB Auto-Negotiation Modes
6
AN_EN
AN0
AN1
Forced Mode
0
0
0
10 Base-T, Half-Duplex
0
0
1
10 Base-T, Full-Duplex
0
1
0
100 Base-TX, Half-Duplex
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Table 7. DP83848C/I/YB Auto-Negotiation Modes (continued)
3.2
AN_EN
AN0
AN1
0
1
1
Forced Mode
AN_EN
AN0
AN1
1
0
0
10 Base-T, Half/Full-Duplex
1
0
1
100 Base-TX, Half/Full-Duplex
1
1
0
10 Base-T, Half/Full-Duplex
100 Base-TX, Half/Full-Duplex
1
1
1
10 Base-T, Half/Full-Duplex
100 Base-TX, Half/Full-Duplex
100 Base-TX, Full-Duplex
Advertised Mode
RMII Interface
The RMII interface can be used to connect the MAC to PHY in 10/100 Mbps systems using a reduced
number of pins. By utilizing this feature, significant PCB space savings can be realized within the system,
especially one with a large number of physical layer devices.
DP83848C/I/YB uses an external 50 MHz clock (X1) as reference for both transmit and receive in the RMII
mode. This is provided by an external oscillator. RX_DV should be pulled high using a 2.2K Ω resistor to
enable RMII mode.
Figure 4. RMII Selection on DP83848C/I/YB
3.3
SNI Mode
DP83848C/I/YB incorporates a 10Mb Serial Network Interface (SNI) that allows a simple data interface for
10Mb only system. While there is no defined standard for this interface, it is based on the earlier Texas
Instruments 10Mb physical layer devices. The following pins are used in SNI mode:
• TX_CLK
• TX_EN
• TXD_0
• RX_CLK
• RXD_0
• CRS
• COL
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AUTO_MDIX Setting
Auto_MDIX removes cabling complications and simplifies end-customer applications by allowing either a
straight or a cross-over cable to be used without changing the system configuration. Auto_MDIX is
enabled by default in the DP83848C/I/YB. In order to disable Auto_MDIX, pin 41 (RX_ER) should be
pulled to ground using a 2.2K Ω resistor. When enabled, this function utilizes auto_negotiation to
determine the proper configuration for transmission and reception of data and subsequently selects the
appropriate MDI pair for MDI/MDIX operation.
Figure 5. Auto_MDIX Operation in DP83848C/I/YB
3.5
Energy Detect
Energy detect facilitates flexible and automatic power management based on detection of a signal on the
cable. This enables an application to use an absolute minimum amount of power over time. Energy detect
functionality is controlled via the Energy Detect Control Register (EDCR), address 0x1Dh. When energy
detect is enabled and there is no activity on the cable, DP83848C/I/YB remains in a low-power mode while
monitoring the receive pair in the transmission line. Activity on the line causes the DP83848C/I/YB to
return to the normal power mode.
3.6
CLK_to_MAC Output
DP83848C/I/YB offers a clock output that can be routed directly to the MAC and act as the MAC reference
clock, eliminating the need, hence, space and cost of an additional MAC clock source. In the MII mode,
the clock output is 25 MHz and in the RMII mode, it is 50 MHz clock.
3.7
Power Down/Interrupt
DP83848C/I/YB offers a separate pin to indicate an interrupt based on various criteria defined by MISR
and MICR registers. In DP83848C/I/YB, the PWR_DOWN/INT pin (pin 7) can be asserted low to put the
device in a power down state. In the interrupt mode, this pin is an open drain output and is asserted low
when an interrupt condition occurs. It is recommended to use an external pull_up resistor for proper
operation of this function.
8
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References
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4
References
•
•
•
•
DP83848C PHYTER Commercial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer
Transceiver Data Sheet (SNOSAT2)
DP83848I PHYTER Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer
Transceiver Data Sheet (SNLS207)
DP83848YB PHYTER Extreme Temperature Single Port 10/100 Mb/s Ethernet Physical Layer
Transceiver (SNLS208)
DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver (SNLS063)
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Appendix A Pinmap
Table 8. Pinmap
DP83848C/I/YB Signal Name
DP83848C/I/YB Pin No
DP83846 Pin No
Description
31
37
MGMT DATA CLOCK
MGMT DATA I/O
MII Interface Pins
MDC
MDIO
30
36
43,44,45,46
41,40, 39,38
RX_CLK
38
45
MII RX CLOCK
RX_ER/MDIX_EN
41
46
MII RX ERROR
RX_DV/MII_MODE
39
44
MII RX DATA VALID
TXD0:3
3,4,5,6
54,55, 85,59
TX_CLK
1
51
MII TX CLOCK
TX_EN
2
52
MII TX ENABLE
TX_ER
n/a
50
MII TX ERROR
COL/PHYAD0
42
60
MII COL DETECT
CRS/LED_CFG
40
61
MII CARRIER SENSE
RD ±
13,14
10,11
RX DATA
TD ±
16,17
17,16
TX DATA
X1
34
67
XTAL/OSC INPUT
X2
33
66
XTAL OUTPUT
LED_ACT/COL/AN_EN
26
32
COL LED STATUS
LED_ACT/COL/AN_EN
26
33
DUPLEX LED STATUS
LED_LINK/AN_0
28
31
LINK LED STATUS
LED_SPEED/AN_1
27
28
SPEED LED STATUS
LED_ACT/COL/AN_EN
26
n/a
ACT LED STATUS
LED_RX/PHYAD4
n/a
29
RX ACTIVITY LED
LED_TX/PHYAD3
n/a
30
TX ACTIVITY LED
29
62
RESET
RXD0:3/PHYAD1:4
MII RX DATA
MII TX DATA
PMD Interface Pins
Clock Interface Pins
LED Interface Pins
Reset Function Pin
RESET_N
Strap Pins
PHYAD0:4
42,43,44,45,46
33,32,31,30,29
MDIX_EN/RX_ER
41
n/a
PHY ADDRESS
AUTO MDIX ENABLE
MII_MODE/RX_DV
39
n/a
MII MODE SELECT
SNI_MODE
6
n/a
MII MODE SELECT
LED_CFG/CRS
40
61
LED CONFIGURATION
PAUSE_EN/RX_ER
n/a
46
PAUSE ENABLE
BIAS RES CONNECTION
Bias Function Pins
RBIAS
24
3
C1
n/a
n/a
REF BYPASS CAP
AN_0/LED_LINK
28
25
TEST MODE SELECT
AN_1/LED_SPEED
27
26
TEST MODE SELECT
AN_EN/LED_ACT/COL
26
27
TEST MODE SELECT
25
n/a
25 MHz CLOCK OUTPUT
Test Mode Pins
Special Function Pins
25MHz_OUT
10
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Appendix A
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Table 8. Pinmap (continued)
DP83848C/I/YB Signal Name
DP83848C/I/YB Pin No
DP83846 Pin No
7
n/a
POWER DOWN/INT
PFBIN1:2
18,37
n/a
POWER FEEDBACK IN
PFBOUT
23
n/a
POWER FEEDBACK OUT
22,32,48
4,7,12, 14,24,35,
43,49,57, 65,72
15,19,35,36,47
2,6,9,13, 15,18,48,
73,34,42, 53,56,64,
19,76,79
GROUND
8,9,10,11,12,20
1,5,8, 20,21,22,
47,63,68, 69,70,71,
74,75,77, 78, 80
RES
PWR_DOWN/INT
Description
Supply Pins
VDD
GND
3.3 V
Reserved Pins
RESERVED
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Appendix B Register Differences
This section covers differences between the registers in DP83848C/I/YB and DP83846 applicable to
software configuration of these devices.
All the IEEE specified registers of Texas Instruments physical layer devices comply with the respective
IEEE standards. Only vendor specific registers have functions that may vary from device to device. If none
of the vendor specific registers are modified, for operation in the system application, the devices will have
similar operations. In designs that do access or adjust any of these optional registers, the system can use
the PHY_ID register, offset 03h, to detect which device is being used and make the appropriate changes
in settings of device registers. Specific functions, of these vendor defined registers, may be available in
another register, or possibly in a different bit within the same register location. For additional information,
or more specific definitions, see the device-specific data sheets.
Table 9. Register Bit Definitions
Register
Address
Hex
Register
Name
Device
Register Description
DP83848C/I/YB
DP83846
Basic Mode Control
Bit 15 – Reset (See Section
Section 2.6 for the difference in
software reset)
Bit 15 – Reset (See Section
Section 2.6 for the difference in
software reset)
00h
BMCR
03h
PHYIDR2
PHY ID 2
5C90h
5C23h
04h
ANAR
Auto-Neg Adv
Bit 11 - ASM_DIR
Bit 11 - Res
05h
ANLPAR
Auto-Neg Link Partner
Ability
Bit 11 - ASM_DIR
10h
PHYSTS
PHY Status
11h
MICR
12h
MISR
16h
PCSR
Bit 10 and 11 - Res
Bit 10 - Pause
Bit 14 MDI-X mode
Bit 14 Res
Bit 7 MII Interrupt
Bit 7 - Res
MII Interrupt Control
Register to control test Interrupt,
Interrupt Enable and Interrupt
Output Enable
Res
Mll Interrupt Status
Register for Interrupt enable and
status
Res
PCS Sub-Layer cfg and
sts
Bit 12 Res
Bit 12 BYP_4B5B
Bit 11 Res
But 11 FREE_CLK
Bit 7 DESC_TIME
Bit 7 Unused
Bit 1 Res
Bit 1 SCRAM_BYPASS
Bit 0 Res
Bit 0 DESCRAM_BYPASS
17h
RBR
RMII and Bypass
Configure or bypass RMii mode
Res
18h
LEDCR
LED Direct Control
Control LED outputs
Res
Register changes (See data
sheet)
Register changes (See data sheet)
19h
PHYCR
PHY Control
1Ah
10BTSCR
10 Base-T
Status/Control
Bit 15 10BT serial
Bits 14 to 12 Res
Bit 15:9 - Res
Bits 11:9 - SQUELCH
12
1Bh
CDCTRL1
CD Test Control
Register changes (See datasheet)
Register changes (See data sheet)
1Dh
EDCR
Energy Detect Control
Enable and control Energy Detect
Res
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TI E2E Community
e2e.ti.com
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