Texas Instruments | AN-1977 LMH0346 Customization with SMBus (Rev. A) | Application notes | Texas Instruments AN-1977 LMH0346 Customization with SMBus (Rev. A) Application notes

Texas Instruments AN-1977 LMH0346 Customization with SMBus (Rev. A) Application notes
Application Report
SNLA119A – July 2009 – Revised April 2013
AN-1977 LMH0346 Customization with SMBus
.....................................................................................................................................................
ABSTRACT
This application report explains how to customize the LMH0346 reclocker using the SMBus.
1
2
3
4
Contents
Introduction ..................................................................................................................
SMBus Overview ............................................................................................................
Enabling SMBus Access for the LMH0346 ..............................................................................
Description of a Subset of LMH0346 Registers .........................................................................
2
2
4
6
List of Figures
1
SMBus Transaction Format................................................................................................ 3
2
SMBus Register Write ...................................................................................................... 3
3
SMBus Register Read ...................................................................................................... 4
4
LMH0346 SMBus Implementation ........................................................................................ 5
5
SMBus Timing Parameters ................................................................................................ 5
6
LMH0346 2.97 Gbps Jitter Transfer with Different Charge Pump Current Settings
7
LMH0346 2.97 Gbps Jitter Tolerance with Different Charge Pump Current Settings.............................. 7
1
Recommended SMBus Timing ............................................................................................ 5
2
Register 00h – Basic Control .............................................................................................. 6
3
Register 0Eh – Modifying the CDR Loop Bandwidth ................................................................... 7
4
Register 10h – Powering Down the SDO and SCO/SDO2 CML Drivers ............................................ 8
5
Register 32h – Reading Back the Detected Rate
...............................
7
List of Tables
......................................................................
8
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Introduction
1
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Introduction
The LMH0346 3G HD/SD SDI Reclocker provides excellent jitter performance for 2.97 Gbps digital video
streams that comply with the SMPTE 424M standard. The reclocker’s small size, excellent jitter
performance, and low power make it ideal for applications such as routers, video switchers, and
distribution amplifiers.
The LMH0346 provides pin-accessible features such as: two differential serial data outputs (one
programmable as a data-rate clock output), auto or manual rate select, auto or manual data bypass,
SD/HD rate indicator, output mute, and lock detect indicator.
Additional features of the LMH0346 can be accessed through special SMBus register access. Care must
be taken when controlling the device using the registers as normal pin-control functionality of the device is
disabled in this mode.
This application report includes an overview of SMBus, followed by details on how to enable SMBus
access on the LMH0346. Information on using the LMH0346 SMBus to accomplish the following three
useful tasks is included at the end of the document:
• Read back the detected data rate (2.97 Gbps, 1.485 Gbps, or 270 Mbps)
• Modify the CDR loop bandwidth
• Disable the second CML output driver to minimize power
2
SMBus Overview
The System Management Bus (SMBus) is a two-wire serial interface through which various system
component chips can communicate with each other and with the rest of the system.
The SMBus is controlled through two lines: a clock line (SCL) and a data line (SDA). SCL is the clock
output from the master (i.e., FPGA host) to the slave devices on the bus. SDA is the bidirectional data
signal between the host and the slave devices on the bus. SCL and SDA are both open drain and require
external pullup resistors. (On the LMH0346, the BYPASS/AUTO BYPASS pin is used for SDA, and the
OUTPUT MUTE pin is used for SCL.)
Most microcontrollers support SMBus. Please refer to the SMBus Specification version 2.0 for
implementation details.
2.1
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCL is high. Data can only
change state when SCL is low. Two unique states define the message START and STOP conditions:
START: A high-to-low transition on SDA while SCL is high indicates a message START condition.
STOP: A low-to-high transition on SDA while SCL is high indicates a message STOP condition.
The host generates START and STOP patterns at the beginning and end of each transaction.
2.2
SMBus Transactions
Each byte (8 bits) is transferred MSB first, followed by an acknowledge bit. The acknowledge bit is “0” for
acknowledge (ACK), or “1” for not acknowledge (NACK). The host generates nine clock pulses for each
byte transfer, and the ninth clock pulse constitutes the acknowledge cycle. The transmitter releases the
SDA line during the acknowledge clock cycle to allow the receiver to send the ACK (or NACK). See
Figure 1.
2
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SMBus Overview
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ACK Signal from
Receiver
SDA
MSB
SCL
S
1
2
3-6
7
8
9
ACK
1
Start
Condition
2
3-8
9
ACK
Clock Line Held
Low by Receiver
While Interrupt
Serviced
Byte Complete
Interrupt Within
Receiver
P
Stop
Condition
Figure 1. SMBus Transaction Format
2.3
Writing a Register
Word Address
Data
Stop
Device
Address
Write
Start
To write a register, the following protocol is used (refer to Figure 2 and also see the SMBus 2.0
specification).
1. The host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The device (slave) drives the ACK bit (“0”).
3. The host drives the 8-bit Register Address.
4. The device drives an ACK bit (“0”).
5. The host drives the 8-bit data byte.
6. The device drives an ACK bit (“0”).
7. The host drives a STOP condition.
ACK
LSB
ACK
LSB
R/W
ACK
MSB
MSB
SDA
Line
Figure 2. SMBus Register Write
2.4
Reading a Register
To read a register, the following protocol is used (refer to Figure 3 and also see the SMBus 2.0
specification).
1. The host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The device (slave) drives the ACK bit (“0”).
3. The host drives the 8-bit Register Address.
4. The device drives an ACK bit (“0”).
5. The host drives a START condition.
6. The host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The device drives an ACK bit (“0”).
8. The device drives the 8-bit data value (register contents).
9. The host drives a NACK bit (“1”) indicating end of the READ transfer.
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Enabling SMBus Access for the LMH0346
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Data
Stop
Device
Address
Read
Word Address
Start
Device
Address
Write
Start
10. The host drives a STOP condition.
NACK
LSB
ACK
MSB
LSB
ACK
LSB
R/W
ACK
MSB
MSB
SDA
Line
Figure 3. SMBus Register Read
3
Enabling SMBus Access for the LMH0346
The LMH0346 SMBus registers were intended for production test control and device monitoring. These
registers are not documented in the LMH0346 datasheet and their performance has not been
characterized. However, some of these registers are useful in certain applications.
Please note the following important points about using the LMH0346 SMBus mode:
• A dedicated SMBus is required per reclocker.
• The LMH0346 SMBus pins must be driven from a 3.3V source (they are not 5V compliant).
• When the SMBus mode is enabled, the hardware power-on-reset function in the LMH0346 is disabled.
When using the LMH0346 SMBus features, the registers and state machine must be initialized by first
powering up in Auto Rate mode and then switching to SMBus mode.
• The 7-bit address for the LMH0346 is 57h. The LSB is set to 0b for a WRITE and 1b for a READ, so
the 8-bit default address for a WRITE is AEh and the 8-bit default address for a READ is AFh.
The following steps explain how to enable SMBus access for the LMH0346:
• Connect RATE0 pin to VCC (nominally 3.3V), while maintaining the ability to drive this pin high or low
to properly reset the device.
• Connect RATE1 pin to VCC (nominally 3.3V), while maintaining the ability to drive this pin high or low
to properly reset the device.
• Connect SCO_EN pin to ground. (Note that enabling the serial clock output while using SMBus access
requires a register bit to be set.)
• Access SDA (SMBus serial data input/output) through the BYPASS/AUTO BYPASS pin of the
LMH0346. This pin requires an external 10 kΩ pullup resistor to VCC. Voltage levels are LVCMOS.
• Access SCL (SMBus serial clock input) through the OUTPUT MUTE pin of the LMH0346. This pin
requires an external 10 kΩ pullup resistor to VCC. Voltage levels are LVCMOS
• Power up the LMH0346 in Auto Rate mode (RATE0=0, RATE1=0) and then change it into SMBus
mode (RATE0=1, RATE1=1) after power up. The LMH0346 should be held in Auto Rate mode for
approximately 300 ms prior to entering SMBus mode. This procedure ensures a proper reset of the
SMBus registers and reclocker state machine.
Figure 4 shows the SMBus implementation for the 20-pin e-TSSOP version of the LMH0346. Table 1 and
Figure 5 show the recommended SMBus Timing.
4
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Enabling SMBus Access for the LMH0346
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VCC
VCC
VCC
56 nF
10 k:
10 k:
1
2
3
RATE0
4
RATE1
5
6
Differential
Input
100:
7
8
9
10
VCC
20
SCO_EN
19
SD/ HD
18
VCCO
RATE0
17
SDO
RATE1
16
SDI
LMH0346 SDO 15
VCCO
SDI
14
VCC
SCO/SDO2
13
SCO/SDO2
BP/ AUTO-BP
12
OP MUTE
LOCK DET
11
XTAL IN/EXT CLK XTAL OUT
LF1
SD/ HD
LF2
Primary
Output
Secondary
Output
DAP
10 k:
27 MHz
10 k:
39 pF
SDA
SCL
39 pF
LOCK DET
Figure 4. LMH0346 SMBus Implementation
Table 1. Recommended SMBus Timing
Symbol
Parameter
Min
fSMB
Bus Operating Frequency
10
Typ
Max
Units
100
tBUF
Bus free time between Stop and Start Condition
4.7
kHz
µs
tHD:STA
Hold time after (repeated) Start Condition. After this period, the first clock is
generated.
4.0
µs
tSU:STA
Repeated Start Condition setup time
4.7
µs
tSU:STO
Stop Condition setup time
4.0
µs
tHD:DAT
Data hold time
300
ns
tSU:DAT
Data setup time
250
ns
tLOW
Clock low period
4.7
µs
tHIGH
Clock high period
4.0
50
µs
tF
Clock/Data Fall Time
300
ns
tR
Clock/Data Rise Time
1000
ns
tPOR
Time in which device must be operational after power on
500
ms
tLOW
tR
tHIGH
SCL
tHD:STA
tHD:DAT
tBUF
See *Note
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
ST
SP
* Note: SDA and SCL should be held low for 2 µs after a Start condition to properly de-assert the Start indicator.
Figure 5. SMBus Timing Parameters
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Description of a Subset of LMH0346 Registers
4
Description of a Subset of LMH0346 Registers
NOTE:
4.1
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When writing to the LMH0346 registers, RSVD bits must be written with the indicated default
values. Only the non-reserved register bits should be modified.
Register 00h – Basic Control
Register 00h is used to invoke the pin control modes that aren't accessible when the SMBus is enabled,
as shown in Table 2.
Table 2. Register 00h – Basic Control
Address
R/W
Bits
Name
Default
Description
00h
R/W
7:6
RATE
00
Rate select (bit 6 = RATE0, bit 7 = RATE1).
00: Auto rate select (default)
01: 270 Mbps.
10: 1.483, 1.485, 2.967, 2.97 Gbps.
11: 2.967, 2.97 Gbps.
5:3
RSVD
000
Reserved. These bits must always be 000.
2
BYPASS
0
Bypass/Auto Bypass.
0: Normal operation. Reclocking automatically bypassed
when reclocker is unlocked or data rate is not supported.
1: Reclocking is bypassed.
1
OPMUTE
0
Output Mute.
0: Normal operation (outputs not muted).
1: Outputs are muted.
0
SCO_EN
0
SCO Enable.
0: SCO/SDO2 output is data.
1: SCO/SDO2 output is clock.
Bits [7:6] can be controlled to force the rate detection mode.
When SMBus mode is used, the SCO_EN and OUTPUT MUTE pins are not available. In order to observe
the serial clock, bit 0 must be set high. Similarly, in order to mute the outputs, bit 1 must be set high.
6
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Description of a Subset of LMH0346 Registers
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4.2
Register 0Eh – Modifying the CDR Loop Bandwidth via the Charge Pump Current
The default settings of the LMH0346 registers have been set to minimize output jitter while meeting
SMPTE 424M specifications for jitter tolerance. It may be useful in some applications to increase the loop
bandwidth of the CDR to extend input jitter tolerance to higher frequencies. Register 0Eh can be used to
increase the LMH0346’s CDR charge pump current, as shown in Table 3. Increasing the charge pump
current will, in turn, increase the loop bandwidth.
Figure 6 and Figure 7 show 2.97 Gbps Jitter Transfer and Jitter Tolerance, respectively, for the LMH0346
with different charge pump current settings.
Table 3. Register 0Eh – Modifying the CDR Loop Bandwidth
R/W
Bits
Name
Default
0Eh
R/W
7:4
RSVD
0001
3:2
CHARGE
PUMP
00
Charge Pump current.
00: Current = 25 µA, CDR BW @ 2.97 Gbps = 2.7 MHz.
01: Current = 50 µA, CDR BW @ 2.97 Gbps = 5.3 MHz.
10: Current = 75 µA, CDR BW @ 2.97 Gbps = 7.8 MHz.
11: Current = 100 µA, CDR BW @ 2.97 Gbps = 9.5 MHz.
1:0
RSVD
11
Reserved. These bits must always be 11.
GAIN (dB)
Address
0.5
-0.5
-1.5
-2.5
-3.5
-4.5
-5.5
-6.5
-7.5
-8.5
100 PA Charge Pump
-9.5
-10.5
75 PA Charge Pump
-11.5
50 PA Charge Pump
-12.5
25 PA Charge Pump
-13.5
2
3
4
5
10
10
10
10
Description
Reserved. These bits must always be 0001.
6
10
7
10
10
8
SINE FREQUENCY (Hz)
Figure 6. LMH0346 2.97 Gbps Jitter Transfer with Different Charge Pump Current Settings
1000
100 PA Charge Pump
JITTER AMPLITUDE (UI)
75 PA Charge Pump
50 PA Charge Pump
100
25 PA Charge Pump
10
1
0.1
2
10
3
10
10
4
5
10
10
6
7
10
8
10
SINE FREQUENCY (Hz)
Figure 7. LMH0346 2.97 Gbps Jitter Tolerance with Different Charge Pump Current Settings
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Description of a Subset of LMH0346 Registers
4.3
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Register 10h – Powering Down the SDO and SCO/SDO2 CML Drivers to Save Power
The LMH0346 has two separate CML output drivers. These drivers can be independently powered down if
not required in the system (that is, if the system needs only one CML driver), as shown in Table 4.
Approximate power savings is 24 mA/buffer.
Table 4. Register 10h – Powering Down the SDO and SCO/SDO2 CML Drivers
4.4
Address
R/W
Bits
Name
Default
10h
R/W
7:3
RSVD
10000
Description
Reserved. These bits must always be 10000.
2
PD SDO
0
Power down SDO output driver.
0: Normal operation.
1: SDO output driver is powered down.
1
PD
SCO/SDO2
0
Power down SCO/SDO2 output driver.
0: Normal operation.
1: SCO/SDO2 output driver is powered down.
0
RSVD
0
Reserved. This bit must always be 0.
Register 32h – Detecting the Locked Rate and Distinguishing Between 3G, HD, and
SD
Register 32h can be read to determine the status of the lock detection state machine – and which data
rate has been detected. While acquiring lock at a given frequency, the LMH0346 will automatically cycle
through the following states:
1. Coarse acquisition (adjusts VCO center frequency with the control voltage held to mid-supply).
2. Frequency acquisition (tunes the VCO to a multiple of the 27 MHz crystal frequency).
3. Phase acquisition (tunes the VCO phase to optimally clock the data input to the LMH0346).
4. Locked.
The register values are shown in Table 5.
Table 5. Register 32h – Reading Back the Detected Rate
8
Address
R/W
Bits
Name
Default
32h
R
7:4
STATE
000
3:0
RSVD
0000
Description
Status of Lock Detection State Machine.
0000, 0001, 0010, 0011: Reserved.
0100: Rate = 270 Mbps, Coarse acquisition.
0101: Rate = 270 Mbps, Frequency acquisition.
0110: Rate = 270 Mbps, Phase acquisition.
0111: Rate = 270 Mbps, LOCKED.
1000: Rate = 1.483/1.485 Gbps, Coarse acquisition.
1001: Rate = 1.483/1.485 Gbps, Frequency acquisition.
1010: Rate = 1.483/1.485 Gbps, Phase acquisition.
1011: Rate = 1.483/1.485 Gbps, LOCKED.
1100: Rate = 2.967/2.97 Gbps, Coarse acquisition.
1101: Rate = 2.967/2.97 Gbps, Frequency acquisition.
1110: Rate = 2.967/2.97 Gbps, Phase acquisition.
1111: Rate = 2.967/2.97 Gbps, LOCKED.
Reserved.
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