Texas Instruments | Enabling Redundancy in Multi-Gigabit Links w/DS40MB200 Mux/Buffer (Rev. A) | Application notes | Texas Instruments Enabling Redundancy in Multi-Gigabit Links w/DS40MB200 Mux/Buffer (Rev. A) Application notes

Texas Instruments Enabling Redundancy in Multi-Gigabit Links w/DS40MB200 Mux/Buffer (Rev. A) Application notes
Application Report
SNLA075A – October 2005 – Revised April 2013
AN-1399 Enabling Redundancy in Multi-Gigabit Links With
DS40MB200 Mux/Buffer
.....................................................................................................................................................
ABSTRACT
The DS40MB200 is a new signal conditioning mux/buffer in TI’s high-speed product portfolio. It enables
redundancy and acts as a repeater in high-speed backplanes and cables. It features programmable preemphasis and fixed input equalization, enabling error free data links to 4 Gbps. It can also be used as a
signal conditioning driver to provide equalization to FR4 board traces as well as cables, shielding host
ASIC, FPGA or SerDes from dealing with the impairments of the transmission medium.
1
2
3
4
5
6
Contents
Introduction ..................................................................................................................
Redundancy .................................................................................................................
Signal Conditioning .........................................................................................................
DS40MB200 as a Driver-Side Equalizer .................................................................................
DS40MB200 as a Cable Equalizer .......................................................................................
References ...................................................................................................................
1
2
4
5
6
7
List of Figures
1
1
Functional Block Diagram of the DS40MB200 .......................................................................... 2
2
DS40MB200 in an Active Backplane ..................................................................................... 3
3
DS40MB200 in a Passive Backplane .................................................................................... 4
4
Pre-Emphasis Waveforms Before and After a Lossy Transmission Line............................................ 5
5
DS40MB200 as an Equalizer Used With ASIC/SerDes
6
DS40MB200 as a Cable Equalizer ....................................................................................... 6
7
Data Eye Pattern After a 10-Meter CAT7 Cable at 1.25 Gbps
8
Data Eye Pattern After a 10-Meter CAT7 Cable at 2.5 Gbps ......................................................... 7
9
Data Eye Pattern After a 5-Meter CAT7 Cable at 4 Gbps ............................................................. 7
...............................................................
.......................................................
6
6
Introduction
In a communication system, redundancy is an important feature to maintain reliable operation and prevent
down time caused by unexpected failures. Implementing redundancy in large scale ASIC or SerDes
components significantly increases the pin-count of the component packages and, very often, carries the
penalty of performance degradation. The DS40MB200 mux/buffer, a new addition to Texas Instruments
high-speed product portfolio, is designed to enable redundancy in data links to 4 Gbps. The DS40MB200
has built-in signal conditioning features to enable error-free data transmission over FR4 backplanes or
high-speed cables.
All trademarks are the property of their respective owners.
SNLA075A – October 2005 – Revised April 2013
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AN-1399 Enabling Redundancy in Multi-Gigabit Links With DS40MB200
Mux/Buffer
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1
Redundancy
2
www.ti.com
Redundancy
The DS40MB200 is a dual bi-directional multiplexor and repeater available in a small leadless LLP-48
package. Each port of the DS40MB200 consists of a transmit signal path through a 1:2 repeater, sending
data to two redundancy cards. The receive path consists of a 2:1 multiplexor that selects the
communication link between the host card and one of the two redundancy cards. Figure 1 shows the block
diagram of the DS40MB200 illustrating its functions.
LO_0 ±
EQ
SIA_0 ±
EQ
SIB_0 ±
PRE_L
MUX_S0
LB0A
Port 0
SOA_0 ±
PRE_S
LI_0 ±
SOB_0 ±
EQ
PRE_S
LO_1 ±
LB0B
EQ
SIA_1 ±
EQ
SIB_1 ±
PRE_L
MUX_S1
LB1A
Port 1
SOA_1 ±
PRE_S
LI_1 ±
SOB_1 ±
EQ
PRE_S
PreL_0
PreL_1
PreS_0
PreS_1
Pre-emphasis
Control
LB1B
VCC
PRE_L
GND
PRE_S
RSV
Figure 1. Functional Block Diagram of the DS40MB200
System designers can choose to place the DS40MB200 on an active or passive backplane to support
redundancy. Figure 2 illustrates the use of the DS40MB200 in an active backplane. With the signal
conditioning features built into the DS40MB200, this arrangement allows system designers to extend the
span of the backplane traces. Many system designers implement redundancy on the host card. Figure 3
illustrates the use of the DS40MB200 in a passive backplane.
2
AN-1399 Enabling Redundancy in Multi-Gigabit Links With DS40MB200
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Redundancy
www.ti.com
Line
Card
ASI
C
Backplane
2
H
T
T
D
T_CLK
SerDes
RD
R_CLK
HR
LI
SOA
SIB
SOB
ASIC or FPGA with integrated SerDes
DS40MB200
Mux/
Buf SIA
LO
REFCLK
Clock
Distribution
Switch Card2
Switch Card1
Channel 1
ASI
C
T
D
T_CLK
H
T
SerDes
RD
R_CLK
HR
REFCLK
Clock
Distribution
ASIC or FPGA with integrated SerDes
Figure 2. DS40MB200 in an Active Backplane
SNLA075A – October 2005 – Revised April 2013
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3
Signal Conditioning
www.ti.com
Line
Card
ASI
C
Backplane
H
T
T
D
T_CLK
SerDes
RD
R_CLK
HR
SOA
LI
SOB
DS40MB200
Mux/
SIA
Buf
SIB
LO
2
REFCLK
Clock
Distribution
ASIC or FPGA with integrated SerDes
Switch Card2
Switch Card1
ASI
C
H
T
T
D
T_CLK
SerDes
RD
R_CLK
HR
REFCLK
Clock
Distribution
ASIC or FPGA with integrated SerDes
Figure 3. DS40MB200 in a Passive Backplane
3
Signal Conditioning
In implementing the redundancy function in either a passive or an active backplane, the DS40MB200
mux/buffer is designed to interface with the transmission medium directly. Each signal path of the
DS40MB200 is designed with signal conditioning features that equalize transmission loss and reduce jitter
caused by the transmission medium.
Each output driver of the DS40MB200 has pre-emphasis to compensate the transmission loss disparity of
the transmission medium that it is driving. Whenever there is a transition of logic state, the driver sends
the first data bit with its full amplitude. Because of lower transmission loss from the transmission medium,
the driver sends the subsequent data bits of the same logic state with reduced amplitude. Effectively, the
driver conditions the output signal amplitude such that the lower and higher frequency pulses reach
approximately the same amplitude at the receiving end of the transmission medium. Figure 4 illustrates
the pre-emphasis waveforms before and after a lossy transmission line.
Pre-emphasis minimizes the deterministic jitter caused by amplitude disparity of the transmission line. The
DS40MB200 provides four steps of pre-emphasis ranging from 0, 3, 6 and 9 dB to handle different amount
of transmission losses. These four pre-emphasis steps are user-selectable through two logic control pins.
4
AN-1399 Enabling Redundancy in Multi-Gigabit Links With DS40MB200
Mux/Buffer
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DS40MB200 as a Driver-Side Equalizer
www.ti.com
dB
f
50
50
Transmission Medium
DS 40MB200
Figure 4. Pre-Emphasis Waveforms Before and After a Lossy Transmission Line
Each input stage of the DS40MB200 has a fixed equalizer followed by a limiting amplifier and driver. The
input equalizer provides a boost to higher frequency signals that are attenuated by the transmission loss
of the input board trace. The fixed equalizer is designed to equalize about 5 dB of transmission loss
disparity from the input transmission line at 4 Gbps. The input equalizer is capable of providing jitter
reduction of about 30 ps caused by a 5 dB transmission loss.
The input equalizer provides secondary equalization to clean up the deterministic jitter caused by the input
transmission line. The driver re-shapes and re-transmits the bit stream with pre-emphasis, compensating
for loss caused by the transmission medium. With the DS40MB200 on both ends of the transmission
medium, system designers can handle up to 14 dB of transmission loss and enable error free data
transmission to 4 Gbps.
4
DS40MB200 as a Driver-Side Equalizer
In addition to its redundancy function, the DS40MB200 can be used as an external equalizer, shielding the
host ASIC or FPGA from the job of handling the transmission impairments from the interconnecting
transmission medium. The DS40MB200 supports a high output amplitude of 1200 mVP-P with fast edge
rates of about 80 ps. Using an external equalizer, such as the DS40MB200, provides system designers
the option of using a lower cost ASIC or FPGA, and distributes signal conditioning devices at critical
locations to improve signal integrity. Figure 5 illustrates the use of DS40MB200 with an ASIC/FPGA.
SNLA075A – October 2005 – Revised April 2013
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AN-1399 Enabling Redundancy in Multi-Gigabit Links With DS40MB200
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Copyright © 2005–2013, Texas Instruments Incorporated
5
DS40MB200 as a Cable Equalizer
www.ti.com
DS40MB200
TX
PLL
ASIC
SerDes
BP
Con
Coupled
Differential
board traces
BP
Con
EQ
RX
PLL
EQ
DE
DE
RX
PLL
DS40MB200
TX
DE
DE
RX
EQ
EQ
ASIC
SerDes
TX
PLL
Backplane
Figure 5. DS40MB200 as an Equalizer Used With ASIC/SerDes
5
DS40MB200 as a Cable Equalizer
The DS40MB200 provides equalization for transmission media such as FR4 board traces, backplanes, or
cables. With programmable pre-emphasis, it can handle transmission losses from different cable lengths
by setting the proper pre-emphasis steps of 0, 3, 6 or 9 dB through control pins. Figure 6 depicts the use
of DS40MB200 as a cable equalizer. Figure 7, Figure 8, and Figure 9 show data eye patterns with the
DS40MB200 driving a CAT7 cable.
DS40MB200
TX
PLL
ASIC
SerDes
RX
PLL
EQ
DE
DE
EQ
RJ45
Twisted Pair
1
2
3
TX
4
5
6
RX
7
8
Twisted Pair
RJ45
1
2
3
4
5
6
7
8
DS40MB200
RX
PLL
EQ
DE
DE
EQ
ASIC
SerDes
TX
PLL
Figure 6. DS40MB200 as a Cable Equalizer
Figure 7. Data Eye Pattern After a 10-Meter CAT7 Cable at 1.25 Gbps
6
AN-1399 Enabling Redundancy in Multi-Gigabit Links With DS40MB200
Mux/Buffer
SNLA075A – October 2005 – Revised April 2013
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
References
www.ti.com
Figure 8. Data Eye Pattern After a 10-Meter CAT7 Cable at 2.5 Gbps
Figure 9. Data Eye Pattern After a 5-Meter CAT7 Cable at 4 Gbps
6
References
•
•
Dual 4.0 Gbps 2:1/1:2 CML Mux/Buffer With Transmit Pre-Emphasis and Receive Equalization
(SNLS144)
AN-1389 Setting Pre-Emphasis Level for DS40MB200 Dual 4Gb/s Mux/Buffer (SNLA073)
SNLA075A – October 2005 – Revised April 2013
Submit Documentation Feedback
AN-1399 Enabling Redundancy in Multi-Gigabit Links With DS40MB200
Mux/Buffer
Copyright © 2005–2013, Texas Instruments Incorporated
7
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