Texas Instruments | RS-485 failsafe biasing: Old versus new transceivers | Application notes | Texas Instruments RS-485 failsafe biasing: Old versus new transceivers Application notes

Texas Instruments RS-485 failsafe biasing: Old versus new transceivers Application notes
Interface (Data Transmission)
Texas Instruments Incorporated
RS-485 failsafe biasing: Old versus
new transceivers
By Thomas Kugelstadt
Senior Applications Engineer
It is incredible that an industrial interface standard such
as RS-485, having been around for 30 years, still appears
obscure to many industrial-network designers. While there
should be plenty of literature available explaining the standard fundamentals, the Texas Instruments (TI) application
team continues to receive basic questions on a weekly
basis, such as how to apply failsafe biasing to an idle bus.
Failsafe biasing refers to the technique of providing a
differential voltage to a terminated, idle bus in order to
maintain the receiver output of a bus transceiver in a
logic-high state. This technique is commonly required
when legacy transceiver designs are used for designing
bus networks.
Legacy designs such as transceiver X in Table 1 possess
a wide input sensitivity of ±200 mV. This means that small
input signals between +200 mV and –200 mV can turn the
receiver output either high or low, thus making the output
state indeterminate.
During a data transmission, the differential line voltage
of a fully loaded bus is required to be higher than ±1.5 V,
which is well above the transceiver’s input sensitivity.
However, during a handover of bus access from one node
to another, or during a transmission pause, the bus idles.
Then the low-impedance termination resistors, connecting
the two conductors of the differential signal pair with each
other, cause the differential bus voltage to be 0 V, right in
the middle of the transceiver’s input sensitivity, which produces an indeterminate output.
Therefore, to keep the receiver outputs at a logic high
during bus idling, a positive, differential failsafe voltage
higher than a receiver’s positive input threshold (VIT+)
must be applied to the bus.
Table 1 shows that the theoretically required failsafe
levels decrease with the receiver’s positive input threshold
from one generation to the next. While transceiver X
requires a minimum of +200 mV of failsafe biasing, transceivers Y and Z can do without it as their positive input
thresholds are below 0 V. Unfortunately, these values
apply only in noise-free environments such as laboratories
or the Earth’s poles, and certainly not in the harsh envi­ron­
ments of industrial factories where RS-485 networks are
commonly installed.
Differential noise induced into the bus wires can falsely
trigger a receiver input if the projected noise magnitude
has not been included in the failsafe voltage calculation.
Using a twisted-pair bus cable helps to convert noise
induced along the cable run into common-mode noise.
This noise is then rejected by the receiver’s differential
input. However, cable irregularities as well as noise induced
at the bus node connectors might contribute to differential
noise that cannot be rejected by a receiver.
Figure 1 on the next page shows that when a noise signal
is superimposed onto the positive input threshold levels of
transceivers X and Y, the minimum hysteresis voltage deter­
mines at which noise level the receiver output will assume
the wrong logic state. Table 1, in which the receiver param­
eters have been extracted from different datasheets, gives
a minimum hysteresis level only for transceiver Z. For the
two older transceivers, X and Y, only typical hysteresis
values are provided. In a situation such as determining the
minimum failsafe value for a worst-case scenario, typical
values are meaningless. In fact, the TI application team
has measured minimum hysteresis voltages for both
transceivers X and Y that were nearly half the specified
typical values.
Furthermore, there is the possibility that for a given
transceiver the hysteresis window might be located anywhere between the positive and negative input thresholds.
Hence, for a worst-case calculation, one must assume that
the hysteresis window is at the uppermost positive
Table 1. Receiver input sensitivities of first-, second-, and third-generation (X, Y, and Z) transceivers
POSITIVE-GOING INPUT
THRESHOLD VOLTAGE, VIT+
(mV)
NEGATIVE-GOING INPUT
THRESHOLD VOLTAGE, VIT–
(mV)
MIN
MAX
MIN
X
(SN65LBC176)
200
–200
50
–0.2 V < VAB < 0.2 V
Y
(SN65HVD12)
–10
–200
35
–0.2 V < VAB < 0.01 V
–20
–200
80
–0.2 V < VAB < 0.07 V
TRANSCEIVER
Z
(SN65HVD72)
TYP
–70
TYP
MAX
–150
INPUT HYSTERESIS
VOLTAGE, VHYS
(mV)
MIN
50
TYP
MAX
RECEIVER OUTPUT IS
INDETERMINATE WHEN
25
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threshold limit. Therefore, to determine a sufficiently
high failsafe-biasing voltage, the projected peak-to-peak
noise level must be added to the positive input threshold
voltage: VAB(min) = VIT+ + VN(PP_max).
For a well-balanced bus with a noise level of VN(PP_max)
= 50 mV, using transceiver X requires a differential failsafe
voltage of VAB(min) = 200 mV + 50 mV = 250 mV (Figure 1).
Operating transceiver Y at the same noise level without
external biasing could be risky, particularly when considering a significantly smaller minimum hysteresis than the
nominal value. Again, adding the noise level to the positive
input threshold provides a minimum failsafe voltage of
VAB(min) = –10 mV + 50 mV = 40 mV.
The more modern third-generation transceiver Z can
maintain a stable output without failsafe biasing. Its positive
input threshold of –20 mV and the specified minimum
hysteresis of 50 mV allow for a maximum peak-to-peak
noise level of 140 mV, which is almost three times the
noise immunity of legacy devices with external biasing.
If it is not possible to use modern transceivers, the cal­cu­
lation methods presented in the following section can be
used to optimize the failsafe-biasing networks required by
legacy transceivers.
Failsafe biasing for legacy transceivers
Figure 2 shows a terminated RS-485 bus with its distributed network nodes and a failsafe-biasing network con­
sisting of two biasing resistors (RFS ) and a termination
resistor (R T1). With the majority of RS-485 applications
being master/slave systems, the failsafe-biasing network is
Figure 1. The need for failsafe biasing depends on the transceiver
VAB
VAB(min)
0.2 V
VHYS(min)
VAB
VAB
VN(PP_max)
VAB(min)
0V
0V
0V
–0.01 V
–0.02 V
VHYS(min)
–0.2 V
VHYS(min)
–0.2 V
–VAB
–0.2 V
–VAB
(a) Legacy transceiver X with
failsafe biasing
–VAB
(b) Legacy transceiver Y with
failsafe biasing
(c) Modern transceiver Z does
not require failsafe biasing
Figure 2. RS-485 bus with failsafe-biasing network for legacy transceivers
VS
R FS
R T1
R INA
Z0
VAB
R INB
R T2
R FS
26
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commonly installed at the master end of the bus,
Figure 3. Common-mode input resistance of the
while the other cable end receives a termination
receiver section
resistor (R T2 ) matching the characteristic line
impedance (Z0 ).
The major drawback of failsafe biasing is its
VS
common-mode loading. A common-mode load is
R2A
R2B
the resistance between a signal conductor and the
R1A
R INA
local transceiver ground. Transceivers have a high
A
R
R
common-mode load, primarily because the receivB
R INB
er’s input-voltage divider (Figure 3) reduces the
R1B
input signal by a factor of 10 or more.
R3B
R3A
The internal resistor network, imposing a
GND
common-mode load on each of the A and B bus
terminals, can be represented by a combined input
resistance (RIN). The total common-mode resist­
ance of an entire transceiver network then can be
Because RFS in combination with RINEQ makes up the
expressed through an equivalent input resistance (RINEQ)
total common-mode load for a signal line, the parallel
for both the A and the B line.
value of the two must not exceed the specified maximum
The RS-485 standard specifies a maximum commonof 375 Ω, which is expressed through
mode load per bus line with 375 Ω. Initially this value is
allocated for only the bus transceivers. Implementing a
1
1
1
RFS || RINEQ = 375 Ω or
+
=
.
(2)
failsafe-biasing network can consume a significant amount
RINEQ RFS 375 Ω
of this loading, therefore allowing only a reduced number
of transceivers to be connected to the bus.
At the remote cable end, the termination resistor (R T2 )
Figure 4 presents a lumped equivalent circuit of an
must match the characteristic line impedance (Z0 ):
RS-485 bus. This circuit allows the failsafe resistor values
1
1
to be determined as a function of the required failsafe bus
RT2 = Z0 or
=
.
(3)
RT2 Z0
voltage (VAB ), the supply voltage (VS ), the common-mode
loading caused by RFS and RINEQ , and the characteristic
At the biasing network, the parallel combination of R T1
line impedance (Z0 ). Determining the currents into nodes
and the two failsafe resistors must also match Z0:
A and B and solving for the respective line voltages (VA
1
1
1
and VB ) yields
RT1 || 2 RFS = Z0 or
=
−
.
(4)
RT1 Z0 2RFS
VS − VA
VA − VB VA − VB
VA
=
+
+
⇒
Inserting Equations 2, 3, and 4 into Equation 1 then
RFS
RT1
RT2
RINEQ
yields the bus failsafe voltage:
V − V
1 
 1
VS(min)
VA = RINEQ ×  S A − ( VA − VB ) × 
+

 RT1 RT2  
VAB(min) =
(5)
 RFS
 1
4
+
−1
RFS 
for Node A, and
 375 Ω Z 
0
VB
V − VB
V − VB
VB
= A
+ A
−
⇒
RFS
RT1
RT2
RINEQ
Figure 4. Lumped equivalent circuit

1  VB 
 1
VB = RINEQ × ( VA − VB ) × 
+

−
R
R

T1
T2  R FS 

VS
for Node B. Allowing for the difference between the two
line voltages and assuring failsafe biasing under minimum
supply conditions permits the required minimum failsafe
bus voltage to be determined:
VAB(min) =
VS(min)
RFS
×
1
1
RINEQ
1
1 
 1
+
+ 2
+
RFS
 RT1 RT 2 
R FS
A
R T1
Z0
VAB
R T2
B
(1)
R FS
R INEQ
R INEQ
27
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Solving Equation 5 for RFS provides the value of each
failsafe-biasing resistor:
 VS(min)

RFS = 
+ 1 ×
 VAB(min) 
1
1
4
+
375 Ω Z0
TI’s 3-V SN65HVD7x family and 5-V SN65HVD8x family.
These new transceivers have the following advantages:
• They don’t require an external bias resistor network
that can impose heavy common-mode loading on the
bus, reducing the number of transceivers that can be
connected to the bus.
• Therefore they allow for up to 256 transceivers on a bus.
• They tolerate high noise levels.
• They are robust against 12-kV IEC ESD and 4-kV IEC
burst transients.
• They are less expensive than legacy transceivers, and
some come in much smaller packages that provide cost
and space savings.
• The designer doesn’t have to spend time going through
a mathematical treatise like the one in this article.
(6)
After RFS is known, R T1 can be derived from Equation 4.
Once the failsafe network has been established, the maximum number of transceivers that can be connected to the
bus can be determined through
n≤
12 kΩ  1
1 
×
−
,
UL XCVR  375 Ω RFS 
(7)
where ULXCVR is the unit-load (UL) rating of the transceiver. A typical design procedure would be to calculate
RFS via Equation 6 first, then determine R T1 via Equation
4 while making R T2 = Z0 . Finally, Equation 7 would be
used to calculate the maximum number of bus transceivers possible.
The design examples in Table 2 show the typical design
procedure. This table also highlights the differences in failsafe biasing between a network using 1-UL, 5-V transceivers (X) and one using 1⁄8-UL, 3.3-V transceivers (Y).
References
1. “Interface circuits for TIA/EIA-485 (RS-485),”
Application Report. Available: www.ti.com/slla036-aaj
2. “3.3V-supply RS-485 with IEC ESD protection,”
SN65HVD72/75/78 Datasheet. Available:
www.ti.com/sllse11-aaj
Related Web sites
Conclusion
Interface (Data Transmission):
www.ti.com/interface-aaj
Failsafe biasing with the high failsafe voltages required for
first-generation transceivers causes heavy common-mode
loading and necessitates a reduction in bus transceiver
count. Using second-generation transceivers with less input
sensitivity and lower unit loading improves the situation at
low noise levels by allowing for a high transceiver count.
The best of both worlds, however, can be accomplished
only with modern third-generation transceivers, such as
www.ti.com/sn65hvd12-aaj
www.ti.com/sn65hvd72-aaj
www.ti.com/sn65hvd82-aaj
www.ti.com/sn65lbc176-aaj
Subscribe to the AAJ:
www.ti.com/subscribe-aaj
Table 2. Examples of how failsafe biasing affects bus transceiver count
TRANSCEIVER X
TRANSCEIVER Y
VS(min) = 4.75 V, VIT+ = 200 mV, ULXCVR = 1 UL
RT2 = 120 Ω (RT2 = Z0)
VS(min) = 3.05 V, VIT+ = –10 mV, ULXCVR = 1⁄ 8 UL
RT2 = 120 Ω (RT2 = Z0)
Assuming VN(PP_max) = 50 mV yields:
VAB(min) = VIT+ + VN(PP_max) = 250 mV
Assuming VN(PP_max) = 50 mV yields:
VAB(min) = VIT+ + VN(PP_max) = 40 mV
Applying Equation 6 yields:
RFS = 555.5 Ω. Choosing the closest E192 value makes RFS = 556 Ω.
Applying Equation 6 yields:
RFS = 2.11 kΩ. Choosing the closest E192 value makes RFS = 2.10 kΩ.
Applying Equation 4 yields:
RT1 = 134.5 Ω. Choosing the closest E192 value makes RT1 = 135 Ω.
Applying Equation 4 yields:
RT1 = 123.5 Ω. Choosing the closest E192 value makes RT1 = 124 Ω.
Applying Equation 7 yields:
n = 10 transceivers
Applying Equation 7 yields:
n = 210 transceivers
28
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