Texas Instruments | SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation (Rev. A) | Application notes | Texas Instruments SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation (Rev. A) Application notes

Texas Instruments SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation (Rev. A) Application notes
Application Report
SLLA340A – March 2013 – Revised April 2013
SN65DSI83, SN65DSI84, and SN65DSI85 Hardware
Implementation Guide
Yoon Lee.......................................................................................... Computer and Consumer Interface
ABSTRACT
This document includes guidelines and recommendations for implementing the SN65DSI83, SN65DSI84,
or SN65DSI85 in system hardware. These recommendations are only guidelines and it is the designer’s
responsibility to consider all system characteristics and requirements. The engineers should refer to the
datasheets for technical details such as device operation, terminal description, and so forth.
3
4
Contents
Overview .....................................................................................................................
1.1
What are SN65DSI83, SN65DSI84 and SN65DSI85? ........................................................
Hardware Implementation Guidelines ....................................................................................
2.1
Layout Recommendation .........................................................................................
2.2
RESET Implementation ...........................................................................................
2.3
ADDR ................................................................................................................
2.4
LVDS REVERSE Routing Option ................................................................................
2.5
Unused DSI Channels or Lanes .................................................................................
2.6
RSVD Pins ..........................................................................................................
References ...................................................................................................................
Reference Schematics .....................................................................................................
1
SN65DSI85 Layout Example .............................................................................................. 4
2
Cold Start Vcc Ramp Up to EN ........................................................................................... 5
3
RESET or SHUTDOWN Timing When Vcc = HIGH.................................................................... 5
4
SN65DSI8X Reference Schematics ...................................................................................... 7
1
2
2
2
3
3
4
5
5
6
6
6
7
List of Figures
List of Tables
1
SN65DSI8X Features Summary .......................................................................................... 2
2
Channel A LVDS Reverse Pin Order ..................................................................................... 6
3
Channel B LVDS Reverse Pin Order ..................................................................................... 6
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Overview
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1
Overview
1.1
What are SN65DSI83, SN65DSI84 and SN65DSI85?
The three devices: SN65DSI83, SN65DSI84 and SN65DSI85 will be referred to as SN65DSI8X in this
document. SN65DSI8X is an MIPI DSI-to-LVDS bridge device that supports video modes in forward
direction. The SN65DSI8X is primarily targeted for portable applications such as tablets and smart phones
that utilize the MIPI DSI video format. The SN65DSI8X can be used between a GPU with DSI output and
a video panel with LVDS inputs.
All three devices share the same pin out and package.
Table 1 lists a summary of the feature sets on these devices.
Table 1. SN65DSI8X Features Summary (1)
Part Name
Description
Max Resolution
SN65DSI83
Single Channel DSI to Single-Link LVDS
Suitable 1366x768/1280x800 60 fps at 24 bpp/18 bpp
SN65DSI84
Single Channel DSI to two Single-Link
LVDS
1920x1200 60 fps at 24 bpp/18 bpp
SN65DSI85
Dual Channel DSI to two Single-Link LVDS 2560x1600 60 fps, 1920x1080p 120 fps at 24 bpp /18 bpp
(1)
2
Each DSI Channel has 4 DSI data lanes + 1 CLK lane. Each LVDS link has 4 data lanes + 1 CLK lane.
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2
Hardware Implementation Guidelines
2.1
Layout Recommendation
2.1.1
Parts and Component Placement
2.1.1.1
VCORE Pin
This pin outputs 1.1 V from the internal voltage regulator. The pin MUST have a 1-µF external capacitor to
GND.
2.1.1.2
REFCLK
A series resistor is recommended near the RECLK source for EMI reduction purpose. If possible, bury the
REFCLK trace in the inner layer, or minimize the trace length from the REFCLK terminal to the CLK
source by placing the source near the SN65DSI8X REFCLK terminal, or do both.
2.1.1.3
Decoupling Capacitors
Decoupling capacitors should be placed near the power plane and power rails for the SN65DSI8X. The
trace length between decoupling capacitors must be minimized to avoid large current loops and trace
inductance. The use of four ceramic capacitors (two 0.1 µF and two 0.01 µF) near the SN65DSI8X is
recommended.
2.1.2
2.1.3
Critical Routes
• DA*P/N and DB*P/N pairs should be routed together with controlled-differential 100-Ω impedance.
Keep away from other high speed signals. Keep lengths within 5 mil of each other. Keep traces on
layers adjacent to ground plane. The number of VIAS should be kept to a minimum. Each pair should
be separated at least by 3 times the signal trace width. Route all differential pairs on the same group of
layers (outer layers or inner layers) if not on the same layer.
• A_Y*P/N and B_Y*P/N pairs should be routed together with controlled differential 100-Ω impedance.
Keep away from other high speed signals. Keep lengths within 5 mil of each other. Keep traces on
layers adjacent to ground plane. The number of VIAS should be kept to a minimum. Each pair should
be separated at least by 3 times the signal trace width. Route all differential pairs on the same group of
layers (outer layers or inner layers) if not on the same layer.
• Ref CLK trace should be routed as short as possible.
Spread Spectrum CLK
The system is allowed to provide the center spread CLK input to the REFCLK or DSI CLK for EMI
reduction purpose. The center spread CLK input to the REFCLK or DSI CLK is passed through to the
LVDS CLK output A_CLKP/N or B_CLKP/N. The spread depth can be 0.5% to 2% with 30 Hz to 50 Hz of
modulation frequency range.
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Hardware Implementation Guidelines
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Purple traces on
this side are LVDS
ChB signals.
Purple traces on
this side are DSI
ChA signals.
Green traces on
this side are LVDS
ChA signals.
Green traces on
this side are LVDS
ChB signals.
Green - TOP Layer, Purple - Layer 3, Blue - Bottom
Figure 1. SN65DSI85 Layout Example
The layer stack up of the board in Figure 1 is as shown in the following:
*6-layer PCB*
Layer 1: Top component side
Layer 2: GND
Layer 3: Signal Route
2.2
Layer4: Power
Layer 5: GND
Layer 6: Bottom component side
RESET Implementation
The SN65DSI8X is reset by controlling the EN terminal (pin B1). The reset implementation defined in the
datasheet should be followed for correct operation of the device after the reset.
Figure 2 and Figure 3 depict the reset timing. User should refer to the datasheet for further details on reset
operation.
Figure 2 shows the EN implementation during cold start when the device is first powered on. Tenable must
be always greater than Tvcc. In case of using the passive reset circuitry, this timing must be insured by
using the correct values of R and C which could vary depending on the ramp up time of the system. The
internal R value on the EN is 200 kΩ.
4
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1.65 V
Vcc
EN
Tvcc
Tenable
Figure 2. Cold Start Vcc Ramp Up to EN
Figure 3 shows the EN implementation while the device is powered on. The following timing must be met
when the SN65DSI8X transitions from a normal operation state to a RESET or SHUTDOWN state while
Vcc remains high.
Vcc
1.65-1.95V
Treset(reset time)
EN
Tdis
Ten
LVDS_A/B_CLK
Figure 3. RESET or SHUTDOWN Timing When Vcc = HIGH
2.3
ADDR
The ADDR determines the least significant bit of the I2C ADDR for the SN65DSI8X. This bit should be
pulled high or low through a resistor depending on the I2C address the system chooses to use for the
SNDSI85. When this pin is pulled low, the device address is 0x2C, high 0x2D.
NOTE: When it is pulled high, it must be tied to the device Vcc such that this pin does not remain
high when the device power is removed.
2.4
LVDS REVERSE Routing Option
The SN65DSI85 allows reversing or swapping the order of the LVDS pins via the register bit control at
address 0x1A per the definitions below.
2.4.1
LVDS Even Odd Swap Option
By setting the 0x1A bit6 EVEN_ODD_SWAP bit in the CSR, the routing of even and odd pixels can be
swapped. When this bit is set to 0 (default), odd pixels are routed to LVDS Channel A (A_Y*P/N) and even
pixels routed to LVDS Channel B (B_Y*P/N). When this bit is set to 1, odd pixels are routed to LVDS
Channel B (B_Y*P/N) and even pixels routed to LVDS Channel A (A_Y*P/N).
2.4.2
LVDS Reverse Pin Order Option
The order of the LVDS pins for LVDS Channel A or Channel B can be reversed by CSR configurations at
the address 0x1A bits 5 CHA_REVERSE_LVDS and bit4 CHB_REVERSE_LVDS.
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References
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Table 2. Channel A LVDS Reverse Pin Order
Pin Number
CHA_REVERSE_LVDS=0 (Default)
CHA_REVERSE_LVDS=1
C8
A_Y0P
A_Y3P
C9
A_Y0N
A_Y3N
D8
A_Y1P
A_CLKP
D9
A_Y1N
A_CLKN
E8
A_Y2P
A_Y2P
E9
A_Y2N
A_Y2N
F8
A_CLKP
A_Y1P
A_Y1N
F9
A_CLKN
G8
A_Y3P
A_Y0P
G9
A_Y3N
A_Y0N
Table 3. Channel B LVDS Reverse Pin Order
Pin Number
2.5
CHB_REVERSE_LVDS=0 (Default)
CHB_REVERSE_LVDS=1
B3
B_Y0P
B_Y3P
A3
B_Y0N
B_Y3N
B4
B_Y1P
B_CLKP
A4
B_Y1N
B_CLKN
B5
B_Y2P
B_Y2P
A5
B_Y2N
B_Y2N
B6
B_CLKP
B_Y1P
A6
B_CLKN
B_Y1N
B7
B_Y3P
B_Y0P
A7
B_Y3N
B_Y0N
Unused DSI Channels or Lanes
Unused DSI input terminals (DA*N/P, DB*N/P) should be left unconnected or driven to LP11 state.
2.6
RSVD Pins
The RSVD1 and RSVD2 are reserved pins. Leave these unconnected for normal operation.
3
References
SN65DSI8X Datasheets (SLLSEB9, SLLSEC1, SLLSEC2)
6
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Reference Schematics
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Reference Schematics
Figure 4 schematics for the SN65DSI8X reference design.
BOARD_1P8V
********Layout Notes*******
Vcc_1P8V
For all differential pairs(DSI and LVDS) in this design follow the guidelines decribed below:
Route together with controlled differential 100ohm impedance and controlled single ended 50ohm
impedance. Keep away from other high speed signals. Keep lengths within 5mil of each other. Keep
traces on layers adjacent to the ground plane. Keep the number of VIAS to minimum. If VIAS are used,
make it symetrical through all signals. Keep diff pairs separated at least by x3 of the trace width.
NO STUBS on the signal path, components should be placed such that the signals can routed in
pass-through manner.
FB1
220 @ 100MHZ
C2
10uF
C3
C4
C5
C6
C7
C8
C9
1.0uF
0.01uF
0.1uF
0.01uF
0.1uF
0.01uF
0.1uF
SN65DSI8X Reference Schematics
1uF is min value.
The number of capacitors and their values may vary depending on the system implementation
Vcore_1P1_Out
Place only if external CLK is
used for LVDSOUT CLK
A/B_CLKP/N. 15-Ohm is
recommended for EMI
reduction but may need to be
adjusted depending on the CLK
waveform.
Vcc_1P8V
BOARD_1P8V
BOARD_1P8V
R2
4.7K
R3
4.7K
C10
1uF
B1
ADDR
A1
RSVD* pins must be left unconnected for normal operation
DSI_A0P
DSI_A0N
DSI_A1P
DSI_A1N
DSI_A2P
DSI_A2N
DSI_A3P
DSI_A3N
DSI_ACLKP
DSI_ACLKN
DSI_B0P
DSI_B0N
DSI_B1P
DSI_B1N
DSI_B2P
DSI_B2N
DSI_B3P
DSI_B3N
DSI_BCLKP
DSI_BCLKN
DSI_A0P
DSI_A0N
DSI_A1P
DSI_A1N
DSI_A2P
DSI_A2N
DSI_A3P
DSI_A3N
DSI_ACLKP
DSI_ACLKN
H3
J3
H4
J4
H6
J6
H7
J7
H5
J5
DSI_B0P
DSI_B0N
DSI_B1P
DSI_B1N
DSI_B2P
DSI_B2N
DSI_B3P
DSI_B3N
DSI_BCLKP
DSI_BCLKN
C2
C1
D2
D1
F2
F1
G2
G1
E2
E1
RESET Impementation
R5
REFCLK
ADDR
SCL
SDA
RSVD1
RSVD2
IRQ
DA0P
DA0N
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
DACP
DACN
A_Y0N
A_Y0P
A_Y1N
A_Y1P
A_Y2N
A_Y2P
A_Y3N
A_Y3P
A_CLKN
A_CLKP
DB0P
DB0N
DB1P
DB1N
DB2P
DB2N
DB3P
DB3N
DBCP
DBCN
B_Y0N
B_Y0P
B_Y1N
B_Y1P
B_Y2N
B_Y2P
B_Y3N
B_Y3P
B_CLKN
B_CLKP
B9
A8
A2
D5
E4
F4
F5
H9
DSI INPUT
H8
B2
EN
LVDS_RefCLK
H1
J1
SCL
SDA
IRQ
C9
C8
D9
D8
E9
E8
G9
G8
F9
F8
FlatChA_Y0N
FlatChA_Y0P
FlatChA_Y1N
FlatChA_Y1P
FlatChA_Y1N
FlatChA_Y1P
FlatChA_Y1N
FlatChA_Y1P
FlatChA_Y1N
FlatChA_Y1P
A3
B3
A4
B4
A5
B5
A7
B7
A6
B6
FlatChB_Y0N
FlatChB_Y0P
FlatChB_Y1N
FlatChB_Y1P
FlatChB_Y1N
FlatChB_Y1P
FlatChB_Y1N
FlatChB_Y1P
FlatChB_Y1N
FlatChB_Y1P
ADDR Impementation
SN65DSI85
RESET/SHTDN
RESET/SHTDN
C1
0.2uF
FlatChA_Y0N
FlatChA_Y0P
FlatChA_Y1N
FlatChA_Y1P
FlatChA_Y2N
FlatChA_Y2P
FlatChA_Y3N
FlatChA_Y3P
FlatChA_CLKN
FlatChA_CLKP
FlatChB_Y0N
FlatChB_Y0P
FlatChB_Y1N
FlatChB_Y1P
FlatChB_Y2N
FlatChB_Y2P
FlatChB_Y3N
FlatChB_Y3P
FlatChB_CLKN
FlatChB_CLKP
LVDS OUTPUT
LVDS_RefCLK
R7
4.7K
Terminate to GND
with a pull-down
resistor if unused
*IMPORTANT*
If REFCLK is to be used, the CLK trace
length between the REFCLK terminal
and the source of the REFCLK shouldbe
kept as short as possble.
NOTE for SN65DSI83 and SN65DSI84
implementation:
- SN65DSI83 implementation: All DB* pins and
B_Y*&B_CLK* pins are NCs.
- SN65DSI84 implementation: All DB* pins and
are NCs.
Vcc_1P8V
Install PU or PD depending
on the I2C Target addr
configuration. DO NOT
INSTALL BOTH.
R4
4.7K
Reset(EN) can be implemented with passive
components as shown or active circuitry. In
case of using passive components, the
values of the RC circuitry need to be
adjusted to make sure the low to high
transition occurs after the Vcc supply has
reached the minimum recommended
operating voltage. For this reason, it is
recommended to USE ACTIVE CIRCUITRY for
better control of the RESET/EN timing.
SCL
SDA
J9
Vcc_1P8V
R1
DNI
25MHz-154MHz
15
H2
GND
GND
GND
GND
GND
GND
GND
GND
RESET/SHTDN
Optional ref CLK
for LVDS Pixel
CLK
Place as close as
possible to CLK source.
Vcore
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
J8
A9
B8
D6
E6
F6
E5
J2
U1
ADDR
ADDR = 1, Slave Addr = 0x2D
ADDR = 0, Slave Addr = 0x2C
ADDR
R6
DNI
Figure 4. SN65DSI8X Reference Schematics
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