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Texas Instruments XIO2221 Implementation Application notes
Application Report
SCPA049 – November 2010
XIO2221 Implementation Guide
Undrea Fields ..................................................................................................................................
ABSTRACT
This document is provided to assist platform designers using the XIO2221 PCI Express to 1394b OHCI
controller. Detailed information can be found in the XIO2221 data manual. However, this document
provides board design suggestions for the various device features when designing in the XIO2221.
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Contents
XIO2221 Typical System Implementation ............................................................................... 2
Power Considerations ...................................................................................................... 3
PCI Express Interface Considerations ................................................................................... 6
1394b Port Interface Considerations ..................................................................................... 8
Miscellaneous Terminal Considerations ................................................................................. 9
Software Considerations .................................................................................................. 10
Board Design Considerations ............................................................................................ 14
Power Management Considerations .................................................................................... 15
Reference Documents .................................................................................................... 16
List of Figures
1
Typical System Implementation ........................................................................................... 2
2
Filter Designs ................................................................................................................ 6
3
PHY to Port Cable Implementation
.....................................................................................
14
List of Tables
1
XIO2221/PCI Express Device Terminal Connection Details .......................................................... 6
2
Terminals Tied to GND ................................................................................................... 10
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XIO2221 Typical System Implementation
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XIO2221 Typical System Implementation
Figure 1 shows a typical implementation of the XIO2221 PCI Express to 1394b OHCI controller. This
solution provides robust PCI Express link to 1394b cable port protocol conversion in a single
semiconductor package. The XIO2221 operates only with the PCI Express link as the primary interface
and the 1394b cable ports as the secondary interface.
Upstream PCI
Express Device
PCI Express
Reference Clock
PCI EXPRESS LINK
SYSTEM SIDE
XIO2221 SIDE
GPIO INTERFACE
XIO2221
Serial
EEPROM
1394b
98.304-MHz
Oscillator
1394b
Port
Figure 1. Typical System Implementation
Either a common differential 100-MHz PCI Express reference clock or an asynchronous single-ended
125-MHz reference clock is supported. Figure 1 illustrates the common 100-MHz reference clock option.
The 1394b core requires the standard 98.304-MHz oscillator as described in the 1394b specification.
The EEPROM can be used to set various configuration registers but is not necessary if those registers are
settable via system software/BIOS.
Eight general-purpose inputs and outputs (GPIO) exist for further system customization.
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Power Considerations
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2
Power Considerations
2.1
1.5-V, 1.95-V, and 3.3-V Digital Supplies
The XIO2221 requires 1.5-V, 1.95-V and 3.3-V digital power supplies.
The 1.5-V terminals are named VDD_15. These terminals supply power to the digital core. The 1.5-V core
allows for a significant reduction in both power consumption and logic switching noise.
The 1.95-V terminals are named DVDD_CORE. These terminals supply power to the PHY digital core.
NOTE: For DVDD_CORE power supply filtering it is recommended that each of the three
DVDD_CORE terminals have 1-µF capacitors to ground placed as close as possible to the
device.
The 3.3-V terminals are named DVDD_33, VDD_33, and VDD_33_AUX and supply power to most of the input and
output cells.
All of these supplies must have 0.1-mF bypass capacitors to VSS (GND) in order for proper operation. The
recommendation is one capacitor for each power terminal.
When placing and connecting all bypass capacitors, high-speed board design rules must be followed.
2.2
1.5-V, 1.95-V, and 3.3-V Analog Supplies
The XIO2221 requires 1.5-V, 1.95-V, and 3.3-V analog power supplies. Because circuit noise on the
analog power terminals must be minimized, the following Pi filters are recommended (See Figure 2).
All of the 1.5-V, 1.95-V, and 3.3-V analog supplies must have 0.1-mF bypass capacitors connected to VSSA
(GND) for proper operation. The recommendation is one capacitor for each power terminal. In addition,
one 1000-pF capacitor per Pi filter is recommended. This 1000-pF capacitor is attached to the device side
of the Pi filter and to VSSA (GND). High-speed board design rules must be followed when connecting
bypass capacitors.
2.3
98.304 MHz Oscillator Power Supply
To minimize induced jitter, the 3.3-V power supply for the 98.304-MHz oscillator should be isolated from
the other 3.3-V supplies. The TI reference design accomplishes this by using a ferrite bead and parallel
1-mF and 0.1-mF capacitors. See TI XIO2221, Reference Schematics. The XIO2221 EVM uses the Siward
Oscillator, part number OSC062100A-98.304-3.3-TS.
2.4
Combined Power Outputs
There are three combined power rails in the XIO2221 that are distributed to the analog circuits, digital
logic, and I/O cells. Each of the three power rails has an output terminal for the external attachment of
bypass capacitors to minimize circuit switching noise. These terminals are named VDD_15_COMB, VDD_33_COMB,
and VDD_COM_IO.
The recommended bypass capacitors for each combined output terminal are 1000 pF, 0.01 mF, and
1.0 mF. When placing these capacitors on the bottom side of the circuit board, the smallest value capacitor
is positioned next to the via associated with the combined output terminal, and the largest value capacitor
is the most distant from the via. The circuit board trace width connecting the combined output terminal via
to the capacitors must be at least 12 to 15 mils wide with the trace length as short as possible.
Other than the three recommended capacitors, no other external components are attached to these
combined output terminals.
2.5
VSS and VSSA GND Terminals
For proper operation of the XIO2221, a unified VSS and VSSA ground plane is recommended. The circuit
board stack-up recommendation is to implement a layer 2 ground plane directly under the XIO2221
device. Both the circuit board vias and ground trace widths that connect the VSS and VSSA ball pads to this
ground plane must be oversized to provide a low-impedance connection.
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Capacitor Selection Recommendations
When selecting bypass capacitors for the XIO2221 device, X7R-type capacitors are recommended. The
frequency versus impedance curves, quality, stability, and cost of these capacitors make them a logical
choice for most computer systems.
The selection of bulk capacitors with low-ESR specifications is recommended to minimize low-frequency
power supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolytic
capacitors. These capacitors typically have ESR specifications that are less than 0.01 Ω at 100 kHz. Also,
several manufacturers sell “D” size surface mount specialty polymer solid aluminum electrolytic capacitors
with ESR specifications slightly higher than 0.01 Ω at 100 kHz. Both of these bulk capacitor options
significantly reduce low-frequency power supply noise and ripple.
2.7
Power-up/Power-down Sequencing
All XIO2221 analog and digital power terminals must be controlled during the power-up and power-down
sequence. During power sequencing, all power rails must remain within 3.6 V to prevent damaging the
XIO2221.
When power cycling the XIO2221, supply sequencing is required to ensure that the output cells have valid
inputs from the core when they are powered up or powered down. The 1.5-V, 1.95-V analog, 1.5-V, and
1.95-V digital power supplies must be applied first when powering up the device and removed last when
powering down the device. Having stable signal levels from the core logic driving the output cells prevents
output driver current and voltage fluctuations when the output cells are powered up or powered down.
For additional power sequencing requirements, please reference the XIO2221 data manual (SCPS171)
and the PCI-Express Card Electromechanical Specification, Revision 1.1.
2.8
Power Supply Filtering Recommendations
To meet the PCI-Express and 1394b OHCI jitter specifications, low-noise power supplies are required on
several of the XIO2221 voltage terminals. The power terminals that require low-noise power include
VDDA_15 and VDDA_33. This section provides guidelines for the filter design to create low-noise power sources.
The least expensive solution for low-noise power sources is to filter existing 3.3-V, 1.95-V and 1.5-V
power supplies. This solution requires analysis of the noise frequencies present on the power supplies.
The XIO2221 has external interfaces operating at clock rates ranging from 100 MHz up to 2.5 GHz. Other
devices located near the XIO2221 may produce switching noise at different frequencies. Also, the power
supplies that generate the 3.3-V, 1.95-V, and 1.5-V power rails may add ripple noise. Linear regulators
have feedback loops that typically operate in the 100-KHz range. Switching power supplies typically have
operating frequencies in the 500-KHz range. When analyzing power supply noise frequencies, the first,
third, and fifth harmonic of every clock source should be considered.
Critical analog circuits within the XIO2221 must be shielded from this power supply noise. The
fundamental requirement for a filter design is to reduce power supply noise to a peak-to-peak amplitude of
less than 25 millivolts. This maximum noise amplitude should apply to all frequencies from 0 Hz to
6.25 GHz.
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The following information should be considered when designing a power supply filter:
1. Ideally, the series resonance frequency for each filter component should be greater than the fifth
harmonic of the maximum clock frequency. With a maximum clock frequency of 1.25 GHz, the third
harmonic is 3.75 GHz and the fifth harmonic is 6.25 GHz. Finding inductors and capacitors with a
series resonance frequency above 6.25 GHz is both difficult and expensive. Components with a series
resonance frequency in the 4-GHz to 6-GHz range are a good compromise.
2. The inductor(s) associated with the filter must have a DC resistance low enough to pass the required
current for the connected power terminals. The voltage drop across the inductor must be low enough
to meet the minus 10% voltage margin requirement associated with each XIO2221 power terminal.
Power supply output voltage variation must be considered as well as voltage drops associated with
any connector pins and circuit board power distribution geometries.
3. The Q versus frequency curve associated with the inductor must be appropriate to reduce power
terminal noise to less than the maximum peak-to-peak amplitude requirement for the XIO2221.
Recommending a specific inductor is difficult because every system design is different and therefore
the noise frequencies and noise amplitudes are different. Many factors will influence the inductor
selection for the filter design. Power supplies must have adequate input and output filtering. A sufficient
number of bulk and bypass capacitors are required to minimize switching noise. Assuming that board
level power is properly filtered and minimal low frequency noise is present, frequencies less than 10
MHz, an inductor with a Q greater than 20 from approximately 10 MHz to 3 GHz should be adequate
for most system applications.
4. The series component(s) in the filter may either be an inductor or a ferrite bead. Testing has been
performed on both component types. When measuring PCI-Express link jitter, the inductor or ferrite
bead solutions produce equal results. When measuring circuit board EMI, the ferrite bead is a superior
solution.
NOTE:
The XIO2221 reference schematics include ferrite beads in the analog power supply filters.
5. When designing filters associated with power distribution, the power supply is a low impedance source
and the device power terminals are a low impedance load. The best filter for this application is a “T”
filter. See Figure 2 for an example T-filter circuit. Some system may require this type of filter design if
the power supplies or nearby components are exceptionally noisy. This type of filter design is
recommended if a significant amount of low frequency noise, frequencies less than 10 MHz, is present
in a system.
6. For most applications a “Pi” filter is adequate. See figure 2 for an example Pi filter circuit. When
implementing a Pi filter, the two capacitors and the inductor must be located next to each other on the
circuit board and must be connected together with wide low-impedance traces. Capacitor ground
connections must be short and low impedance.
7. If a significant amount of high frequency noise (frequencies greater than 300 MHz) is present in a
system, creating an internal circuit board capacitor helps reduce this noise. This is accomplished by
locating power and ground planes next to each other in the circuit board stack-up. A gap of 0.003 mils
between the power and ground planes significantly reduces this high frequency noise.
8. Another option for filtering high-frequency logic noise is to create an internal board capacitor using
signal layer copper plates. When a component requires a low-noise power supply, usually the Pi filter
is located near the component. Directly under the Pi filter, a plate capacitor may be created. In the
circuit board stack-up, select a signal layer that is physically located next to a ground plane. Then,
generate an internal 0.25-inch by 0.25-inch plate on that signal layer. Assuming a 0.006-mil gap
between the signal layer plate and the internal ground plane, this generates a 12-pF capacitor. By
connecting this plate capacitor to the trace between the Pi filter and the component’s power terminals,
an internal circuit board high frequency bypass capacitor is created. This solution is extremely effective
for switching frequencies above 300 MHz.
Figure 2 illustrates two different filter designs that may be used with the XIO2221 to provide low-noise
power to critical power terminals.
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Component
Side
Power Supply
Side
T-Filter Design
Component
Side
Power Supply
Side
Pi-Filter Design
Figure 2. Filter Designs
3
PCI Express Interface Considerations
The XIO2221 has an x1 PCI Express interface that is fully compliant to the PCI Express Base
Specification, Revision 1.0a. The remainder of this chapter describes implementation considerations for
the XIO2221’s primary PCI Express interface.
3.1
Gbps Transmit and Receive Link
The XIO2221 TX and RX terminals attach to the upstream PCI Express device over a 2.5-Gbps
high-speed differential transmit and receive PCI Express x1 Link. The connection details are provided in
Table 1.
Table 1. XIO2221/PCI Express Device Terminal Connection Details
TERMINAL NAME
COMMENTS
XIO2221
UPSTREAM PCI EXPRESS
DEVICE
TXP
RXP
XIO2221’s transmit positive differential terminal connects to the upstream
device’s receive positive differential terminal.
TXN
RXN
XIO2221’s transmit negative differential terminal connects to the upstream
device’s receive negative differential terminal.
RXP
TXP
XIO2221’s receive positive differential terminal connects to the upstream
device’s transmit positive differential terminal.
RXN
TXN
XIO2221’s receive negative differential terminal connects to the upstream
device’s transmit negative differential terminal.
The XIO2221 TXP and TXN terminals comprise a low-voltage, 100-Ω, differentially driven, signal pair. The
RXP and RXN terminals for the XIO2221 receive a low-voltage, 100-Ω, differentially driven, signal pair.
The XIO2221 has integrated 50-Ω termination resistors to VSS on both the RXP and RXN terminals
eliminating the need for external components.
Each lane of the differential signal pair must be ac-coupled. The recommended value for the series
capacitor is 0.1 mF. To minimize stray capacitance associated with the series capacitor circuit board solder
pads, 0402-sized capacitors are recommended.
When routing a 2.5-Gb/s low-voltage, 100-Ω differentially driven signal pair, the following circuit board
design guidelines must be considered:
1. The PCI-Express drivers and receivers are designed to operate with adequate bit error rate margins
over a 20-inch maximum length signal pair routed through FR4 circuit board material.
2. Each differential signal pair must be 100-Ω differential impedance with each single-ended lane
measuring in the range of 50-Ω to 55-Ω impedance to ground.
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3. The differential signal trace lengths associated with a PCI Express high-speed link must be length
matched to minimize signal jitter. This length matching requirement applies only to the P and N signals
within a differential pair. The transmitter differential pair does not need to be length matched to the
receiver differential pair. The absolute maximum trace length difference between the TXP signal and
TXN signal must be less than 5 mils. This also applies to the RXP and RXN signal pair.
4. If a differential signal pair is broken into segments by vias, series capacitors, or connectors, the length
of the positive signal trace must be length matched to the negative signal trace for each segment.
Trace length differences over all segments are additive and must be less than 5 mils.
5. The location of the series capacitors is critical. For add-in cards, the series capacitors are located
between the TXP/TXN terminals and the PCI-Express connector. In addition, the capacitors are placed
near the PCI Express connector. This translates to two capacitors on the motherboard for the
downstream link and two capacitors on the add-in card for the upstream link. If both the upstream
device and the downstream device reside on the same circuit board, the capacitors are located near
the TXP/TXN terminals for each link.
6. The number of vias must be minimized. Each signal trace via reduces the maximum trace length by
approximately 2 inches. For example: if 6 vias are needed, the maximum trace length is 8 inches.
7. When routing a differential signal pair, 45-degree angles are preferred over 90-degree angles. Signal
trace length matching is easier with 45-degree angles and overall signal trace length is reduced.
8. The differential signal pairs must not be routed over gaps in the power planes or ground planes. This
causes impedance mismatches.
9. If vias are used to change from one signal layer to another signal layer, it is important to maintain the
same 50-Ω impedance reference to the ground plane. Changing reference planes causes signal trace
impedance mismatches. If changing reference planes cannot be prevented, bypass capacitors
connecting the two reference planes next to the signal trace vias helps reduce the impedance
mismatch.
10. If possible, the differential signal pairs should be routed on the top and bottom layers of a circuit board.
Signal propagation speeds are faster on external signal layers.
3.2
PCI Express Transmitter Reference Resistor
The REF0_PCIE and REF1_PCIE terminals connect to an external resistor to set the drive current for the
PCI Express TX driver. The required resistor value is 14,532 Ω with a 1% tolerance.
A 14,532-Ω resistor is a custom value. To eliminate the need for a custom resistor, two series resistors
are recommended, a 14,300-Ω 1% resistor and a 232-Ω 1% resistor. Trace lengths must be kept short to
minimize noise coupling into the reference resistor terminals.
3.3
PCI-Express Reference Clock Inputs
The XIO2221 requires an external reference clock for the PCI-Express interface. The PCI Express Base
Specification and PCI Express Card Electromechanical Specification provide information concerning the
requirements for this reference clock. The XIO2221 is designed to meet all stated specifications when the
reference clock input is within all PCI Express operating parameters. This includes both standard clock
oscillator sources or spread spectrum clock oscillator sources.
The XIO2221 supports two options for the PCI Express reference clock: a 100-MHz common differential
reference clock or a 125-MHz asynchronous single-ended reference clock. Both implementations are
described below.
The first option is a system-wide, 100-MHz differential reference clock. A single clock source with multiple
differential clock outputs is connected to all PCI Express devices in the system. The differential connection
between the clock source and each PCI Express device is point-topoint. This system implementation is
referred to as a common clock design.
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The XIO2221 is optimized for this type of system clock design. The REFCLK+ and REFCLK– terminals
provide differential reference clock inputs to the XIO2221. The circuit board routing rules associated with
the 100-MHz differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules
itemized in Section 3.1. The only difference is that the differential reference clock does not require series
capacitors. The requirement is a DC connection from the clock driver output to the XIO2221 receiver input.
Electrical specifications for these differential inputs are included in the XIO2221 data manual. Terminating
the differential clock signal is circuit board design specific, but the XIO2221 design has no internal
50-Ω-to-ground termination resistors. Both REFCLK inputs, at approximately 20 kΩ to ground, are
high-impedance inputs.
The second option is a 125-MHz asynchronous single-ended reference clock. For this case, the devices at
each end of the PCI Express link have different clock sources. The XIO2221 has a 125-MHz single-ended
reference clock option for asynchronous clocking designs. When the REFCLK_SEL input terminal is tied
to VDD_33, this clocking mode is enabled.
The single-ended reference clock is attached to the REFCLK+ terminal. The REFCLK+ input, at
approximately 20 kΩ, is a high-impedance input. Any clock termination design must account for a
high-impedance input. The REFCLK– terminal is attached to a 0.1-mF capacitor. The capacitor’s second
terminal is connected to VSSA. Electrical specifications for this single-ended input are included in the
XIO2221 data manual.
3.4
PCI Express Reset
The XIO2221 PCI Express Reset (PERST ) terminal connects to the upstream PCI Express device’s
PERST output. The PERST input cell has hysteresis and is operational during the main power state. No
external components are required.
See the XIO2221 data manual and PCI-Express Card Electromechanical Specification to fully understand
the PERST electrical requirements and timing requirements associated with power-up and power-down
sequencing. In addition, the data manual configuration register sections identify all register bits that are
reset by PERST.
4
1394b Port Interface Considerations
The XIO2221 has one 1394b cable port that can operate at 100, 200, 400, or 800 Mbps. This port is
compliant with the IEEE Std 1394b-2002, standard. This section describes implementation considerations
for the XIO2221’s 1394b cable port.
• The cable not active (CNA) terminal is an output that reflects the state of the incoming 1394b cable
port bias voltage. If no cable bias voltage is detected by the XIO2221, then this output is asserted high.
If the CNA terminal is not used, then it can be left as a no-connect.
• The cable power status (CPS) terminal is an input that drives an internal comparator for the purpose of
detecting the presence of 1394b cable power. Normally, terminal CPS is connected to the 1394b cable
power source through a 390-kΩ resistor. However, if this detection feature is not used, then CPS
should be connected directly to GND.
• PC2, PC1, and PC0 are the power class programming inputs. On the de-assertion of PERST , these
inputs are sampled and loaded into the power class field in the 1394b PHY base configuration
registers. Since the binary value associated with the power class field is implementation specific, the
system designer must reference the 1394b power class description table in the XIO2221 Data Manual
to determine the appropriate PC2:0 input levels. Each terminal is connected to either GND or VDD_33 to
specify the appropriate power class binary value. This connection may either be direct or through a
weak resistor.
• Terminals R0 and R1 are provided to set the operating current of the cable driver. A 6.34-kΩ ±1%
resistor is required to meet the IEEE Std. output voltage limits. One side of the resistor is connected to
the R0 terminal and the other side of the resistor to the R1 terminal. Signal traces must be short to
minimize noise coupling into the two terminals.
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•
•
TPA0P, TPA0N, TPB0P, TPB0N, and TPBIAS0 comprise the five major terminals associated with
1394b PHY port. TPA0P and TPA0N are the cable A differential signals. TPB0P and TPB0N are the
cable B differential signals. TPBIAS0 provides the 1.86-V nominal bias required for proper 1394a
driver/receiver operation and for active cable connection signaling to the remote node. The 1394b TPA
and TPB differential pairs must follow the same routing guidelines as the PCI Express TX and RX
differential pairs except for the differential impedance requirement of 110 Ω.
The XIO2221 is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal
to provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks
required for transmission and resynchronization of data at the S100 through S800 media data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394a
and less than ±50 ppm for IEEE Std. 1394b. Adjacent PHYs may, therefore, have a difference of up to
200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference
over the maximum packet length. Larger clock variations can cause resynchronization overflows or
underflows, resulting in corrupted packet data.
For the XIO2221, the PCLK output can be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. The frequency of the PCLK output must be within ±50
ppm of the nominal frequency of 98.304 MHz.
The following are some typical specifications for an oscillator used with the XIO2221 to achieve the
required frequency accuracy and stability:
• RMS jitter of 5 ps or less
• RMS phase-noise jitter of 1 ps or less over the range 12 kHz to 20 MHz or higher
• Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ±100 ppm. A device
with ±30-ppm or ±50-ppm frequency tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A device with ±30-ppm or ±50-ppm frequency stability
is recommended for adequate margin.
5
Miscellaneous Terminal Considerations
5.1
GPIOTerminals
There are eight GPIO terminals in the XIO2221. All eight GPIO terminals are 3.3-V tolerant.
One classic PCI configuration register defines the GPIO terminal direction as either an input or an output.
A second register either defines the GPIO output state or reports the GPIO input state. The power-up
default is GPIO input mode. The power-up default signal level for each GPIO terminal is determined by
either an internal active pullup transistor or any externally attached components. Internal active pullup
transistors are present on all GPIO terminals. When a GPIO terminal is configured as an input, the internal
active pullup transistor is enabled. If a GPIO terminal is configured as an output, the internal active pullup
transistor is disabled.
5.2
GRST Terminal
GRST is a global reset terminal that is provided for custom reset requirements. When this input is
asserted low, all registers, state machines, digital logic, and analog circuits are returned to their power-up
default state. This reset is asynchronous to all external reference clock and internal clock domains. The
GRST input buffer has hysteresis and an internal active pullup resistor. This input is powered either by
main power.
During an XIO2221 device power-up from the D3cold power state, there is no requirement to assert this
terminal low. An internal power-up reset function performs an equivalent reset to GRST .
If the system designer has no need for a custom reset, the GRST terminal can simply be left floating. An
internal active pullup resistor will guarantee a non-reset state.
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PHY TESTM and VREG_PD Terminals
The TESTM terminal must be pulled up to DVDD_33 using a 1-kΩ resistor. The VREG_PD terminal can
be connected to GND to enable the internal 1.95-V regulator, this terminal can be pulled up to DVDD_33
using a 1-kΩ resistor to use an external 1.95-V regulator for the 1.95-V device power rails.
5.4
PHY SE and SM Terminals
The SE and SM terminals must be tied to GND.
5.5
5.5 VDD_33_AUX
The VDD_33_AUX terminal should be tied to GND through a 10-kΩ pull-down resistor as the XIO2221
does not support VAUX.
5.6
Reserved Terminals
The XIO2221 has multiple reserved terminals. The recommendation for all reserved terminals is a
no-connect state, with the exception of the following terminals, which should be tied to GND:
Table 2. Terminals Tied to GND
ZAY PACKAGE
RSVD TERMINALS
TIE TO GND
M8
D14
D12
E14
G12
H14
D13
J14
Do not connect reserved terminals to other signals or external components. Doing so may increase power
consumption or cause output driver signal conflicts.
6
Software Considerations
The basic XIO2221 programming model consists of a 1394b OHCI controller with a three-port PHY that
sits behind a PCI Express-to-PCI translation bridge. All operating systems that support this system
configuration properly configure the standard functionality within the XIO2221.
To be more specific, the PCI Express-to-PCI translation bridge supports the classic PCI-to-PCI bridge
programming model with a type 1 PCI bridge header. Also, if the operating system supports revision 1.2 of
the OHCI controller specification and the IEEE standards 1394a-1995 and 1394b-2002, then the 1394b
OHCI controller will be configured properly. All other XIO2221 advanced features default to a disabled
state and do not require configuration register initialization for basic operation.
6.1
Interrupt Configuration
The 1394b OHCI core only generates PCI bus interrupts on INTA . When the 1394b OHCI core asserts or
de-asserts an interrupt, the bridge core asynchronously detects the state change and generates upstream
PCI Express interrupt messages. The PCI Express interface must be link trained and in the L0 link active
state for interrupt messages to be sent upstream. The XIO2221 data manual illustrates the PCI Express
message format for assert and deassert INTA messages.
6.2
Serial EEPROM Interface Configuration
An external serial EEPROM port is provided on the XIO2221 for power-up configuration support. Typically,
the system BIOS will initialize the configuration registers associated with the serial EEPROM feature. But
for custom systems or PCI-Express add-in cards, this feature is provided to automate basic XIO2221
configuration register initialization.
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The registers loaded by the serial EEPROM feature are located in the classic PCI configuration space for
the bridge. For the 1394b controller, both classic PCI configuration registers and OHCI memory-mapped
configuration registers are loaded.
NOTE: The serial EEPROM also loads TI proprietary registers. The data loaded into these
proprietary registers must not be changed from the values specified in the EEPROM register
loading map. Otherwise, the operational state of the XIO2221 is indeterminate.
The SDA terminal provides a basic EEPROM enable or disable option. Upon de-assertion of PERST, the
logic state of this terminal is checked. If a 1b is detected, then the serial EEPROM interface is enabled. A
0b disables the interface. An external pullup or pulldown resistor is required to generate the appropriate
logic state.
Immediately after the detection of a 1b state on the SDA terminal, the XIO2221 performs the following
actions:
1. Bit 3 (SBDETECT) in the serial-bus control and status register is set.
2. Bit 4 (ROMBUSY) in the serial-bus control and status register is set, and a serial EEPROM download
is initiated to device address 1010000b and word address 00h.
3. The EEPROM data byte located in word address 00h is checked. If bit 7 is asserted, then this indicates
an end-of-list indicator, and the serial-bus state machine aborts the download. A 00h value indicates a
valid PCI Express-to-PCI bus bridge function header. EEPROM word address 00h must only be loaded
with 00h, 80h, or FFh. Other byte values must not be used because they may cause configuration
register download errors and leave the XIO2221 in an indeterminate state.
4. After a valid function header is detected, the EEPROM data byte located in word address 01h is read.
This location determines the number of bytes that are downloaded into the bridge configuration
registers and must equal 1Eh.
5. The starting EEPROM word address is 02h, and the ending address is 1Fh. While downloading the
1Eh data bytes, each byte is loaded into the specified bridge configuration register. The XIO2221 data
manual includes an EEPROM register loading map.
6. When the bridge function download is finished, the next EEPROM data byte is checked for a valid
1394b OHCI function header. If a 01h value is detected, then the EEPROM download continues. If
bit 7 is asserted, then this indicates an end-of-list indicator and the serial-bus state machine aborts the
download. EEPROM word address 20h must only be loaded with 01h, 80h, or FFh. Other byte values
must not be used because they may cause configuration register download errors and leave the
XIO2221 in an indeterminate state.
7. The next EEPROM data byte is checked for the length of the 1394b OHCI download. The length
information must equal 18h.
8. The starting EEPROM word address is 22h and the ending address is 39h. While downloading the 18h
data bytes, each byte is loaded into the specified 1394b OHCI configuration register.
9. The last data byte at word address 3Ah is checked for a valid end-of-list indicator byte. This data byte
must equal 80h.
10. When the serial EEPROM interface state machine is finished, the ROMBUSY status bit is deasserted.
If any errors are detected during the download procedure, then bit 0 (ROM_ERR) in the serial-bus
control and status register is set. If ROM_ERR status is asserted, then the state of any configuration
register targeted by the EEPROM download is unknown.
11. Additional detail is provided in the XIO2221 data manual related to the serial EEPROM function and
configuration register download map.
6.3
BIOS Considerations
This section provides a high-level overview of the registers that need to be programmed by the BIOS upon
initialization of the XIO2221. In general, the only registers that must be programmed for proper operation
within a Windows operating system are those registers that are EEPROM loadable. Other registers may
need to be changed according to system implementation. Microsoft provides the following reference
documents concerning architecture and driver support for PCI and PCI Express devices in Windows:
http://www.microsoft.com/whdc/system/bus/pci/default.mspx.
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Software Considerations
6.3.1
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6.3.2
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Bridge Classic PCI Configuration Registers
Primary Bus Number Register (PCI offset 18h) – This register indicates the bus number of the PCI
bus segment that the primary PCI Express interface is connected to. The bridge uses this information
to determine how to respond to a type 0 configuration transaction. The register default is 00h.
Secondary Bus Number Register (PCI offset 19h) – This register indicates the bus number of the
PCI bus segment that the secondary PCI interface is connected to. The bridge uses this information to
determine how to respond to a type 1 configuration transaction. The register default is 00h.
Subordinate Bus Number Register (PCI offset 1Ah) – This register indicates the bus number of the
highest number PCI bus segment that is downstream of the bridge. For the XIO2221, the subordinate
bus number and secondary bus number registers must be equal. The register default is 00h.
Subsystem Vendor ID and Subsystem ID Registers (PCI offsets 84h and 86h) –These registers
are used for subsystem and option card identification purposes. Typically, these registers contain the
OEM vendor ID and an OEM identified designator. These fields can be programmed using the
EEPROM or BIOS. If using BIOS, then the subsystem access register at offset D0h is written to update
the subsystem vendor ID and subsystem ID registers.
GPIO Control and Data Registers (PCI offsets B4h and B6h) – These register determine the
direction of the GPIO terminals and set the default state for all GPIO outputs. The initialization state for
these registers is system architecture dependent. The control register default is GPIO input mode.
General Control Register (PCI offset D4h) – This register controls various bridge power
management and interface operation specific functions that are fully described in the XIO2221 data
manual. This register can be programmed using the EEPROM or BIOS.
Arbiter Control (PCI offset DCh) –This register controls the internal classic PCI Bus arbiter function
and can be programmed using the EEPROM or BIOS.
1. EEPROM word address 0Dh bit 7 maps to arbiter control register bit 7 and controls the bus parking
option.
2. EEPROM word address 0Dh bit 6 maps to arbiter control register bit 6 and controls the priority tier
for the bridge.
3. EEPROM word address 0Dh bits 5-1 map to arbiter control register bits 5-1.
4. These reserve bits must be set to 00000b.
5. EEPROM word address 0Dh bit 0 maps to arbiter control register bit 0 and controls the priority tier
for the 1394b OHCI core.
Arbiter Request Mask (PCI offset DDh) –This register controls the internal classic PCI bus arbiter
function and can be programmed using the EEPROM or BIOS.
1. EEPROM word address 0Eh bit 7 maps to arbiter mask register bit 7 and controls the arbiter
timeout option. A value of 0b is recommended.
2. EEPROM word address 0Eh bit 6 maps to arbiter mask register bit 6 and controls the automatic
request mask option.
3. EEPROM word address 0Eh bits 5-1 map to arbiter mask register bits 5-1. These reserve bits must
be set to 00000b.
4. EEPROM word address 0Eh bit 0 maps to arbiter mask register bit 0 and controls masking the PCI
bus request signal for the 1394b OHCI core.
1394b OHCI Classic PCI Configuration Registers
Subsystem Vendor ID and Subsystem Device ID Registers (PCI offsets 2Ch and 2Eh) – These
registers are used for subsystem and option card identification purposes. Typically, these registers
contain the OEM vendor ID and an OEM device ID. These fields can be programmed using the
EEPROM or BIOS. If using BIOS, then the subsystem access register at offset F8h is written to update
the subsystem vendor ID and subsystem device ID registers.
• MIN_GNT Register (PCI offset 3Eh) – This register assigns a minimum latency timer value to the
OHCI controller and can be programmed using the EEPROM or BIOS. If the EEPROM download
option is selected, then only the least significant 4 bits of the MIN_GNT register are updated. EEPROM
word address 22h bits 3-0 map to MIN_GNT register bits 3-0. If the BIOS load option is selected, then
the MIN_GNT register power-on default equals 02h until the register is updated.
• MAX_LAT Register (PCI offset 3Fh) – This register assigns a maximum arbitration priority level to the
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Software Considerations
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6.3.3
OHCI controller and can be programmed using the EEPROM or BIOS. If the EEPROM download
option is selected, only the least significant 4 bits of the MAX_LAT register are updated. EEPROM
word address 22h bits 7–4 map to MAX_LAT register bits 3-0. If the BIOS load option is selected, then
the MAX_LAT register power-on default equals 04h until the register is updated.
Miscellaneous Control Register (PCI offset F0h) – Bits 9–7, 4, and 2–0 within this register may be
downloaded from the EEPROM or loaded by the BIOS. Miscellaneous control register bits 9 and 8 are
loaded from EEPROM word address 34h bits 1 and 0. While EEPROM word address 33h bits 7, 4, and
2–0 map to miscellaneous control register bits 7, 4, and 2–0.
1. Bits 9–8: MR_ENHANCE controls read command behavior for transactions greater than two data
phases.
2. Bit 7: PM_VERSION_CTRL selects power management 1.1 or 1.2 compliance.
3. Bit 4: DIS_TGT_ABT selects either signaling target abort or returning indeterminate data equal to
FFh.
4. Bit 2: DISABLE_SCLKGATE is a test mode for enabling or disabling the hardware autogating of the
internal PHY clock to the PCI bus clock for the 1394b core. This is a test feature only and must be
cleared to 0b.
5. Bit 1: DISABLE_PCIGATE is a test mode for enabling or disabling the hardware autogating of the
internal OHCI clock to the PCI bus clock for the 1394b core. This is a test feature only and must be
cleared to 0b.
6. Bit 0: KEEP_PCLK has no effect in the XIO2221. The recommended default value is 0b.
Link Enhancement Control Register (PCI offset F4h) – Bits 15–12, 7, 2, and 1 within this register
may be downloaded from the EEPROM or loaded by the BIOS. Link enhancement control register bits
15–12 are loaded from EEPROM word address 32h bits 7–4. While, EEPROM word address 27h bits
7, 2, and 1 map to link enhancement control register bits 7, 2, and 1.
1. Bit 15: DIS_AT_PIPELINE enables or disables AT pipelining.
2. Bit 14: ENAB_DRAFT Enables some features beyond the OHCI 1.1 specification.
3. Bits 13–12: ATX_THRESH defines the initial AT FIFO threshold value.
4. Bit 7: ENAB_UNFAIR controls responding to requests with priority arbitration.
5. Bit 2: ENAB_INSERT_IDLE Inserts an idle state so the link waits one clock cycle before driving
CTL and DATA lines.
6. Bit 1: ENAB_ACCEL enables or disables 1394b-2000 standard acceleration enhancements.
1394b OHCI Memory Mapped Configuration Registers
GUID ROM Register (OHCI offset 04h) – The mini-ROM field, bit 7-0, if not equal to 00h, indicates the
starting location of the EEPROM mini-ROM data. This field is loaded only by the EEPROM.
• GUID High and Low Registers (OHCI offsets 24h and 28h) – These registers represent the 64-bit
global unique ID, which maps to the third quadlet and chip ID low information in the bus info block.
These registers may be downloaded from the EEPROM or loaded by the BIOS.
• Host Controller Control Register (OHCI offset 50h) – Bit 23, PROGRAM PHY ENABLE, informs
software that the 1394a link and PHY layers are configured for 1394a-2000 enhancements. This bit
may be downloaded from the EEPROM or loaded by the BIOS. For the EEPROM download option,
word address 27h bit 6 maps to the host controller control register bit 23.
•
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13
Board Design Considerations
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7
Board Design Considerations
7.1
PHY Port Cable Connection
Figure 3 illustrates the typical TP cable connections.
XIO2221
CPS
400 kW
CABLE
POWER
PAIR
1 mF
TPBIAS
56.2 W
56.2 W
270 pF
TPA +
CABLE
PAIR
A
TPA -
CABLE PORT
TPB+
CABLE
PAIR
B
TPB-
56.2 W
270 pF
56.2 W
5.1 kW
1000 pF
.01 mF
1 MW
The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 270-pF capacitor
is recommended.
Figure 3. PHY to Port Cable Implementation
7.2
Crystal Selection
The XIO2221 is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to
provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks
required for transmission and resynchronization of data at the S100 through S800 media data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394.
Adjacent PHYs may, therefore, have a difference of up to 200 ppm from each other in their internal clocks,
and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock
variations may cause resynchronization overflows or underflows, resulting in corrupted packet data.
For the XIO2221, the PCLK output may be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a
non-1394b LLC, the frequency of the PCLK output must be within ±100 ppm of the nominal frequency of
49.152 MHz. When operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output
must be within ±100 ppm of the nominal frequency of 98.304 MHz.
The following are some typical specifications for an oscillator used with the XIO2221 from TI to achieve
the required frequency accuracy and stability:
• RMS jitter of 5 picoseconds or better
• RMS phase noise jitter of 1 pico second or less over the range 12 kHz to 20 MHz or better
• Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ±100 ppm. A device
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Power Management Considerations
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•
with ±30 ppm or ±50 ppm frequency tolerance is recommended for adequate margin.
Frequency stability (over temperature and age): A device with ±30 ppm or ±50 ppm frequency stability
is recommended for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm,
and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the oscillator alone. Aging also contributes to the frequency variation.
It is strongly recommended that part of the verification process for the design is to measure the frequency
of the PCLK output of the PHY. This should be done with a frequency counter with an accuracy of six
digits or better.
8
Power Management Considerations
8.1
Active State Power Management Information
The PCI Express interface on the XIO2221 has the ability to automatically reduce power when there is no
queued bus activity. Once this feature is enabled by software, the XIO2221 device automatically
transitions into and out of a low-power state. The XIO2221 supports both the L0’s and L1 active state
power management (ASPM) requirements.
In the PCI Express link capabilities registers, two 3-bit exit latency fields specify the latency time required
for the bridge to transition from either the L0’s or L1 state back to the L0 state. In the PCI Express device
capabilities register, two 3-bit acceptable latency fields specify the maximum latency time that the bridge
will tolerate for the attached upstream PCI Express device to transition from either the L0’s or L1 state
back to the L0 state. The acceptable latency fields are an indirect measure of the bridge’s internal
buffering.
Power management software uses the reported acceptable latency number to compare against the exit
latencies reported by all components physically located on the PCI-Express link between the Bridge and
the Root Complex to determine whether ASPM entry can be used with no significant impact to system
performance.
8.2
PCI Bus Power Override Information
System software has the ability to manually reduce power on the secondary PCI bus using the bridge’s
power override feature. During system initialization, XIO2221 configuration registers must be loaded with
system specific power information and power override instructions. After this initial setup, the PCI Express
set slot power limit message may be used to either enable or disable the power override feature.
During system initialization the following configuration register fields are loaded. These fields are loaded
by either the BIOS or serial EEPROM.
1. The general control register contains MIN_POWER_SCALE and MIN_POWER_VALUE fields that are
loaded with the power information associated with the XIO2221.
2. The general control register contains a POWER_OVRD field that is loaded with the secondary PCI bus
power override option.
3. The power override option is initialized associated with responding to all transactions with unsupported
request except for configuration transactions and set slot power limit messages.
After the previously described initialization procedure, the PCI Express set slot power limit message may
be used to either enable or disable the power override feature. If the scale and value power information in
the PCI Express message is less than the general control register SCALE and VALUE fields, then the
power override feature is enabled. If the scale and value power information in the PCI Express message is
equal to or greater than the SCALE and VALUE fields, then the power override feature is disabled.
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Reference Documents
9
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Reference Documents
1. PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
2. PCI Express Base Specification, Revision 1.1
3. PCI Express Card Electromechanical Specification, Revision 1.1
4. PCI Local Bus Specification, Revision 2.3 and 3.0
5. PCI-to-PCI Bridge Architecture Specification, Revision 1.1
6. PCI Bus Power Management Interface Specification, Revision 1.1 and 1.2
7. 1394 Open Host Controller Interface Specification (Release 1.2)
8. IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995)
9. IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000)
10. IEEE Standard for a High Performance Serial Bus—Amendment 2 (IEEE Std 1394b-2002)
11. P1394b Draft Standard for High Performance Serial Bus (Supplement)
12. PCI Mobile Design Guide, Revision 1.1
13. ExpressCard Standard, Release 1.0 and 1.1
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