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Texas Instruments TVP5154A PCB Layout lines Application notes
Application Report
SLEA082 – June 2010
TVP5154A PCB Layout Guidelines
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TVP5154A PCB Layout Guidelines
We recommend using at least four layers in the PCB layout to ensure proper isolation between the
signals, the power supplies and the grounds. We typically use the following layer stack in our EVM design:
1.
2.
3.
4.
Top
Internal 1
Internal 2
Bottom
Signal layer
Split ground plane layer
Power plane layer
Signal layer
The Top and Bottom layers are reserved for signals. The Internal 2 layer is a power plane where all power
supplies are assigned to their own area or region within the layer.
The Internal 1 layer is considered a split ground plane. The analog and digital areas of the TVP5154 EVM
are isolated throughout the board by using a split of a 30mil trace between the regions. The analog and
digital areas of the TVP5154 EVM are then connected via ferrite beads as close to the power source as
possible. This helps minimize the coupling of digital noise into the analog signals and vice versa.
Layout Recommendations
The following are only PCB layout recommendations based on methods commonly used in our EVMs:
1. Maintain good insulation between the four channels of TVP5154A to minimize introduction of crosstalk.
2. Keep digital and analog signals away from crystal on every layer.
3. While using one ground plane, we do recommend using a split plane to isolate the analog and digital
ground planes underneath the analog and digital supply voltages.
4. Do not route any signals or create a signal layer within the ground plane or the power plane.
5. Be sure that the power planes are the same size or smaller than their respective split ground planes.
6. Do not overlap the analog power plane with the digital ground plane and vice versa.
7. Do not place analog areas too close to the clock domain areas.
8. Do not cross another signal with the analog trace. If necessary, signals must be perpendicular.
9. Do not place digital signals in the analog areas.
10. Avoid long traces for analog signals and use of guard (ground) trace is recommended.
11. Make the length of the digital trace for data and clock as equal as possible.
12. Place decoupling capacitors close to the power pins of the ICs. Typically, 0.1µF capacitors are used.
13. See Figure 1 for recommended GND split.
SLEA082 – June 2010
TVP5154A PCB Layout Guidelines
Copyright © 2010, Texas Instruments Incorporated
1
128
PDN
XOUT
www.ti.com
123 12
2
97
96
1
12mm
12mm
Exposed
Thermal Pad
Recommended
Thermal Land
AGND
DGND
65
32
64
TMS
AGND
33 34 35 36
Insert
Figure 1. Split Ground Planes (TQFP Package)
2
TVP5154A PCB Layout Guidelines
SLEA082 – June 2010
Copyright © 2010, Texas Instruments Incorporated
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