Texas Instruments | SCANSTA101 | Application notes | Texas Instruments SCANSTA101 Application notes

Texas Instruments SCANSTA101 Application notes
SCANSTA101
Literature Number: SNLA198
SCANSTA101 Quick Reference
Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x11
0x13
0x15
0x17
0x19
Register
Start
Status
Interrupt Control
Interrupt Status
Setup
Clock Divider
LFSR Exponent
LFSR LSB Seed
LFSR MSB Seed
LFSR LSB Result
LFSR MSB Result
Index
Vector Index
Header/Trailer Index
Macro Index
Sequencer Index
Bridge Support
Active Bits
5
10
8
8
8
6
3
16
16
16
16
16
16
16
16
16
16
Reset Value
0x0000
0x0000
0x0000
0x0000
0x0043
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Memory Map
R/W
Address
0x0D
0x0E
0x0F
0x10
0x12
0x14
0x16
0x18
0x1A
Function
TDO_SM
TDI_SM
Expected
Mask
Vector 1
Vector 2
Vector 3
Vector 4
Data header
Data trailer
Instruction header
Instruction trailer
Base
Address
(Long
Words)
0x00
0x1C0
0x380
0x540
0x700
0x700
0x700
0x700
0x708
0x728
0x748
0x768
0x788 to
Macro 1 to Macro 16
0x797
Sequencer
0x798
Scan Bridge
0x7B8
support
Long Word
Index
Index
Register
0x000 to 0x1BF
0x000 to 0x1BF
0x000 to 0x1BF
0x000 to 0x1BF
0x0 to 0x1
0x2 to 0x3
0x4 to 0x5
0x6 to 0x7
0x00 to 1x1F
0x20 to 0x3F
0x40 to 0x5F
0x60 to 0x7F
0x0C
0x0C
0x0C
0x0C
0x0 to 0xF
0x15
0x00 to 0x1F
0x17
0x00 to 0x3F
0x19
0x11
0x13
Vector Structure
Macro Type
The vector is two long words (64 bits) long.
Macro type is set by bits 0x11:0x10 in the macro structure.
Bits
Function
Comment
Maximum of 2 long words or
4 Gbits
0 to 255 (only macros 0 to 15 are
0x20 to 0x27 Macro number
valid)
0x28 to 0x2E Reserved
Reserved
Preloaded data / load Preloaded – 1
0x2F
on the fly
load on the fly – 0
0x30 to 0x3F Reserved
Reserved
0x00 to 0x1F
Data length (long
words)
17
Macro Structure
Macro controls the TMS_SM line. The macro is 1 long word
(32 bits) long.
Bits
Function
0x00 to 0x06 First 7 TMS_SM bits
0x07
TMS_SM loop bit
TMS_SM bit at
0x08
terminal count
0x09 to 0x0F Last 7 TMS_SM bits
0x10 to 0x11 Macro type bits
0x12 to 0x14 Header/trailer usage
Macro structure bit
0x15
7 enable
Macro structure bit
0x16
8 enable
Sync bit support
0x17
enable
Pre-shift TCK_SM
0x18 to 0x1A
count
Post-shift TCK_SM
0x1B to 0x1D
count
0x1E
Use mask
0x1F
Compare
Comment
Most significant bits are shifted out
Loop bit for SHIFT or BIST macro
Output at terminal count for SHIFT
macro
Least significant bits are shifted out
See macro type table
See header/trailer usage table
Ignored for SHIFT macros
Ignored for SHIFT macros
Sync bit length in setup register
Count of bits 0x00 to 0x06 to be
used
Count of bits 0x09 to 0x0F to be
used
Use mask – 1
Compare all bits – 0
Compare TDI_SM to expected
Bit
0x11
Bit
0x10
0
0
0
1
1
0
1
1
Macro
Type
Comment
Loop-on-loop bit for vector count –
BIST
no data
Loop-on-loop bit for vector count –
SHIFT
data from TDO_SM memory
Loop-on-loop bit for vector count –
SHIFT w /
data from TDO_SM memory – data
capture
to TDI_SM memory
STATE
No loop – no data
Header/Trailer Usage
A macro can call out an instruction shift or a data shift, but not
both.
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Function
Ignore headers and trailers
Use instruction header
Use instruction trailer
Use instruction header and trailer
Use data header
Use data trailer
Use data header and trailer
Reserved
Header/Trailer Structure
The headers and trailers are 32 long words (1024 bits) long
Bits
0x00 to 0x1F
0x20 to 0x3FF
Function
Comment
Must be > 0 if use header/trailer
Data length (bits)
bits are set in macro
Header/trailer data Max 922 bits
SCANSTA101 Quick Reference
Sequencer Structure
Bits
Function
Sequence repeat
count
Vector repeat count
Vector number
Vector repeat count
and vector number
Vector repeat count
Vector number
0x00 to 0x1F
0x20 to 0x2F
0x30 to 0x3F
..x.. - ..x..
0x3E0 to 0x3EF
0x3F0 to 0x3FF
Start Register
Comment
Max of 255
First vector
First vector
Repeat for each vector to be
used in sequence
Vector 255 (if used)
Vector 255 (if used)
Scan Bridge Support Structure
Only Mode Register 0 in the Scan Bridge is used.
Bits
Function
0x00 to 0x0F
0x10 to 0x17
0x18 to 0x1F
0x20 to 0x27
0x28 to 0x2F
Number levels
Scan Bridge address
Scan Bridge LSPs
Scan Bridge address
Scan Bridge LSPs
Scan Bridge address
..x.. - ..x..
and LSPs
0x7F0 to 0x7F7 Scan Bridge address
0x7F8 to 0x7FF Scan Bridge LSPs
Comment
Levels of Scan Bridge support
Level 0
Level 0
Level 1
Level 1
Additional hierarchical levels
Level 125 (if used)
Level 125 (if used)
Use Mask/Compare
Use mask/compare is set by bits 0x1F:0x1E in the macro structure.
Bit 0x1F
Bit 0x1E
Description
0
X
1
0
1
0
Do not compare
Compare with mask
Compare without mask
National Semiconductor
2900 Semiconductor Drive
Santa Clara, CA 95051
1 800 272 9959
Mailing address:
PO Box 58090
Santa Clara, CA 95052
Visit our website at:
national.com
For more information,
send email to:
support@nsc.com
To begin scan operations, write the start register with a valid
vector number.
Bits
Type
2:0
RW
7:3
RO
8
12:9
13
15:14
RW
RO
RW
RO
Field
Use vector <2:0> - only vectors 1
to 4 are valid
Reserved for future vector
expansion
Use sequencer (preloaded data)
Reserved
Onboard memory BIST
Reserved
Setup Register
Bits
Type
Field
1:0
RW
2
RW
3
4
5
6
9:7
11:10
14:11
15
RW
RW
RW
RW
RW
RW
RO
RW
Test loop back
Reset – synchronous processor-commanded
reset
TRST – Scan Master test reset
Scan Bridge support initiate/release
Debug mode
Default TDO value on BIST or STATE macro
Sync-bit length <9:7>
TDO_SM control (use bit 6)
Reserved
16/32-bit mode
Status Register
Write to status register only for test and debug. Disable writes
to register during normal operation.
Bits
Type
Field
2:0
7:3
8
9
10
11
12
13
14
15
RW
RO
RW
RW
RW
RW
RW
RW
RO
RW
Using vector <2:0>
Reserved for vector expansion
Using sequencer
TDI status half-full
TDI status full
TDO status empty
TDO status half-empty
Memory BIST result
BIST running
Results of compare (1 = match)
Interrupt Control/Status Registers
Control register enables interrupts. Status register reports
interrupt status.
Bits
Type
Field
2:0
7:3
8
9
10
11
12
15:13
RW
RO
RW
RW
RW
RW
RW
RO
Vector <2:0> interrupt
Reserved for vector expansion
Sequencer interrupt
TDI half-full interrupt
TDI full interrupt
TDO empty interrupt
TDO half-empty interrupt
Reserved
Pin Descriptions
Pin Name
I/O
Description
D(15:0)
A(4:0)
SCK
INT
OE
DTACK
R/W
STB
CE
RST
TDO
TDI
TMS
TCK
TRST
TDI_SM
TDO_SM
TMS_SM
TCK_SM
TRST0_SM
TRIST_SM
I/O
I
I
O
I
O
I
I
I
I
O
I
I
I
I
I
O
O
O
O
O
Bidirectional data bus
Address bus
System clock
Interrupt output
Output enable
Data transfer handshake
Processor read/write
Data transfer handshake
Chip-enable data transfer handshake
Asynchronous reset
TDO for SCANSTA101 TAP
TDI for SCANSTA101 TAP
TMS for SCANSTA101 TAP
TCK for SCANSTA101 TAP
TRST for SCANSTA101 TAP
Scan Master test data input
Scan Master test data output
Scan Master test mode select
Scan Master test clock output
Scan Master test reset output
Indicates TDO_SM is TRI-STATE®
© National Semiconductor Corporation, January 2010. National, , and TRI-STATE are registered trademarks of National Semiconductor. All other product names are trademarks or registered trademarks of their respective holders. All rights reserved.
540121-001
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising