Texas Instruments | Powering electronics from the USB port | Application notes | Texas Instruments Powering electronics from the USB port Application notes

Texas Instruments Powering electronics from the USB port Application notes
Power Management
Texas Instruments Incorporated
Powering electronics from the USB port
By Robert Kollman, Senior Applications Manager, Power Management, DMTS,
and John Betten, Applications Engineer, Member Group Technical Staff
quiescent current to a total of 500 µA for a low-power
Introduction
The USB interface can provide power to low-power
peripherals but must adhere to the USB 2.0 specification
(Reference 1). Table 1 provides an overview of the
requirements placed on the peripheral equipment. The
host equipment provides a 5-V supply capable of, in the
worst case, only 2.25 W of power. In some cases, this is
clearly not enough for the peripheral, and an alternate
power source such as a wall adapter or off-line power
supply is used. In other cases, 2.25 W is much more than
is needed; and low-cost, linear regulators can be used to
generate the supply voltages for the peripherals. However,
in many cases this power limit necessitates the use of
higher-efficiency power-supply designs and complicates
the system trade-offs of cost, efficiency, and size. This
article discusses these issues.
device and 2.5 mA for a high-power device. It often
requires the use of switches to power down portions of
the peripheral’s electronics.
The USB 1.0 specification has been active since its
release in November 1995. Products that were delivered to
the 1.0 specification had no official logo associated with
them. Many times the products did not fully meet the
current-limit requirements, which usually was not a
problem with the product connected to a PC. However,
problems did arise when there were multiple products
connected in a hub arrangement. With the release of the
2.0 specification, certified products will be marked with a
logo. The certification promises to be more rigorous, and
designers should expect to meet the requirements of the
new specification.
Inrush limit and power segmentation
Table 1. USB power requirements at a glance
PARAMETER
Low-power device
Voltage
High-power device
Maximum quiescent
Low-power device
current
Maximum low-power current
Maximum high-power current
Maximum power draw
Maximum input capacitor
Maximum inrush
REQUIREMENT
4.4 to 5.25 V
4.75 to 5.25 V at
upstream connector
500 µA
100 mA
500 mA
2.25 W
10 µF
50 µC
Another unique requirement of the USB power interface
is the different current draws allowed. When a device is
first connected to the USB, its bypass capacitor could be
charged abruptly and create a glitch on the host equipment
supply. The USB specification resolves this problem by
limiting the initial power surge in two ways. The peripheral
device is allowed only a small (<10-µF) bypass capacitor,
and the charge drawn from the bus is limited to 50 µC
over a specified time. Larger capacitors can be used if
inrush limiting is provided. Once the USB is connected,
there are further limits on current draw. The host first
recognizes the peripheral as low-power, allowing it to draw
less than 100 mA of current. The peripheral can ask the
host to recognize it as a high-power device in a process
called “enumeration.” Once enumeration is completed and
permission is granted, the allowed peripheral current is
increased to 500 mA. The USB spec also includes a suspend
mode that supports remote wake-up. This mode limits
There are two possible configurations for USB products—
a single peripheral connected directly to a host, or a set
of peripherals connected through hubs to the host. For a
single peripheral, the current-limiting requirements usually
are not an issue unless a large input capacitor is placed
across the power-supply voltage for hold-up. If hubs are
used, current limiting will definitely be required due to the
unknown nature of the peripherals that will be plugged
into the hub.
The current limits can be implemented in two manners,
one using discrete power devices with external control
circuits, and the other with the switches integrated into
the controllers. In higher-power applications, the discrete
approach usually yields a lower-cost solution. However, in
lower-power applications, an integrated approach is very
attractive. With the low voltages and currents involved in
the USB, a number of manufacturers are developing ICs
specifically targeted for these markets. Figure 1 on the
next page presents a typical circuit. The first output is
an adjustable linear regulator that can be configured for
0.9- to 3.3-V output, which powers the hub controller and
other electronics. The second is a switched output that
powers the peripherals connected to the hub. The integrated approach provides a number of desirable features.
The device is much more rugged than a discrete approach
because a thermal limit monitors the pass-element
temperature and shuts down if an over-temperature is
detected. Two-level current limiting is provided in the
switch to prevent glitching of the host power bus. Initial
power-up current is limited to 100 mA until the output
reaches 93% of the input voltage; then, once the USB
controller is enumerated, the current limit is raised to
500 mA, typical of the high-power peripherals.
28
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Power Management
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Figure 1. Internal switch power segmentation and limiting
U1
TPS2140PWP
Bus
Power
2
+
C1
4.7 µF
3
4
5
6
7
SWPLDN
SWIN
SWOUT
SWIN
SWOUT
LDOIN
LDOOUT
SWENA
LDOPLDN
LDOENA
ADJ
GND
LDOPG
14
Power
to Other
Peripherals
13
12
C3
0.1 µF
11
+
C4
4.7 µF
10
9
8
R2
332 kΩ
15
C2
0.1 µF
SWPG
PWP
1
Switch
Enable
R1
100 kΩ
C6
0.1 µF
+
C5
4.7 µF
Power
to Hub
Control
Table 2. Power-management options
POWER
MANAGER
IMPLEMENTATION
Internal switch
External switch
SWITCH
RESISTANCE
(mΩ)
100
50
CIRCUIT AREA
(in2)
0.30
0.5
Table 2 compares the two approaches, internal versus
external switches or pass elements. The pass elements
have higher resistance in the internal switch approach,
which occupies less than 60% of the external switch
approach. However, the silicon die area is more costly in
the internal switch because more mask levels are involved
in the IC’s device structure than in a simple MOSFET.
Typically, the IC will use over 20 mask levels compared
with 8–10 levels of the MOSFET. The higher level of integration eliminates at least two semiconductor packages
and the resulting poor interconnect efficiency. In addition,
the higher level of integration provides a higher reliability
as bond wires and solder joints are eliminated. Reliability
is further enhanced with the over-temperature protection
of the internal switch. With the external switch, there is
no cost-effective method to measure MOSFET temperature to protect it from shorted loads. Current foldback and
power cycling techniques can help but do not provide the
robustness of the thermal shutdown. The last column of
the table presents a cost comparison between the two
approaches. The costs are almost the same and would
bear a closer examination on a particular requirement.
Generally, the reason the costs are so close is that the
OVERTEMPERATURE
PROTECTION
Yes
No
OVERALL
RELATIVE COST
(%)
80
100
external switch approach uses multiple semiconductor
packages compared with the single package of the integrated switch. Each of the packages has its own overhead
of assembly and test, making the overall system-level costs
about equivalent.
Powering low-voltage digital electronics
Generating low voltages, such as 3.3 V, from the USB can
be done in several ways. Regardless of the configuration
used, the output current for a 3.3-V output is limited to
0.65 A (assuming 95% efficiency) due to the 2.25-W input
power limitation. The options to provide these lower voltages include linear regulators, switching power supplies,
and charge pumps. Within switching power supplies, there
are two further subgroups, synchronous and conventional.
The synchronous is more efficient and costly and will be
used to get as much power from the USB as possible.
The linear regulator is the lowest-cost and highestdensity option for generating lower voltages from the 5-V
USB. When there is no power issue, it will be the circuit
of choice. However, when power becomes an issue,
switching regulators can more efficiently power the
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peripheral. Figure 2 shows one of the lowest-cost buck
switching regulator options available. In this circuit, the
switching of the FET, Q2, is controlled to “buck” the
average voltage presented to the output filter, which then
smooths the switching waveform. The drawback of this
circuit is that the lack of controller integration requires an
external FET and drive circuit, which makes the circuit
relatively large. An external FET provides flexibility in the
design, allowing lower on resistance devices to be used
compared with integrated FET controllers, and possibly
achieving greater efficiency.
In Figure 2, a large percentage of the overall power loss
is dissipated in the freewheeling diode D2. In Figure 3 this
diode is replaced with an N-channel FET, making this
circuit a synchronous buck converter, which significantly
improves the converter efficiency. Efficiency improvements
Figure 2. Low-cost, non-synchronous buck regulator
5 VIN
+
2
VCC
6
DTC
3
R2
30.1 kΩ
R6
10 kΩ
OUT
4
FB
7
RT
8 GND
R4
100 kΩ
R5
43.2 kΩ
3 2 1
COMP
C3
0.033 µF
Q1
2N3904
R1
499 Ω
U1
TL5001D
C2
100 pF
C1
470 µF
6.3 V
SCP
1
4
Q2
TPS1101
D1
MBRM140
5
L1
47 µH
8 7 6 5
3.3 V
D2
MBRS340T3
C4
1 µF
R3
100 kΩ
+
C5
470 µF
6.3 V
C6
1000 pF
Figure 3. External-switch synchronous buck regulator
Q1
Si3443DV
5 VIN
4
C3
22 µF
6.3 V
3
U1
TPS43000
R2
37.4 kΩ
C8
3.0 pF
R5
32.4 kΩ
1
2
3
4
5
6
7
8
SYNC/SD
SWN
CCS
SWP
RT
PDRV
BUCK
GND
PFM
NDRV
COMP
VOUT
FB
C7
270 pF
R4
115 kΩ
VP
CCM
VIN
C9
560 pF
3.3 V
6
5
2
1
+
C1
120 µF
4V
C2
22 µF
6.3 V
R1
1 kΩ
16
15
14
13
12
11
10
9
R3
L1
5.0 µH
1 2 5 6
C4
0.47 µF
3
4
C5
0.47 µF
Q2
Si3442DV
D1
ZHCS2000
C6
0.47 µF
5.76 kΩ
R6
100 kΩ
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Figure 4. Step-down charge pump
Figure 5. Boost regulator
5 VIN
U1
TPS60501DGS
C1
1 µF
16 V
1
2
3
4
5
EN
FB
PG
GND
C2F–
C1F–
C2F+
OUT
VIN
C1F+
R1
499 kΩ
10
9
8
7
6
C2
.01 µF
C2
1 µF
16 V
C3
.01 µF
C4
22 µF
6.3 V
C3
4.7 µF
6.3 V
4
EN
VCC
REF
FB
SS
OUT
COMP
GND
L1
15 µH
8
7
6
5
12 V
D1
MBRS130T3
C5
10 µF
16 V
solution. The controller utilizes internal FETs that connect
two flying capacitors in various series or parallel configurations, dumping their energy to the output. The input
voltage and the load are used to set the internal FET
configuration automatically. At loads heavier than 150 mA,
the controller acts as an LDO and stops using the switched
capacitors altogether. Output current is limited to a maximum of 0.25 A, which limits this circuit to low-power
applications. Efficiency is between 80 and 90% for light
loads between 1 mA and 50 mA, but drops off to approximately 65% above that when operating in LDO mode. The
cost of Figure 4 is one of the lowest, due to the low cost of
the ceramic capacitors.
Table 3 provides a summary of the low-voltage step-down
options discussed. Efficiency, cost, and circuit area are
also listed for reference. So what’s the right choice? Linear
regulators, when you can afford the losses. Then take a
look at charge pumps and determine their losses based on
conversion ratios. Finally, evaluate non-synchronous and
then synchronous regulators. In each case, the system
cost and size increase, but more power is available for the
load. A second trade-off in the switching power supplies
involves deciding between internal and external FETs.
The cost is usually lowest with external FETs; while the
design time, component count, and size will be smaller
with internal FETs.
Powering higher-voltage analog
Table 3. Low-voltage (5-V to 3.3-V) regulator options
Linear
Non-synchronous buck
Non-synchronous buck
Synchronous buck
Synchronous buck
Charge pump*
2
U1
TPS6734D
C4
1000 pF
can be realized over a wide load range with this circuit. At
very light loads, pulse skipping can decrease gate-drive
losses. When the output voltage drops 2% below the nominal voltage set point, the converter senses it and switches
until the output reaches an upper threshold; it then puts
itself in sleep mode until the load discharges the output
capacitor to the lower threshold again. This circuit provides
excellent efficiency but is more costly than the one in
Figure 2. Its circuit area is also slightly smaller, mainly
because the controller can operate at frequencies of up to
1 MHz, which allows the inductor and input/output capacitors to be noticeably smaller.
Integrating the top FET, bottom FET, drive circuit, and
feedback compensation into the controller provides for a
small, integrated, and efficient converter solution. This is
becoming a very popular solution because it is generally
simple to design and has a very short design cycle time.
Software is available that aids in the design, making it
possible for novices to design power supplies. Controllers
such as the TPS5431x and TPS5461x SWIFT TM series provide such integration, but their cost is higher due to the
added performance and features.
Circuit area is often a critical design parameter. The stepdown charge pump in Figure 4 represents an extremely
small solution. Four ceramic capacitors and the charge
pump controller are the only components required for this
TOPOLOGY
1
3
3.3 V
5 VIN
INTERNAL
SWITCH
Y
N
Y
N
Y
Y
C1
4.7 µF
6.3 V
OVERALL
RELATIVE
COST
(%)
40
100
150
200
250
70
TYPICAL
EFFICIENCY
(%)
66
87
85
96
95
60 to 90
AREA
(in2)
0.1
1.2
1.1
1.0
0.7
0.15
Higher-legacy voltages, such as 5 V
and 12 V, are often required to power
analog circuits. The loading on these
outputs is typically not as heavy as on
their digital voltage counterparts—
usually less than 100 mA. The circuit
in Figure 5 is a boost regulator that
provides 12 V and will provide up to
120 mA while operating over the 5-V
USB output voltage range. In this
*Current is limited to 0.25 A, and efficiency is largely dependent on input voltage.
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Figure 6. Synchronous SEPIC converter
5 VIN
C1
22 µF
6.3 V
D1
B240
L1
47 µH
C3
1 µF
1
Q1
IRF7404
2
3
4
5 VOUT
1 2 3
5 6 7 8
5
6
Q2
IRF7401
4
7
8
1 2 3
C6
22 µF
6.3 V
C7
100 µF
6.3 V
R2
86.6 kΩ
U1
UCC39421PW
R3
1 kΩ
5 6 7 8
4
C2
1 µF
R1
10 Ω
RSEN
RSEL
VOUT
COMP
RECT
FB
PGND
PFM
CHRG
GND
VPUMP
CP
VIN
RT
SYNC/SD
ISENSE
16
15
14
13
11
C8
1 µF
C9
1 µF
R5
28 kΩ
10
9
L2
47 µH
R7
0.1 Ω
0.25 W
R4
169 kΩ
12
R6
169 kΩ
C4
68 pF
C5
4700 pF
D2
BAT54
R8
3.01 kΩ
design, the FET is integrated
Figure 7. Synchronous buck converter with auxiliary output winding
into the controller along with
the feedback resistor network,
reducing total parts count to a
minimum. A drawback to this
Q1
IRLMS6702
approach is that the circuit
5V
block provides no current limit.
U1
If the 12-V output is shorted to
C1
TPS62000DGS
10 µF
ground, there is nothing in the
10
1
VIN
PGND
6.3 V
5 VIN
VIN, L1, D1 path to limit current.
2
9
FC
L
3.3 V
An alternative topology, the
3
8
L1
GND
EN
SEPIC, can overcome this shortC4
10
µH
C3
C2
4
7
R1
PG
SYNC
10 µF
0.1 µF
4.7 µF
coming. Also, the SEPIC conver825 kΩ
5
6
FB
ILIM
6.3 V
6.3
V
sion ratio extends above and
below the input voltage as
compared with the boost, whose
R2
130 kΩ
ratio just includes voltage greater
than VIN. Since the USB voltage
can range from 4.5 V to 5.5 V,
the SEPIC converter in Figure 6
makes an excellent choice for a
5-V output. This SEPIC uses a synchronous rectifier Q1 to
high RMS ripple-current rating and a low ESR to minimize
reduce the losses in the output diode and improve effithe output ripple voltage. Ceramic capacitors are usually
ciency by several percent. Diode D1 conducts only during
chosen due to their high ripple-current rating and low cost.
the on/off transitions of Q1 to prevent the intrinsic diode
Figure 7 shows an option for providing dual-output voltof Q1 from conducting. Additional benefits include lowages from a single synchronous buck converter. When the
input ripple currents and inherent current limiting. On the
bottom-side FET (internal to TPS62000) conducts, FET
negative side, the addition of the dc blocking capacitor C3
Q1 turns on, and output cap C1 charges with an additional
is required. Since the blocking capacitor and output capacivoltage developed across the secondary of L1. The level of
tors must handle large pulsing currents, they require a
the auxiliary voltage is determined by the turns ratio
32
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Table 4. Higher-voltage regulator options
TOPOLOGY
5-V to 12-V boost
5-V to 12-V boost
5-V to 5-V SEPIC*
5-V to 5-V SEPIC
3.3-V to 5-V charge pump**
Sync buck w/aux winding✝
INTERNAL
SWITCH
N
Y
N
Y
Y
Y-Sync buck
N-Aux
TYPICAL
EFFICIENCY
(%)
86
85
89
85
65 to 75
95
CURRENT
LIMIT
N
N
Y
Y
Y
Y
OVERALL
RELATIVE
COST
(%)
280
320
560
550
200
100
AREA
(in2)
0.7
0.6
1.0
0.9
0.2
0.3
* Synchronous operation
** TPS60133 charge pump controller, 0.3-A maximum output current
✝ Cost and area of auxiliary output only
between the two windings of L1. The voltage across C1 is
stacked on the 3.3-V regulated output; so, for a 5-V auxiliary
output, an additional 1.7 V needs to be developed across
L1’s secondary. A turns ratio of 2:1 will work well in this
application. For low current levels, the voltage drops
developed across the internal bottom FET and Q1 (which
turn on in phase with each other) are small and often cancel each other out. These FET drops may not significantly
add to the output-voltage tolerance error, and good regulation can be achieved.
Table 4 presents a comparison of some of the options
for generating higher voltages for analog loads. Here again,
the decision involves a trade-off between cost, performance,
and loss. If power is not a problem, the first choice to
consider is a charge pump. When loss becomes an issue, a
switching regulator may become warranted. The first
circuit to consider, particularly if a buck regulator is being
used, is the auxiliary winding scheme of Figure 7. It adds
minimal cost and degrades efficiency the least. Next come
the SEPIC and boost regulator. The need for short-circuit
protection will determine which approach will be favored.
Usually a boost will be chosen for its higher efficiency if
current limiting is not needed or can be accommodated
elsewhere in the system. There are also trade-offs in
synchronous and non-synchronous operation, as well as in
an internal versus external switch, as in the buck regulator.
USB-powered DSL modem power supply example
The circuit in Figure 8 (next page) is an example of a
complete USB power supply with 3.3-V, 5-V, and 12-V
outputs. With the 3.3-V powered at 0.32 A, the 5-V at
0.05 A, and the 12-V at 0.05 A, the overall efficiency is
89.5%, which allows the input power to remain below the
2.25-W maximum limit. In operation, only the 3.3-V output
is allowed to power up at turn-on, with the 5-V and 12-V
enable pins being held low by the bus controller. No more
than 100 mA is drawn off the 3.3-V output during powerup in low-power mode. Enumeration then comes from the
bus controller to allow the 5-V and 12-V to power up. A
boost topology was used for both the 5-V and 12-V outputs,
with the 5-V power stage input powered from the 3.3-V
output. The controller chosen for both boost regulators
was the low-cost TL1451A dual controller. The approach
taken for this design example is geared toward low cost
and high efficiency rather than small area. Figure 9 shows
a photograph of the completed hardware, which measures
1.5" × 2".
Figure 9. DSL modem power supply
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Figure 8. USB-powered DSL modem power supply
J1
4.5 - 5.5 VIN
GND
U1
TPS62000DGS
5 VIN
1
2
C2
0.1 µF
C1
4.7 µF
6.3 V
C5
0.1 µF
1
2
3
4
5
10
9
L
8
EN
7
SYNC
6
VIN
PGND
FC
GND
PG
FB
L1
10 µH
J2
4
R3
825 kΩ
ILIM
R6
100 kΩ
R5
130 kΩ
C6
0.1 µF
3
C4
10 µF
6.3 V
R7
100 kΩ
2
1
Q1
IRLMS6802
R8
10 kΩ
1 2 5 6
Q3
2N7002
5-V & 12-V
Enable
C7
0.1 µF
C8
0.1 µF
R10
10 kΩ
R11
10 kΩ
GND
12 V @ 100 mA
Q2
IRLMS6802
3
R9
10 kΩ
5 V @ 100 mA
4
4
3
3.3 V @ 500 mA
1 2 5 6
Q4
2N7002
C9
4.7 µF
6.3 V
L2
3.8 µH
R13
84.5 kΩ
C14
0.1 µF
C15
0.1 µF
R21
12.7 kΩ
R23
20 kΩ
R22
100 kΩ
R25
C18
.01 µF
R18
1 kΩ
R24
20 kΩ
U2
TL1451ACNS
C16
.01 µF
R20
12.7 kΩ
R19
20 kΩ
R26
1 kΩ
C11
1 µF
R15
28.0 kΩ
C13
0.1 µF
100 kΩ
R27
20 kΩ
16
11
12
13
14
6
5
4
3
2
1
R28
13.3 kΩ
VREF
2DTC
2FB
GND
2IN–
2IN+
2OUT
1DTC
1FB
1OUT
R16
1 2 5 6
3
1 kΩ
9
Q6
MMBT3906
R17
499 Ω
8
4
1IN+
RT
SCP
D1
MBRS130T3
Q7
IRLMS2002
C12
10 µF
16 V
Q8
MMBT3906
10
7
L3
10 µH
C17
4.7 µF
6.3 V
15
CT
C19
1 µF
C20
1 µF
R30
1 kΩ
R29
499 Ω
Q9
MMBT3904
1 2 5 6
3
Q10
MMBT3906
R31
499 Ω
R34
10 kΩ
Q5
MMBT3904
1IN–
C22
150 pF
C24
1 µF
VCC
R14
499 Ω
4
D2
MBRS130T3
Q11
IRLMS2002
C21
10 µF
16 V
Q12
MMBT3906
R32
84.5 kΩ
Conclusion
Reference
The design of a power supply powered from the USB port
is heavily driven by the 2.25 W of available input power
and the peripheral load requirements. The design process
should involve a very careful analysis of load currents
followed by a program to minimize them. Once the loads
have been determined, the power-supply engineer should
develop multiple block diagrams with the topologies
described in this article to develop the lowest-cost, most
power- and area-compliant approach. The array of integrated circuits to support these designs is very diverse;
the designer has the options of striving for maximum
integration, minimum cost, and ease of use.
1. USB Implementers Forum Inc., “Universal Serial Bus
Specification Revision 2.0,” www.usb.org
Related Web sites
www.ti.com/sc/device/partnumber
Replace partnumber with TL1451A, TL5001, TPS2140,
TPS6734, TPS43000, TPS54310, TPS54610, TPS54611,
TPS60130, TPS60500, TPS62000 or UCC39421
www.usb.org
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2Q 2002
Analog Applications Journal
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C011905
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SLYT118
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