Texas Instruments | Interfacing Between the 1394a Links and TSB41BA3A (Rev. A) | Application notes | Texas Instruments Interfacing Between the 1394a Links and TSB41BA3A (Rev. A) Application notes

Texas Instruments Interfacing Between the 1394a Links and TSB41BA3A (Rev. A) Application notes
Application Report
SLLA153A – October 2004
Interfacing Between the 1394a Links and TSB41BA3A
David Liu .................................................................................................... Catalog Interface Solutions
ABSTRACT
The TSB41BA3A, a 1394b PHY, can interface to 1394-1995 and 1394a link-layer
controllers (LLC) like the following: TSB12LV21B, TSB12LV26, TSB12LV32,
TSB42AA4, TSB42AB4, or TSB12LV01B. For integrated 1394 link and PHY such as
TSB43AA82A, it can also be connected cable port to cable port. This application report
describes overall electrical connections between a Texas Instruments (TI) discrete
1394-1995, 1394a link and TSB41BA3A, using the TSB12LV32 and TSB12LV01B as
the examples.
Contents
1
Terminology .........................................................................................
2
Cable Interface ......................................................................................
3
Physical Layer Device – TSB41BA3A ...........................................................
4
PHY-Link Interface .................................................................................
5
Link-Layer Controller-TSB12LV01B ..............................................................
6
Link-Layer Controller-TSB12LV32 (GP2Lynx) ..................................................
7
References ..........................................................................................
Appendix A
Reference Schematic ....................................................................
1
2
3
4
5
6
7
8
List of Tables
1
1
Possible Cable Connections ...................................................................... 2
Terminology
In this application report, several terms are used to describe components of a node-to-node 1394
connections. These terms are defined here to enhance clarity:
Port: refers to the port terminal pins on the PHY device. TSB41BA3A is a three-port PHY device.
Connector: refers to the physical receptacle located in close proximity to the PHY. Its pins are connected
directly to the port through the termination resistor networks. The connector is designed to receive a
cable’s plug.
Plug: located at each end of a 1394 cable and is inserted into the connector.
SLLA153A – October 2004
Interfacing Between the 1394a Links and TSB41BA3A
1
www.ti.com
Cable Interface
2
Cable Interface
The TSB41BA3A cable interface can follow either the 1394a-2000 (1394a) protocol or the 1394b-2002
(1394b) protocol on each port. The mode of operation of any given port is determined by the interface
capabilities of the port being connected and the way the port has been configured using the six selection
pins (Table 1 of the TSB41BA3A data manual). When any of three ports configured as 1394b bilingual or
1394a data-strobe is connected to a 1394a compliant node, the cable interface of that port operates in the
1394a data-strobe mode at s100, s200, and s400 speed. When any of three ports configured as 1394b
beta-only 200 (B2), for example, is connected to a 1394b compliant node, the cable interface of that port
operates in the 1394b mode at s100B and s200B speed only.
The 1394b specification extends the 1394 bus speed to s800, s1600, and s3200. A new Beta connector
and its associated cable are defined in the 1394b specification. A node that only runs in Beta mode should
use the Beta-only connector and Beta cable. For 1394-1995 and 1394a legacy connection, a cable with a
legacy plug on one side and a bilingual plug on the other side should be used. A Beta-only or a bilingual
PHY port cannot be connected to either the 1394a 4-pin connector or the 1394a 6-pin connector. Only a
port that is configured as a 1394a data-strobe port can be connected to either the 1394a 6-pin or the 4-pin
connector. Table 1 illustrates the TSB41BA3A connection scheme.
Table 1. Possible Cable Connections
Plug 1
Plug 2
Max Speed
Bilingual
6 Pin Cable (Carries Power)
S400
Bilingual
4 Pin Cable (No Power)
S400
Bilingual
Bilingual
S400B
Beta
Beta
S400B
Beta
Bilingual
S400B
The port configuration is done through the S5_LINKON, S4, S3, S2_PC0, S1_PC1, and S0_PC2 selection
pins. On hardware reset, S5_LINKON, S4, S3, S2_PC0, S1_PC1, and S2_PC2 are selection pins that
configure the speed and mode of the ports of the TSB41BA3A. Please refer to Table 1 of the TSB41BA3A
data manual (SLLS618) for a complete description of the port configuration process.
The cable interface is shown on sheet 1 of the 1394a Link/TSB41BA3A schematic (Appendix A). It
includes two 1394b Bilingual Connectors (Connector 0 and Connector 1) that connect to the PHY. Port 2
is not brought out to a connector. Port 2 is an unused port configured as a 1394a port. In this case, mode
#2 is used for port configuration; S5_LINKON and S4 are tied to the GND through a 1-kΩ resistor
respectively. S3 is tied to DVDD(3.3) through a 1-kΩ resistor. TSB41BA3A automatically determines the
correct cable interface connection method for the bilingual ports.
The cable power from each cable is connected to the other ports and is available as bus power. The PHY
operates off bus power in the schematic. A voltage regulator regulates the bus power to 3.3V. To be 1394
compliant, the regulator must allow input voltage ranges between 8-V DC and 30-V DC. The voltage
regulator is shown on sheet 1 of the 1394a Link/TSB41BA3A schematic (Appendix A). When cable power
is not active, the voltage regulator may also be powered from a 12-V source, such as a PC power supply.
A diode determines which power source is used. For protection, a 0.75-A fuse should be used in-line with
the 12-V source.
The cable shield from each cable (pin10, 11, 12, 13 of the bilingual connector) is directly connected to
chassis ground. The Twisted-Pair A Reference Ground must also be tied to signal ground through a
combination of resistor and capacitor. The combination of a 1-MΩ resistor and 0.1-µF capacitor placed
next to each connector is suggested.
The drivers on each port (TPA and TPB) are designed to work with an external 112-Ω termination-resistor
network. This is to match the 110-Ω cable impedance. One network must be provided at each end of the
twisted-pair cable. On bilingual ports, the midpoint of the TPA resistor network is directly connected to
TPBIAS, a 1-µF capacitor for stability and a 270-pF capacitor for EMI on TPBIAS. The midpoint of the
TPB resistor network is coupled to ground through a parallel RC network. These 112-Ω termination-resistor networks should be placed as close as possible to the PHY, and the common mode
components should be placed as close as possible to the 112-Ω termination network.
2
Interfacing Between the 1394a Links and TSB41BA3A
SLLA153A – October 2004
www.ti.com
Physical Layer Device – TSB41BA3A
3
Physical Layer Device – TSB41BA3A
The electrical connection for TSB41BA3A is shown on sheet 2 and sheet 3 of the 1394a Link/TSB41BA3A
schematic (Appendix A).
The power pins (DVDD-3.3, AVDD-3.3, DVDD(CORE), and PLLVDD(CORE)) of the TSB41BA3A must be
grouped separately, and then decoupled to the GND pins through several high-frequency decoupling
capacitors. The following rules apply to the decoupling capacitors:
• Place one 0.001-µF capacitor as close as possible to each power pin. If two or more power pins are
adjacent, only one 0.001-µF capacitor is required for the group.
• Place one 0.1-µF capacitor as close as possible to each single power pin on the PHY. A single power
pin is one that is not adjacent to another power pin.
TSB41BA3A requires an external 49.152-MHz crystal clock to generate a reference clock. The external
clock drivers an internal phase-locked loop (PLL), which generates the required reference signal. This
reference signal provides the clock signals that control transmission of the outbound encoded information.
A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is
used for resynchronization of the received data when operating the PHY-link interface in compliance with
the IEEE 1394a-2000 standard (BMODE input low). A 98.304-MHz clock signal is supplied to the
associated LLC for synchronization of the two devices when operating the PHY-link interface in
compliance with the IEEE 1394b-2002 standard (BMODE input high).
Crystal Selection: To ensure that the PHY oscillator starts under all operational conditions, TI
recommends using a fundamental parallel mode crystal with a CL of 20-pF or less with an ESR of 30-Ω or
less. The termination capacitor values that should be placed on each leg of the crystal can be calculated
with the following equation:
Ctermination = (CL- Cboard) x 2
Where:
Cboard = (Board trace capacitance + PHY input capacitance)
If a 20-pF crystal is placed close to the PHY, then Cboard≈ 4-pF and Ctermination≈ 33-pF.
When a 1394 port is not brought out to a connector, it must be terminated correctly. The preferred method
is to configure the port in the 1394a mode. In the 1394a mode, the TPB+ and TPB- pins must be tied
together and connected to ground. The TPBIAS can be tied to ground through a 1-µF capacitor or left
unconnected. The TPA+ and TPA- pins can be left unconnected. Port 2 in the schematic illustrates a
properly terminated 1394a port.
The CPS pin detects the presence of cable power and is connected to the cable power through a 400-kΩ
resistor. A common resistor value of 390-kΩ may be used. The node should always have the CPS pin
connected to cable power through a 400-kΩ resistor, even if the PHY does not use cable power. If cable
power is not available, the CPS may be tied directly to PHY ground.
The assertion of the RESET pin resets the internal logic. An internal pull-up to VDD is provided so only an
external delay capacitor is required for proper power-up operation. A 0.22-µF is the recommend value for
the external delay capacitor.
The R0 and R1 terminals set the internal operating currents and the cable driver output current. To meet
the IEEE 1394-1995 standard output voltage limits, a 6.34-kΩ± 1% resistance is required.
S2_PC0, S1_PC1, and S0_PC2 are power class and ports mode configuration pins. On hardware reset,
those pins, along with the other three mode configuration pins (S5_LINKON, S4, and S3), allow the user
to configure the three ports of TSB41BA3A. After the hardware reset, they become the power class pins.
The power class pins program the power class value into the PWR field of the transmitted self-ID packet.
This allows other nodes on the bus to understand the power requirements of the node. These pins are
programmed according to the Power Class Description in the IEEE 1394a standard, Table 7-3. The
schematic is programmed to a power class of “100” or decimal 4. This indicates that the node:
1. May be powered from the bus
2. Is capable of repeating power
3. Is using up to 3 W
SLLA153A – October 2004
Interfacing Between the 1394a Links and TSB41BA3A
3
www.ti.com
PHY-Link Interface
4. Needs no additional power to enable the link
The power class pins are hard-wired to their values shown on the schematic.
S4 and S3 are configuration pins. Along with the other four mode configuration pins (S5_LINKON,
S2_PC0, S1_PC1, and S0_PC2), they allow the user to configure the three ports of TSB41BA3A. In this
case, mode #22 is used for ports configuration, S4 is tied to the GND through a 1-kΩ resistor and S3 is
tied to DVDD(3.3) through a 1-kΩ resistor.
VREG_PD is the enable pin for the internal voltage regulator that supplies the core voltage. For a single
3.3-V supply operation, this pin must be tied low to enable the voltage regulator. If this pin is tied high,
then the core voltage must be supplied externally to the PLLVDD(CORE) and DVDD(CORE) respectively.
In the 1394b mode, TSB41BA3A uses the PINT to send status and interrupt information to the link. In the
1394a mode, the PINT can be left open and unconnected.
In the 1394a mode, the LCLK should be tied to ground.
TESTM, SE, and SM terminals are test control pins for manufacturing test. For normal operation, TESTM
must be tied to DVDD(3.3) through a 1-kΩ resistor. SE and SM must be tied to ground directly.
4
PHY-Link Interface
The PHY-link interface of the TSB41BA3A can follow either the 1394a protocol or the 1394b protocol.
When using any 1394-1995 or 1394a links such as the TSB12LV01B or the TSB12LV32, the PHY-link
interface has to be in the 1394a protocol. In this case, the BMODE pin has to be tied low to GND. When
using any 1394b link such as the TSB82AA2, the PHY-link interface has to be in the 1394b protocol. In
this case, the BMODE pin is tied high. The BMODE pin only sets the mode of operation of the PHY-link
interface; it does not set the mode of operation of the cable interface. No isolation is implemented in this
schematic. The PHY and link operate off of the same ground plane.
To reduce EMI emissions and reduce reflections on the PCLK line, a series-damping resistor is
recommended. The schematic shows a 0-Ω resistor, which is essentially a placeholder on the board. To
reduce EMI, a 22-Ω resistor on the PCLK line is recommended. This resistor should be placed as close to
the PHY as possible. Its value can be adjusted to reduce emissions. By slowing down the edge rates on
PCLK, this 22-Ω resistor significantly reduces reflections that may occur when the distance between the
PHY and link is large (greater than 4 inches in this case).
The Link Request signal (LREQ) is input to the PHY from the link. The link uses this to initiate a service
request to the PHY. When the BMODE pin is deasserted, the IEEE 1394b-2002 BOSS arbitration is
disabled and the LREQ request stream follows the 1394a specification.
CTL0 and CTL1 are bi-directional signals used to control the communication between the PHY and the
link. These signals should be directly connected between the PHY and link. The CTL encoding follows the
1394a specification.
TSB12LV01B and TSB12LV32 are 400-Mbps link layer devices that use all data I/O lines (D0- D7) to
communicate with the PHY. When status information is received from the PHY, only D0 and D1 are used.
S5_LINKON of TSB41BA3A is used both as a link-on output and as a configuration pin for the ports. On
hardware reset, this terminal, along with other 5 configuration pins (S4, S3, S2_PC0, S1_PC1, and
S0_PC2), allows the user to configure the TSB41BA3A ports. After hardware reset, this terminal is the
link-on output, which notifies the LLC or other power-up logic to power up and become active. This
terminal can be connected to the link-on input terminal of the LLC through a 1-kΩ resistor if the link-on
input is available on the link layer.
If a power down option control for PD is not implemented, the PD pin on the PHY (pin 77) should be tied
to ground through a 1-kΩ resistor to keep the PHY enabled.
4
Interfacing Between the 1394a Links and TSB41BA3A
SLLA153A – October 2004
www.ti.com
Link-Layer Controller-TSB12LV01B
5
Link-Layer Controller-TSB12LV01B
The TSB12LV01B is a 400-Mbps general-purpose IEEE 1394-1995 link-layer controller. The TSB12LV01B
was intended for use in PC peripherals and telecom. It can transfer data between a host controller, 1394
PHY-Link interface, and external devices connected to the local bus interface.
The TSB12LV01B follows the big-endian architecture. Bit 0 is the most significant bit. Byte 0 is the most
significant byte.
ADDR0 – ADDR7 is the 8-bit host address bus. This bus should be connected to the host processor
address bus. All internal memory space (CFR and FIFO) may be addressed with only 6 of the 8 address
lines. Address lines 6 and 7 should be grounded. Most significant byte of the TSB12LV01B address
should be connected to the most significant byte of the host processor address bus, regardless of the host
processor endianess.
The 32-bit host interface of the TSB12LV01B was designed to support a Motorola 68K-type
microcontroller/microprocessor. The interface supports three access modes: normal, quick, and burst.
DATA0 –DATA31 is the 32-bit host data bus. This bus should be connected to the host processor I/O data
bus. Most significant byte of the TSB12LV01B data bus should be connected to the most significant byte
of the host processor data bus, regardless of the host processor endianess.
The BCLK is the clock input to the TSB12LV01B and should be tied to the host output clock. The
TSB12LV01B can support clock rates up to 50-MHz.
The CA pin of the TSB12LV01B is the active-low Cycle Acknowledge pin. It is a control signal to the host
bus. When asserted, it signals an acknowledge from the TSB12LV01B to the host access cycle. It
indicates that the access to the TSB12LV01B configuration register (CFR) space or FIFO is complete.
Note:
If interfacing directly to a Motorola 68K-type microcontroller/microprocessor, the CA pin
should be connected to the transfer acknowledge (TA) pin of the processor.
The CS pin of the TSB12LV01B is the active-low Cycle Start pin that indicates the beginning of an access
to the TSB12LV01B configuration or FIFO space.
Note:
If interfacing directly to a Motorola 68K-type microcontroller/microprocessor, the CS pin
should be connected to the transfer start (TS) pin of the processor.
INT is an active-low Interrupt pin that should be connected to the Interrupt pin of the host. When INT is
low, TSB12LV01B notifies the host bus that an interrupt has occurred.
WR is the Read/Write enable pin that should be connected to the WR pin of the host. When CS is low and
WR is high, a read from the TSB12VL01B is requested by the host bus controller. To request a write
access, WR and CS must be low.
The RESET is the asynchronous system reset to the TSB12LV01B. This pin may be connected to the
PHY reset pin, may be controlled by the host controller, or may be controlled via an external reset source.
The CYCLEIN input terminal is an optional external 8-kHz clock input that can be used to set up the
isochronous cycle clock. This terminal is tied to VCC since it is not used in this case.
The CYCLEOUT output terminal is the TSB12LV01B version of the cycle clock. It is based on the timer
controls and received cycle-start messages. It may be left open.
GPO0, GPO1, and GPO2 are general-purpose output bits. The power up default function for these
terminals is GRFEMP, CYCDE, and CYST respectively if they are not being used. After power-up, these
terminals may be programmed as general-purpose output pins.
SLLA153A – October 2004
Interfacing Between the 1394a Links and TSB41BA3A
5
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Link-Layer Controller-TSB12LV32 (GP2Lynx)
6
Link-Layer Controller-TSB12LV32 (GP2Lynx)
The TSB12LV32 is a 400-Mbps IEEE 1394a general-purpose link-layer controller. The 12LV32 can be
used in PC peripherals, such as printers, scanners, and desktop cameras. It can transfer data between a
host controller, 1394 PHY-Link interface, and external devices connected to the data mover port (DMA
interface).
The TSB12LV32 DIRECT pin is sampled during hardware reset to determine if galvanic isolation is
present. If the terminal is high, no isolation is present. If the terminal is low, TI bus-holder isolation is used.
The TSB12LV32 does not support Annex J isolation.
The CONTNDR terminal on the link defaults to being input on hardware reset. In the schematic,
CONTNDR is tied to ground through a 1-kΩ resistor. This tells the link that the node is not contender for
Isochronous Resource Manager (IRM) or Bus Manager functions. However, after power-on, the value of
this pin may be driven internally from the CTNDRSTAT bit inside the link layer controller.
The TSB12LV32 has a programmable microcontroller interface with 8-bit or 16-bit data bus, five different
modes of operation include burst mode, and a clock frequency up to 50-MHz. In this schematic, it is set up
to operate in 16-bit fixed-timing mode with a Motorola 68000-style processor. To configure the
TSB12LV32 for this mode, the MCMODE/SIZ1 and M8BIT/SIZ0 pins are tied to ground. Because the
device is not configured for the Motorola ColdFire mode, the ColdFire terminal is also tied to ground.
The MCS (Cycle Start) terminal is an active-low input terminal to the GP2Lynx. It signals the beginning of
a microcontroller access to the GP2Lynx. The MCS is connected to the TSZ line on the Motorola 68000.
The MCA (Cycle Acknowledge) is an active-low output signal representing the cycle acknowledge sent
from the GP2Lynx to the TAZ terminal on the 68000. The MWR is the read/write indicator. When asserted
high, this input terminal indicates a read access from the GP2Lynx. When asserted low, it indicates a write
access to the GP2Lynx. All data transfers on the microcontroller interface are synchronized with the rising
edge of the BCLK.
The GP2Lynx device follows the big-endian architecture: to configure the micro interface for little-endian
mode, the LENDIAN pin must be set high. In little-endian mode, the MD [0:15] lines are byte-swapped
before it is written into the device’s internal FIFO or configuration register (CFR). In the schematic,
big-endian mode is used; therefore, LENDIAN is tied to ground. Because the Motorola 68000 processor
uses bit 15 as the MSB (most significant bit) and the GP2Lynx uses bit 0 as the MSB, the data interface is
swapped between the two devices (i.e., bit 15 on the GP2Lynx is connected to the bit 0 of the 68000). The
micro interface can also be configured for data-invariant or address-invariant modes using the MDINV and
MCMODE/SIZ0 terminals. However, MDINV is meaningful only when LENDIAN is enabled (high).
All GP2Lynx internal registers are 32-bit wide. However, since the Motorola 68000 processor operates on
word boundary accesses, the GP2Lynx internally stacks 2 word writes before transferring tem to the link
registers. No external byte stacking is needed.
Accessing all GP2Lynx internal registers requires only 7 bits of address lines. Since MA [0] is the MSB bit
on the TSB12LV32, it is connected to A [6] of the 68000 processor. Consequently, MA [6] is connected to
A [0] of the 68000 processor.
The TEA terminal is connected to the Motorola TEAZ input terminal. This signal indicates the presence of
an error in the data transfer operation.
The STAT0 – STAT2 are general status output terminals. These pins can be independently programmed
to show one of fourteen possible internal hardware statuses. For more information on the programming of
the STAT0 – STAT2, please refer to the latest TSB12LV32 data manual (TI Literature Number
SLLS336B).
The CYCLEIN input terminal is an optional external 8-kHz clock that can be used to set up the
isochronous cycle clock. This terminal is tied to VDD since it is not used in this case.
INT is an active-low output terminal representing the logical NOR of all internal interrupts.
The data mover (DM) port is an 8/16-bit high-speed port that supports isochronous, asynchronous, and
asynchronous streaming transmit/receive from an unbuffered port at 25-MHz. It is meant to handle an
external memory interface of large data packets. The DM port has eight modes of operation and can
support four-channels for isochronous transmit.
6
Interfacing Between the 1394a Links and TSB41BA3A
SLLA153A – October 2004
www.ti.com
References
The DM port has seven control pins. For more information on the functionality of these pins, please refer
to the latest TSB12LV32 data manual (TI Literature Number SLLS336B).
7
References
1. TSB12LV01B, IEEE 1394-1995 High-Speed Serial-Bus Link-Layer Controller (SLLS435A)
2. TSB12LV32, TSB12LV32I, IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer
Controller for Computer Peripherals and Consumer Audio/Video Electronics (SLLS336B)
3. TSB41BA3A, IEEE 1394b Three-Port Cable Transceiver/Arbiter (SLLS618)
4. IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus
5. IEEE Std 1394a-2000, IEEE Standard for a High Performance Serial Bus – Amendment 1
6. IEEE Std 1394b, IEEE Standard for a High Performance Serial Bus – Amendment 2
SLLA153A – October 2004
Interfacing Between the 1394a Links and TSB41BA3A
7
www.ti.com
References
Appendix A Reference Schematic
8
Reference Schematic
SLLA153A – October 2004
5
4
3
2
R1
TPBIAS0
C1
1
U5
BUS POWER
4.99K
10
C2
C3
R4
R5
D
C17
1uF
CONNECTOR 0
R2
R3
56.2
56.2
270pF
56.2
12V Supply
56.2
D2
2
1
2
5
4
6
ON
FB
SIG_GND
PWR_GND
12
1
L1
DVDD(3.3)
2
680uH
3
C19
C20
100uF
100uF
D
C21
0.01uF
D1
LM2574HVM-3.3
0.75A
MBRS120T3
VOUT
MBRS1100T3
1
TPA0+
3.3uF
50v
F1
1
13
11
4
5
3
6
7
8
2
9
1
10
12
C18
0.01uF
50V
VIN
2
270pF
TPA0BUS POWER
TPB0+
TPB0DVDD(3.3)
1394 Bilingual Connector
C5
.001uF
C6
C7
.001uF
.001uF
C8
.1uF
C9
C22
C23
C24
C25
C26
C27
.1uF
0.001
.1uF
0.001
.1uF
0.001
R6
.1uF
1M
C
C
1000@100MHz
DVDD(3.3)
AVDD(3.3)
12
C28
FB2
.001uF
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C110
C111 C112 C113
10uF
.1uF
0.001
.1uF
0.001
.1uF
0.001
.1uF
0.001
.1uF
0.001
.1uF
0.001
1uF
1uF
C42
C43
C44
C45
C46
10uF
1 uF
0.001
.1uF
0.001
C47
C48
C49
C50
.1uF
0.001
1uF
1uF
1uF
1uF
1000@100MHz
DVDD(3.3)
TPBIAS1
C4
PLLVDD(3.3)
12
R7
C109
FB3
4.99K
270pF
CONNECTOR 1
B
13
11
4
5
3
6
7
8
2
9
1
10
12
.001uF
R8
R9
56.2
56.2
C10
C11
R10
R11
1uF
270pF
56.2
56.2
1000@100MHz
PLLVDD(CORE)
12
FB4
B
TPA1+
TPA1BUS POWER
TPB1+
DVDD(CORE)
TPB1-
1394 Bilingual Connector
C12
C13
C14
C15
C16
R12
.001uF
.001uF
.001uF
.1uF
.1uF
1M
C51
C52
C53
C54
C55
C56
C57
C58
1uF
0.001
.1uF
.001uF
.1uF
.001uF
.1uF
.001uF
A
A
Title
Power and 1394b Bilingual Connectors
Size
B
Date:
5
4
3
2
Document Number
1.0
Monday, August 04, 2003
Rev
1.0
Sheet
1
1
of
3
4
3
BUS POWER
DVDD(CORE)
DVDD(3.3)
AVDD(3.3)
PLLVDD(3.3)
PLLVDD(CORE)
DVDD(3.3)
U2
DVDD-1.8
DVDD-1.8
DVDD-1.8
DVDD-1.8
34
CPS
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
47
46
45
42
41
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
54
53
52
49
48
TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
C
DVDD(3.3)
R17
R18
1K
1K
60
59
58
56
55
TPBIAS2
TPA2+
TPA2TPB2+
TPB2-
33
32
S4
S3
1
27
26
X1
35
36
49.152 MHz
C60
22pF
22pF
R21
31
PLLVDD-1.8
PLLVDD-1.8
29
30
TESTM
S5_LINKON
78
2
VREG_PD
SLPEN
73
79
LPS
80
LREQ
PCLK
3
5
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
9
10
11
12
13
15
16
17
19
20
R0
R1
23
22
PINT
XI
XO
BMODE
74
66
67
68
SE
SM
TSB12LV01B POWER(3.3V)
D
R14
R15
1K
1K
R16
R19
0
R35
1K
16
33
64
86
VCC+5V
VCC+5V
VCC+5V
VCC+5V
76
POWERON
67
65
LREQ
SCLK
63
62
60
59
58
57
55
54
53
52
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
42
44
CYCLEIN
CYCLEOUT
35
34
36
CA
CS
WR
32
39
BCLK
RESET
37
INT
48
49
50
GOP0
GOP1
GOP2
1
11
21
31
38
GND
GND
GND
GND
GND
6.34K 1%
DVDD(3.3)
LCLK
25
28
PLLGND1
PLLGND2
RESETz
PD
75
77
4
14
38
64
72
76
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
21
40
43
50
61
62
B
1K
PLLVDD-3.3
S2_PC0
S1_PC1
S0_PC2
7
C59
24
39
44
51
57
63
R20
FROM MCU /TA
TO MCU /TS
FROM MCU /WR
1K
FROM MCU CLK
TO EITHER MCU /RESET OR PHY /RESET
R22
1K
TO MCU /INT
C61
.22uF
TSB41BA3
TSB12LV01B POWER(3.3V)
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
TSB12LV01B
8
37
65
71
AVDD-3.3
AVDD-3.3
AVDD-3.3
AVDD-3.3
AVDD-3.3
AVDD-3.3
6
26
43
56
69
74
96
390K
DVDD-3.3
DVDD-3.3
DVDD-3.3
DVDD-3.3
MCU ADDR LINE[0:5]
U1
MCU DATA LINE[0:31]
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R13
6
18
69
70
1
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
22
23
24
25
27
28
29
30
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
82
83
84
85
87
88
89
90
92
93
94
95
97
98
99
100
2
3
4
5
7
8
9
10
12
13
14
15
17
18
19
20
RESERVED
75
MTEST0
MTEST1
MTEST2
MTEST3
71
72
73
77
C
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
2
40
41
45
46
47
51
61
66
68
70
78
79
80
81
91
5
A
A
TSB12LV01B POWER(3.3V)
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
Title
TSB12LV01B/TSB41BA3
Size
B
Date:
5
4
3
2
Document Number
1.0
Monday, August 04, 2003
Rev
1.0
Sheet
1
2
of
3
5
4
3
BUS POWER
DVDD(CORE)
DVDD(3.3)
TSB12LV32 POWER(3.3V)
DVDD-1.8
DVDD-1.8
DVDD-1.8
DVDD-1.8
34
CPS
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
47
46
45
42
41
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
54
53
52
49
48
TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
C
DVDD(3.3)
R26
R27
1K
1K
60
59
58
56
55
TPBIAS2
TPA2+
TPA2TPB2+
TPB2-
33
32
S4
S3
1
27
26
X2
35
36
49.152 MHz
7
C84
C85
22pF
22pF
R30
1K
B
25
28
4
14
38
64
72
76
24
39
44
51
57
63
PLLVDD-3.3
31
PLLVDD-1.8
PLLVDD-1.8
29
30
TESTM
S5_LINKON
78
2
VREG_PD
SLPEN
73
79
LPS
80
LREQ
PCLK
3
5
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
9
10
11
12
13
15
16
17
19
20
R0
R1
23
22
R24
BMODE
LCLK
S2_PC0
S1_PC1
S0_PC2
66
67
68
PLLGND1
PLLGND2
RESETz
PD
75
77
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
21
40
43
50
61
62
SE
SM
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
VDD5V
VDD5V
VDD5V
64
LINKON
53
LPS
74
72
LREQ
SCLK
70
69
67
66
63
62
61
60
59
58
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
76
CYCLEIN
79
65
DIRECT
CONTNDR
MA0
MA1
MA2
MA3
MA4
MA5
MA6
24
23
22
21
19
18
17
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
68000
68000
68000
68000
68000
68000
68000
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
99
98
97
96
94
93
92
91
89
88
87
86
84
83
82
81
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
Motorola
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
68000
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
MCMODE/SIZ1
M8BIT/SIZ0
MDINV
COLDFIRE
LENDIAN
14
13
11
12
75
R33
1.2K
R25
0
R28
R32
6.34K 1%
74
10
35
85
10K
R34
1K
DVDD(3.3)
R29
1K
From Motorola 68000/ColdFire TAZ
To Motorola 68000/ColdFire TSZ
From Motorola 68000/ColdFire R/WZ
To Motorola 68000/ColdFire TEAZ terminal
From Motorola 68000/ColdFire CLK or PHY SYSCLK
R31
1K
C86
.22uF
MCA
MCS
MWR
3
6
9
TEA
BCLK
RESET
56
55
54
STAT2
STAT1
STAT0
2
1
16
CYSTART
INT
TESTMODE
C
B
16-Bit Fixed Timing Mode
ColdFire Mode OFF
Big Endian Mode (No Byte Swapping)
5
25
30
45
57
73
78
90
100
GND
GND
GND
GND
GND
GND
GND
GND
GND
TSB41BA3
4
7
8
D
26
27
28
29
31
32
33
34
36
37
38
39
41
42
43
44
46
50
51
52
48
49
77
1K
LINK POWER(3.3V)
PINT
XI
XO
TQFP100
DMD0
DMD1
DMD2
DMD3
DMD4
DMD5
DMD6
DMD7
DMD8
DMD9
DMD10
DMD11
DMD12
DMD13
DMD14
DMD15
DMCLK
DMDONE
PKTFLAG
DMERROR
DMPRE
DMRW
DMREADY
TSB12LV32 (GP2Lynx)
8
37
65
71
390K
AVDD-3.3
AVDD-3.3
AVDD-3.3
AVDD-3.3
AVDD-3.3
AVDD-3.3
95
80
71
68
47
40
20
15
DVDD-3.3
DVDD-3.3
DVDD-3.3
DVDD-3.3
U4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
6
18
69
70
R23
1
AVDD(3.3)
PLLVDD(3.3)
PLLVDD(CORE)
DVDD(3.3)
U3
D
2
TSB12LV32 POWER(3.3V)
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
A
A
TSB12LV32 POWER(3.3V)
Title
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
.001uF
TSB12LV32/TSB41BA3
Size
B
Date:
5
4
3
2
Document Number
1.0
Monday, August 04, 2003
Rev
1.0
Sheet
1
3
of
3
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