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Texas Instruments AN-1238 Wide Bus Applications Using Parallel BLVDS SerDes Devices Application notes
Application Report
SNLA054 – May 2004
AN-1238 Wide Bus Applications Using Parallel BLVDS
SerDes Devices
.....................................................................................................................................................
ABSTRACT
Currently, BLVDS SerDes devices from National Semiconductor are available in 10-bit and 16-bit
configurations. In cases where there are more parallel bits to transmit than a single SerDes can handle,
multiple SerDes pairs can be used in parallel to perform the task provided certain constraints are met. The
problem is clock to data skew. Not the skew between a deserializer's recovered clock (RCLK) and it's
recovered data, but rather, between the RCLK of one deserializer and the data recovered by a second
deserializer operating in parallel. For each SerDes pair the phase between the RCLK and the recovered
data is relatively constant, but any difference in delay from one serial stream to another will result in skew
between the RCLKs of the deserializers and hence the data of one deserializer and the RCLK of another.
Since the client receive device must ultimately use only 1 RCLK, skew between the serial streams will
affect the setup and hold times of the parallel data presented to it.
1
2
3
Contents
SOURCES OF PATH SKEW .............................................................................................. 2
DETERMINING THE WORST CASE SKEW ............................................................................ 3
CONCLUSION .............................................................................................................. 5
List of Figures
....................................................................................
1
Parallel Serializers and Deserializers
2
RCLK and Rdata Timing ................................................................................................... 3
2
List of Tables
1
Maximum Phase Difference and the Impact on Deserializer Output Timing ........................................ 4
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1
SOURCES OF PATH SKEW
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Currently, BLVDS SerDes devices from National Semiconductor are available in 10-bit and 16-bit
configurations. In cases where there are more parallel bits to transmit than a single SerDes can handle,
multiple SerDes pairs can be used in parallel to perform the task provided certain constraints are met. The
problem is clock to data skew. Not the skew between a deserializer's recovered clock (RCLK) and it's
recovered data, but rather, between the RCLK of one deserializer and the data recovered by a second
deserializer operating in parallel. For each SerDes pair the phase between the RCLK and the recovered
data is relatively constant, but any difference in delay from one serial stream to another will result in skew
between the RCLKs of the deserializers and hence the data of one deserializer and the RCLK of another.
Since the client receive device must ultimately use only 1 RCLK, skew between the serial streams will
affect the setup and hold times of the parallel data presented to it.
This application note will show how to use the datasheet parameters tSD (Serializer Delay) and tDD
(Deserializer Delay) to determine the timing constraints at the client receiver parallel interface when using
SerDes in parallel.
Figure 1. Parallel Serializers and Deserializers
1
SOURCES OF PATH SKEW
First let's look at the sources of phase offset (skew) in the paths. The diagram in Figure 1 shows two
SerDes being used in parallel to transmit data from the client transmit device to the client receive device.
• A is the flight time between TCLK1 and TCLK2 from the Client Transmit.
• E is the serializer delay tSD. The deserializer delay consists of a fractional number of clock cycles
whose delay is proportional to the clock rate, and, a constant delay which is the result of propagation
delays in the serializer.
• B is the flight time from serializer 2 to deserializer 2 or from serializer 1 to deserializer 1. This may be
over PCB traces or through cables.
• F is the deserializer delay tDD. The deserializer delay consists of a fractional number of clock cycles
whose delay is proportional to the clock rate, and, a constant delay which is the result of propagation
delays in the deserializer.
• C is the RCLK flight time from Deserializer 2 or Deserializer 1 to the client receive.
In this example the RCLK from deserializer 1 (RCLK1) is used to clock all of the recovered data from both
deserializers into the client device. The recovered clock from deserializer two (RCLK2) is not connected.
Since the recovered data (Rdata2) from deserializer 2 is in phase with RCLK2, the phase difference
between RCLK 1 and RCLK 2 can be used to determine the timing constraints between data from
deserializer 2 and the RCLK from deserializer 1.
The total time for data passing through path 1 is the sum of the flight times of PCB traces and other
interconnections, and the delays of the serializer and deserializer.
Path 1 = A1 + B1 + C1 + E1 + F1
The total time for data through path 2 is the sum of the flight times and the delays through those devices.
Path 2 = A2 + B2 + C2 + E2 + F2
So the phase difference (Δφ) at the client receive is the difference of the overall delays in path 1 and path
2.
Δφ = (A1 + B1 + C1 + E1 + F1) – (A2 + B2 + C2 + E2 + F2)
2
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DETERMINING THE WORST CASE SKEW
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With careful PCB layout, the flight times within the two paths can be made so that A1 = A2, B1 = B2, and C1
= C2 now the phase difference contributed by these segments will be negligible and any phase difference
between the paths can be attributed solely to the serializer and deserializer delays tSD and tDD (E + F).
If (A1 + B1 + C1) = (A2 + B2 + C2)
then
Δφ = (E1 + F1) – (E2 + F2)
Δφ = (tSD1 + tDD1) – (tSD2 + tDD2)
2
DETERMINING THE WORST CASE SKEW
The worst case phase difference will occur when the minimum delays are experienced in the serializer
and deserializer in one path, the MIN path, and the maximum delays are experienced in the serializer and
deserializer in the other path, the MAX path. These worst case delays are specified by tSDmin and tSDmax for
the serializers and by tDDmin and tDDmax for the deserializers.
Δφ = (tSDmax + tDDmax) – (tSDmin + tDDmin)
The maximum skew between serial streams in an otherwise skew controlled design can be determined
using the maximum and minimum values of the Serializer Delay and Deserializer Delay parameters.
In Figure 1 RCLK1 (the recovered clock from deserializer 1) is selected as the reference clock for the
client receive device. All data presented to the client receive device is referenced to RCLK1. Assume that
Path 1 is the MIN path and has the SerDes pair with the minimum delay and that Path 2 is the MAX path;
its SerDes pair has the maximum delay. This means that RCLK2 and Rdata2 will trail RCLK1 by Δφ. The
setup time for Rdata2 will be degraded by as much as Δφ. See Figure 2.
Figure 2. RCLK and Rdata Timing
The assumption that Path 1 is the MIN path and Path 2 is the MAX path could be wrong however. In fact,
it could be that Path 1 is the MAX Path and Path 2 is the MIN path in which case RCLK1 will trail RCLK2
by Δφ. Now it is the hold time for Rdata2 that could be degraded by as much as Δφ. (Figure 2).
To be sure that either case is accounted for, both conditions must be considered. See Figure 2. If the
MAX path is chosen as the reference then the clock and data from the MIN path will lead the clock and
data from the MAX path by Δφ. The hold parameter of the MIN path data will be degraded by Δφ ns.
tROH′ = tROH − Δφ
Conversely, if the MIN path clock is chosen as the reference, then the MAX path clock and data will trail
the clock and data from the MIN path by Δφ. The setup parameter of the MAX path data will be degraded
by Δφ ns.
tROS′ = tROS + Δφ
NOTE: Since tROS is the data valid time before the reference clock it is specified as a negative
number. Therefore Δφ is added to tROS.
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DETERMINING THE WORST CASE SKEW
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Since the setup and hold parameters are specified in relation to the recovered clock period, it is
convenient to use only the delay portion of the Serializer Delay and Deserializer Delay parameters. Both
tSD and tDD are specified as a fractional number of clock cycles (xtCP and ytCP) plus a delay value (tS and tD).
tSDmin = xtCP + tSmin, tSDmax = xtCP + tSmax
tDDmin = ytCP + tDmin, tDDmax = ytCP + tDmax
So
Δφ = [(xtCP + tSmax) + (ytCP + tDmax)] − [(xtCP + tSmin) + ytCP + tDmin)]
Since the fractional clock cycle portion of the specs are proportional to the operating frequency they will be
the same for all devices of that type regardless of the operating frequency. This means that part of the
parameter value can be eliminated from the skew calculation. Rewriting the equation for the overall phase
difference and substituting for E and F, we can see that the overall difference in phase will be due to the
difference in delays through the serializers plus the difference in delays through the deserializers.
Δφ = (E1 + F1) − (E2 + F2)
Δφ = (E1 − E2) + (F1 − F2)
Δφ = (tSD1 − tSD2) + (tDD1 − tDD2)
Δφ = (tSDmax − tSDmin) + (tDDmax − tDDmin)
Δφ = [(xtCP + tSmax) − [(xtCP + tSmin)] + [(ytCP + tDmin) − (ytCP + tDmin)]
Since xtCP1 = xtCP2 and ytCP1 = ytCP2
Δφ = (tSmax – tSmin) + (tDmax – tDmin)
So the maximum timing inpact on any number of serial paths can be calculated as follows:
tROH′ = tROH – Δφ = tROH − [(tSmax − tSmin) + (tDmax − tDmin)]
and
tROS′ = tROS + Δφ = tROS + [(tSmax − tSmin) + (tDmax − tDmin)]
Table 1 summarizes the setup and hold time calculations for the 10-bit SerDes products at various
frequencies.
Table 1. Maximum Phase Difference and the Impact on Deserializer Output Timing (1)
Serializers
tSD
Range
tSMIN/tSMAX
DS92LV1021
0/5
Deserializers
DS92LV1212
A
1/3
DS92LV1023
1/3
DS92LV1224
1/3
(1)
tDD
Range
tDMIN/tDMAX
Δφ
16 MHz
62.5 ns
30 MHz
33.33 ns
40 MHz
25 ns
66 MHz
15.15 ns
1.25/6.25
10
15
2.12
0.0
N/A
1.25/6.25
7
N/A
5.12
3.0
−1.24
2.25/5.25
5
N/A
7.12
5.0
N/A
2.75/4.75
4
N/A
N/A
N/A
1.76
Within temperature specification for tSD and tDD. Much of the variation in deserializer delay is due to variation over temperature. The basic
tDD specification captures the entire range of variation. In application it is more likely that deserializers used in parallel will be located
close together and therefore subject to the same temperature. The Within Temperature specification can be used under such conditions.
Example: Using the DS92LV1023 and DS92LV1224 SerDes chipsets in parallel with a 40 MHz clock.
To calculate the maximum phase difference (Δφ) between two '1023/'1224 serial links refer to the
datasheet parameters tSD, tDD, tROS, tROH, and tRCP.
tSDMIN = tTCP + 1 ns
tSDMAX = tTCP + 3 ns
tDDMIN = 1.75 * tRCP + 1.25 ns
tDDMAX = 1.75 * tRCP + 6.25 ns
tRCP = 1/40 MHz = 25 ns
4
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CONCLUSION
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tROS = −0.4 * tRCP = −0.4 * 25 ns = −10 ns
tROH = 0.4 * tRCP = 0.4 * 25 ns = 10 ns
Plug the values into the equations for tROS' and tROH'.
Δφ = (tSmax − tSmin) + (tDmax − tDmin)
= (3 – 1) + (6.25 – 1.25) = 7 ns
tROH' = tROH − Δφ = 10 – 7 = 3 ns
tROS' = tROS + Δφ = (−10) + 7 = −3 ns
Therefore if the Client Receive ASIC supports a input set/hold of −3/+3 ns, then the timing is validated.
If the assumption that the SerDes pairs will all be at the same temperature is valid, then the Within
Temperature specifications can be used to get wider setup and hold numbers.
tSDMIN = tTCP + 1 ns
tSDMAX = tTCP + 3 ns
tDDMIN = 1.75 * tTCP + 2.25 ns
tDDMAX = 1.75 * tTCP + 5.25 ns
Δφ = (tSmax − tSmin) + (tDmax − tDmin)
= (3 – 1) + (5.25 – 2.25) = 5 ns
tROH' = tROH − Δφ = 10 – 5 = 5 ns
tROS' = tROS + Δφ = (−10) + 5 = −5 ns
Therefore if the client receive device supports a input set/hold of −5/+5 ns, then the timing is validated.
3
CONCLUSION
For any parallel arrangement of BLVDS SerDes pairs (where the flight times throughout the path have
been controlled) the maximum phase difference between any deserializer output to another deserializer
output will occur when the serializer and deserializer in one path both have a minimum delay while the
serializer and deserializer in the other path both have the maximum delay. The parameters tSD and tDD
specify the minimum and maximum delays for BLVDS SerDes devices. Some of the delay variation can
be eliminated by using the Within Temperature specifications. Parallel arrangements are feasible and
greatly depend upon the clock rate and the required set/hold time at the client receive device. In practice
clock rates up to 50–60 MHz may be supported depending upon the system timing.
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