Texas Instruments | AN-259 DS3662-The Bus Optimizer | Application notes | Texas Instruments AN-259 DS3662-The Bus Optimizer Application notes

Texas Instruments AN-259 DS3662-The Bus Optimizer Application notes
DS3662
Application Note 259 DS3662-The Bus Optimizer
Literature Number: SNLA139
National Semiconductor
Application Note 259
R. V. Balakrishnan
April 1981
I. INTRODUCTION
A single ended Bus is an unbalanced Data Transmission medium, which is timeshared by several system elements. Like
any unbalanced system, it is highly susceptible to
common-mode noise, such as ground noise and crosstalk.
In general, the latter determines the maximum physical
length of the Bus that can be incorporated with acceptable
reliability. Crosstalk is a major problem in high speed computer Buses which employ Schottky Transceivers for increased data rate capability. It is therefore highly desirable to
minimize crosstalk noise in Bus circuits to allow for longer
Buses and to provide higher system reliability.
This article describes the operation of the DS3662 Quad
High Speed Trapezoidal Bus Transceiver, which has been
specially designed to minimize crosstalk problems. The
Driver generates precise Trapezoidal waveforms that reduce
noise coupling to adjacent Bus channels. The Receiver uses
a low pass filter, whose time constant is matched to the
Driver slew rate to provide maximum noise rejection with acceptable signal delay characteristics. Precision high speed
circuitry optimizes noise immunity without sacrificing the high
data rate capability of Schottky Transceivers.
crosstalk. Crosstalk also includes noise induced by sources
external to the Bus. Additional noise may be generated due
to reflections at imperfect terminations.
Bus Receviers are designed to respond to high speed transitions and to provide low propagation delays. Unfortunately,
their fast response results in high noise sensitivity. The combined effect of the noise on the Bus and the sensitivity of the
Receiver to the noise severely limits the Bus performance.
II. THE PROBLEM
Conventional Bus Drivers are designed to provide high output currents for charging and discharging relatively large Bus
capacitances quickly. These high speed transitions are characterized by peak slew rates of up to 5V/ns around the
mid-region of the transition. This can cause considerable
noise coupling to adjacent lines, commonly referred to as
III. THE SOLUTION
The above situation can be considerably improved by employing noise reduction techniques in both the Driver and the
Receiver circuits. Slew rate control can be used in the Driver
to reduce crosstalk, and Receiver noise sensitivity can be reduced by using a low pass filter at its input. These techniques are commonly used in line transmission circuits
where the associated data rates in general are considerably
lower. However, these techniques do present some difficulties in high speed Bus circuits. Increased rise and fall times,
resulting from slew rate control, can affect data rates unless
care is taken to limit the maximum rise and fall times to minimum pulse width requirements. With any appreciable slew
rate control, the rise and fall times of the resulting Driver output waveform will be comparable to the pulse widths at maximum data rates. This condition dictates high fidelity of the
transmitted waveform and precise Receiver thresholds at the
middle of the Bus voltage swing in order to minimize pulse
width distortion. Figure 1 illustrates the different sources of
pulse width distortion due to the trapezoidal nature of the
signal.
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DS3662— The Bus Optimizer
DS3662— The Bus
Optimizer
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FIGURE 1. Pulse Width Distortion
© 1999 National Semiconductor Corporation
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transitions in order to maintain a low level of pulse width distortion, as well as equal noise rejection to positive and negative going noise pulses. The response of an ideal low pass
filter to signal and noise pulses is shown in Figure 2.
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AN-259
The low pass filter in the Receiver should provide optimum
noise rejection without introducing excessive delay in passing the signal waveform. In addition, the Receiver should
have a symmetrical response to positive and negative going
be noted that even under heavy loading, the regular Drivers
have peak slew rates that are considerably higher than the
average. In contrast, the trapezoidal waveform provides considerably lower slew rate with slightly higher rise and fall
times. Such an increase in rise and fall time has very little effect on data rates. In fact, the high fidelity of the transmitted
waveform allows pulse widths as low as 20 ns to be transmitted on the Bus, as shown in Figure 5.
The block diagram of the Driver is shown in Figure 6 and Figure 7. When a high to low transition is applied to the input,
switch ‘S’ opens and node ‘A’ is pulled low by the current
source ‘I’. This switches the amplifier output to a high state.
The slew rate of the output transition is limited by the charging current through the capacitor, a constant value equal to
I/C volts/sec.
The DS3662 overcomes these and other problems by using
high speed linear circuitry with on-chip capacitors for controlling slew rate and low pass filtering. The Driver is of open
collector type intended for use with terminated 120Ω Buses.
The external termination consists of a 180Ω resistor from the
Bus to +5V logic supply with a 390Ω resistor from the Bus to
ground. Such a termination results in a Bus logic high level of
3.4V with VCC at 5V (See Figure 2 ). The Bus can be terminated at one or both ends as shown in Figure 3.
IV. THE DRIVER
Using a Miller integrator circuit, the Driver generates a linearly rising and falling waveform with a constant slew rate of
0.2V/ns (typical) during the entire period of transition. This
corresponds to typical rise and fall times of 15 ns. Figure 4
compares the output waveform of a typical Schottky Driver
and the DS3662 under different capacitive loads. It should
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FIGURE 2. Ideal Receiver Low Pass Filter Response
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FIGURE 3. Bus Termination
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2
inherent tracking ability of I.C. current sources provide equal
rise and fall times resulting in a symmetrical output waveform.
The on-chip capacitors are fabricated using back to back
junction diodes. The use of junction capacitors reduces die
area and the back to back connection allows operation with
either polarity. The capacitor terminal, connected to the amplifier input, remains at Vth ≅ 1.6V during the output transition. This voltage, being close to the middle of the output
swing, reduces the effect of the capacitor voltage sensitivity
on the output waveshape.
AN005857-5
1 — Typical High Speed Driver Output Unloaded
2 — Typical High Speed Driver Output Loaded
3 — Typical Output of Controlled Slew Rate Driver Which is Load
Independent
Note: The word “loading” here refers to capacitive loading only.
V. THE RECEIVER
The Receiver consists of a low pass filter followed by a high
speed comparator with a typical threshold of 1.7V (see Figure 8). This threshold value corresponds to the mid-point
voltage of the 0 to 3.4V Bus swing. It is derived from a potential divider allowing the Bus logic levels to track with VCC
variations. If the low pass filter capacitor is voltage insensitive, this circuit will provide equal propagation delay for positive and negative going signal transitions on the Bus. In addition, it will also provide equal noise rejection to a positive
and negative going pulse (see Figure 2). However, the junction capacitors, being voltage sensitive, will exhibit
non-symmetrical response in the above circuit. This problem
is overcome in the DS3662 Receiver by using a back to back
junction capacitor with the ground end biased at 1.7V (see
Figure 9). Although the capacitor still varies with the voltage
at node ‘A’, the variation is symmetrical about 1.7V (the
middle of the Bus swing) and therefore will provide an identical response to transitions of either polarity.
FIGURE 4. Waveform Comparison
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tpm ≈ 20 ns
tr ≈ tf ≈ 15 ns
(10% to 90%)
FIGURE 5. Minimum Pulse Width Driver Output
VI. TRANSCEIVER PERFORMANCE
The characteristics of the trapezoidal Transceiver are fully
detailed in the device data sheet. Some of the more important specifications are discussed below. Both AC and DC
specifications are guaranteed over a 0–70˚C temperature
range and a supply range of 4.75–5.25V.
The Driver typically has a propagation delay of 15 ns with a
maximum of 30 ns. The Receiver propagation delays are
specified at 25 ns typical and 40 ns maximum. The Driver
output rise and fall times are guaranteed to be within 10 to
20 ns with a typical of 15 ns. The noise immunity of the Receiver is specified in terms of the width of a 2.5V pulse that
is guaranteed to be rejected by the Receiver (see Figure 10).
The Receiver typically rejects a 20 ns pulse going positive
from ground level or going negative from a 3.4V logic 1 level.
Worst case rejection is specified at 10 ns.
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FIGURE 6. Driver
AN005857-8
FIGURE 7. Driver
Likewise, when a low to high transition is applied to the input,
switch “S” closes and node “A” is pulled up by the “21” current source, switching the amplifier output to a low state. The
capacitor now has an equal but opposite charging current
which once again limits the slew rate to −I/C volts/sec. The
3
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AN005857-9
AN005857-10
FIGURE 8. Receiver
FIGURE 9. Receiver
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Rejects positive or negative going noise pulses of pulse widths up to 20 ns typical.
Detects and propagates trapezoidal signal pulses in 20 ns typical.
FIGURE 10. Receiver Noise Immunity
less than 10 feet. In contrast, the DS3662’s Driver generates
much less crosstalk and its Receiver is immune to the induced noise even when the noise amplitude exceeds the
signal amplitude as seen in the oscillogram at 50 feet. When
the same experiment was repeated with the DS8641, it responded to the noise even at 10 feet as shown in Figure 14.
Figure 15 shows the plots of maximum data rate versus line
length for the three Transceivers discussed above under two
different conditions. The graph in Figure 15 is obtained with
no consideration to the pulse width distortion whereas the
one in Figure 15 is obtained for a maximum allowable pulse
width distortion of ± 10%. A square waveform is used so that
the pulse width distortion criteria will apply to both positive
and negative going pulses. These graphs clearly show that
the DS3662 can be used at considerably higher data rates
with lower distortion for longer distances than the other two
Transceivers (Figure 15) although the others have a slightly
higher data rate capability at short distances with high timing
distortion (Figure 15).
The AC response of the DS3662 Driver and Receiver are depicted in Figure 11 and Figure 12 respectively. Figure 11
shows the typical Driver output waveform as compared to a
standard high speed Transceiver output. Oscillograms in
Figure 12 demonstrate the ability of the Receiver to distinguish the trapezoidal signal from the noise. Here the Receiver rejects a noise pulse of 19 ns width, while accepting a
narrower signal pulse ( = 16 ns) of the same amplitude (The
signal is triangular since the pulse width is smaller than the
rise and fall time of the Trapezoidal Driver output).
The performance of the Transceiver under actual operating
condition is demonstrated in Figure 13 through Figure 15.
Oscillograms in Figure 13 clearly show the capability of the
DS3662 in real life situations. Here it is compared with the
DS8834 under identical conditions. The Transceivers drive a
minicomputer Bus (flat ribbon cable) 100 feet long, terminated at the far end with taps at various lengths for connecting to the Receiver input. The cable is randomly folded to
generate crosstalk between the various parts. In addition a
noise pulse is induced on the signal line by driving an adjacent line with a pulse generator. This corresponds to the second dominant pulse in the Bus waveforms at approximately
600 ns from the main signal pulse. As can be seen, the
DS8834 with fast rise and fall times on the Driver output generates more crosstalk and its Receiver easily responds to
this crosstalk and to the externally induced noise (even
though it has hysteresis!), limiting the useful Bus length to
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VII. CONCLUSION
The DS3662, with its combination of a trapezoidal Driver and
a noise rejecting Receiver utilizing on chip capacitors, represents a significant improvement in high speed Bus circuits
and a solution to Bus noise problems commonly encountered in Mini and Microcomputer systems.
4
Typical High Speed Bus Driver Output Waveforms DS3662 — Trapezoidal Driver Output Waveform
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FIGURE 11.
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FIGURE 12. DS3662 Receiver Response
5
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DS8834 DS3662
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FIGURE 13.
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6
DS8641
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FIGURE 14.
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FIGURE 15. Data Rate vs. Line Length
7
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DS3662— The Bus Optimizer
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AN-259
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