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Texas Instruments LMH1297EVM (Rev. A) User guides
User's Guide
SNAU205A – March 2017 – Revised August 2019
LMH1297EVM Evaluation Board
The LMH1297EVM is an evaluation module designed for high-speed performance and functional
evaluation of the Texas Instruments LMH1297 12G UHD-SDI 75-Ω bidirectional I/O with integrated
reclocker. With this kit, users can quickly evaluate the cable reach and output signal integrity supported by
the LMH1297. High-performance edge-mount BNC connectors are used at the 75-Ω port for the SDI_IO
and SDI_OUT signals, while 100-Ω differential input and output ports are routed to edge-mount SMA
connectors. These connectors facilitate connection to lab equipment or user systems for performance
evaluation. An onboard MSP430 MCU is included to support an optional SMBus or SPI serial control
interface when configuring the LMH1297 operating modes.
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Contents
Overview ...................................................................................................................... 2
Features ....................................................................................................................... 3
Applications ................................................................................................................... 3
Ordering Information ........................................................................................................ 3
Setup .......................................................................................................................... 4
5.1
Modes of Operation ................................................................................................ 5
5.2
Software/Hardware Description and Setup ...................................................................... 7
5.3
Retimed Output at 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, and 270 Mbps ................... 11
SigCon Architect LMH1297 GUI Profile ................................................................................. 13
6.1
Configuration Page ................................................................................................ 13
6.2
Low Level Page ................................................................................................... 14
6.3
High Level Page ................................................................................................... 15
6.4
Eye Monitor Page ................................................................................................. 18
Bill Of Materials ............................................................................................................. 19
Schematics .................................................................................................................. 21
EVM Layout ................................................................................................................. 23
List of Figures
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LMH1297EVM ................................................................................................................ 2
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LMH1297EVM Input and Output Pins..................................................................................... 4
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Jumper Orientation for User Configuration ............................................................................... 5
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LMH1297EVM CD Mode Default Setup for SMBus Operation With SigCon Architect
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LMH1297EVM EQ Mode Default Setup for SMBus Operation With SigCon Architect ........................... 10
CD Mode at 11.88 Gbps, Measured at SDI_IO+, Reclocked Output ............................................... 11
EQ Mode at 11.88 Gbps, Measured at OUT0±, Reclocked Output ................................................. 11
CD Mode at 5.94 Gbps, Measured at SDI_IO+, Reclocked Output ................................................. 11
EQ Mode at 5.94 Gbps, Measured at OUT0±, Reclocked Output ................................................... 11
CD Mode at 2.97 Gbps, Measured at SDI_IO+, Reclocked Output ................................................. 11
EQ Mode at 2.97 Gbps, Measured at OUT0±, Reclocked Output ................................................... 11
CD Mode at 1.485 Gbps, Measured at SDI_IO+, Reclocked Output ............................................... 12
EQ Mode at 1.485 Gbps, Measured at OUT0±, Reclocked Output ................................................. 12
CD Mode at 270 Mbps, Measured at SDI_IO+, Reclocked Output.................................................. 12
EQ Mode at 270 Mbps, Measured at OUT0±, Reclocked Output ................................................... 12
LMH1297EVM Configuration Page ..................................................................................... 13
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Overview
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17
LMH1297EVM Low Level Page .......................................................................................... 14
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LMH1297EVM High Level Page
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Macro Utility Syntax ........................................................................................................ 16
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Macro Utility Example
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Macro Utility Example Log File ...........................................................................................
LMH1297EVM Eye Monitor Page ........................................................................................
LMH1297 Schematic Page ...............................................................................................
MSP430 USB2ANY Schematic Page ...................................................................................
LMH1297EVM Top Layer .................................................................................................
LMH1297EVM Bottom Layer .............................................................................................
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List of Tables
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Description of 4-Level Voltage Inputs and Jumper Ties ...............................................................
Description of Connections in SPI Mode (MODE_SEL = Level F) ...................................................
Description of Connections in SMBus Mode (MODE_SEL = Level L) ...............................................
Input and Output Channel Connections ..................................................................................
LMH1297 Ordering Information
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Trademarks
All trademarks are the property of their respective owners.
1
Overview
Figure 1. LMH1297EVM
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Features
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2
Features
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Applications
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User-Configurable Adaptive Cable Equalizer or Cable Driver With Integrated Reclocker
Supports ST-2082-1 (12G), ST-2081-1 (6G), ST-424 (3G), ST-292 (HD), and ST-259 (SD)
Integrated Reclocker Locks to SMPTE Video Rates of 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps
or Divide-by-1.001 Sub-Rates and 270 Mbps
EQ (Equalizer) Mode:
– Adaptive Cable Equalizer at 75-Ω Single-Ended Input on SDI_IO
– 100-Ω Output Driver With De-Emphasis on OUT0
– Line-Side Reclocked 75-Ω Loop-Through Output on SDI_OUT
CD (Cable Driver) Mode:
– PCB Equalizer at 100-Ω Differential Input on IN0
– Dual Cable Drivers with Integrated Reclocker and Pre-Emphasis on SDI_IO and SDI_OUT
– Host-Side Reclocked 100-Ω Loop-Back Output on OUT0
Programmable Through Pins, SPI, or SMBus Interface
Single-Supply Operation: VDD = 2.5 V ± 5%
–40°C to +85°C Operation
High-Speed Signal Flowthrough Pinout Package: 5-mm × 5-mm 32-Pin QFN
SMPTE-Compatible Serial Digital Interface
UHDTV/4K/8K/HDTV/SDTV Video
IP Media Gateway
Digital Video Processing and Editing
Ordering Information
Table 1. LMH1297 Ordering Information
EVM ID
DEVICE ID
DEVICE PACKAGE
LMH1297EVM
LMH1297RTV
QFN (32)
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Setup
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Setup
This section describes the jumpers and connectors on the EVM as well as how to connect, set up, and
use the LMH1297EVM. When operating the LMH1297EVM, signal inputs and outputs can be connected
as shown in Figure 2.
OUT0+
SDI_IO+
OUT0-
IN0+
SDI_OUT+
IN0-
Mini-USB Port
Connection to PC
Figure 2. LMH1297EVM Input and Output Pins
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5.1
Modes of Operation
The LMH1297EVM can be used in one of three modes:
1. Pin Mode (Default) – Provides general access to the LMH1297 signal integrity and I/O control settings
with IC pin-level logic.
2. SPI Mode – Provides full access to the LMH1297 signal integrity and control settings with MISO,
MOSI, SCK, and SSN pins.
3. SMBus Mode – Provides full access to the LMH1297 signal integrity and control settings with SDA,
SCL, and GND pins. ADDR0 and ADDR1 pins are used for SMBus address strap.
Using either SPI or SMBus mode, users have full access to all register controls in the LMH1297. For
convenience, the LMH1297EVM features an on-chip MSP430 that is configured as a USB2ANY interface
between LMH1297 and PC through the mini-USB port header on J31.
NOTE: Currently, the interface from PC to on-board MSP430 can only support SMBus
communication.
The external control pins on the LMH1297EVM are used to configure the default device settings. A 4-level
input scheme across the control pin interface increases the amount of control levels available to the
device with fewer physical pins. The channel settings and controls are configurable in pin mode for the
LMH1297 4-logic levels (L, R, F, H). The four logic levels correspond to the following voltages in Table 2.
Table 2. Description of 4-Level Voltage Inputs and Jumper Ties
LEVEL
SETTING
NOMINAL PIN VOLTAGE
H
Tie 1 kΩ to VIN
VIN – 0.04 V
F
Float (Leave Pin Open)
2/3 × VIN
R
Tie 20 kΩ to GND
1/3 × VIN
L
Tie 1kΩ to GND
0.08 V
Typical 4-Level Input Thresholds:
• Internal Threshold between L and R = 0.2 × VIN
• Internal Threshold between R and F = 0.5 × VIN
• Internal Threshold between F and H = 0.8 × VIN
To set these 4-level voltage inputs, each input is controlled by a group of 6 jumper pins set in Figure 3.
1 lQ š} s/E
(Level H)
1
2
GND
(Not Valid)
Input Pin
3
4
Input Pin
1 lQ š} 'E
(Level L)
5
6
20 lQ š} 'E
(Level R)
Figure 3. Jumper Orientation for User Configuration
Therefore, the following jumper positions allow access to each of the four logic levels:
LEVEL
JUMPER TIES
H
Pin 1-3
F
Pin 3-4 (or no connect)
R
Pin 4-6
L
Pin 3-5
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The following jumpers have 4-level input control: J10, J11, J12, J13, J14, J15, J16, J17, J18, and J19.
In Pin Mode, EQ/CD_SEL, OUT0_SEL, HOST_EQ0, OUT_CTRL, SDI_VOD, and SDI_OUT_SEL pins
control different LMH1297 settings. Using SPI or SMBus, these initial pin control values can be overridden
by setting the appropriate override bits through register control. Both SPI and SMBus interfaces allow full
control over a wide range of device settings. See Table 3 and Table 4 for jumper descriptions and
differences.
Table 3. Description of Connections in SPI Mode (MODE_SEL = Level F)
COMPONENT
NAME
COMMENTS
J1
GND
GND power supply
J2
VDD_CDR
2.5-V VDD_CDR power supply
J3
VIN
2.5-V VIN power supply
J4
VIN_VDD_CDR_Connect
2.5-V power supply. Shunt Pin 1 and 2 to tie VIN and VDD_CDR.
J5
ENABLE
Enable Pin for the LMH1297. Shunt Pin 1 and 2 for proper
operation. Refer to LMH1297 data sheet for detailed information.
J6
SPI_MISO
Shunt Pin 1 and 2 to connect MISO signal to J8 for proper SPI mode
operation.
J7
LOCK_N
Reclocker lock indicator for the selected input. Shunt Pin 1 and 2 for
proper operation. Refer to LMH1297 data sheet for detailed
information.
J8
SPI Access
SPI access pins. See datasheet and EVM schematic for detailed
pinout information.
J9
SPI Access
For SPI mode, install Pin 1-2, 3-4, and 5-6 for SPI 3.3-V to 2.5-V
level shift. Leave Pin 7-10 open.
See the data sheet for additional information on SPI operation.
J10
EQ_CD_SEL
EQ_CD_SEL pin selects the I/O direction. See the data sheet and
EVM schematic for additional operation information.
J11
OUT0_SEL
OUT0_SEL pin enables or disables the OUT0 100-Ω output. See
datasheet and EVM schematic for additional operation information.
J12
HOST_EQ0
HOST_EQ0 pin selects the IN0 100-Ω EQ Adaption Mode settings
and OUT0 100-Ω driver output amplitude and de-emphasis level.
See the data sheet and EVM schematic for additional operation
information.
J13
MODE_SEL
Level F: SPI Mode
OUT_CTRL
OUT_CTRL selects the signal flow from the selected IN port to the
enabled outputs. It selects reclocked data, reclocked data and clock,
bypass reclocker (equalized data route to output driver), or both
equalizer and reclocker bypassed. See the data sheet and EVM
schematic for additional operation information.
J15
SDI_VOD
SDI_VOD selects incremental increase or decrease of nominal
driver output amplitude applied to the SDI_IO (CD Mode) and
SDI_OUT 75-Ω outputs. See the data sheet and EVM schematic for
additional operation information.
J16
SS_N
Slave Select. When SS_N is at logic low, it enables SPI access to
the LMH1297 slave device.
J17
MISO
MISO is the SPI serial control data output from the LMH1297 slave
device. MISO is a 2.5-V LVCMOS output.
J18
SDI_OUT_SEL
SDI_OUT_SEL pin enables or disables the SDI_OUT 75-Ω output.
See the data sheet and EVM schematic for additional operation
information.
J19
RSV1
Reserved. Do not connect. Leave floating.
J14
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Table 4. Description of Connections in SMBus Mode (MODE_SEL = Level L)
COMPONENT
NAME
COMMENTS
J6
SPI_MISO
Leave Pin 1 and 2 open for proper SMBus operation.
J8
SMBus Access
SMBus access pins. See the data sheet and EVM schematic for detailed
pinout information.
J9
SMBus Access
External 2-kΩ pullup resistor to 3.3-V supply. Install shunt jumpers on Pin
7-8 and 9-10 for proper operation. Leave Pins 1-6 open.
See the data sheet for additional information on SMBus operation.
J13
MODE_SEL
Level L: SMBus Mode
J16
ADDR0
4-Level strap pins to determine up to 16 unique SMBus address with J17
to create AD[1:0]. See the data sheet for different SMBus address
combinations.
J17
ADDR1
4-Level strap pins to determine up to 16 unique SMBus address with J16
to create AD[1:0]. See the data sheet for different SMBus address
combinations.
NOTE: Jumpers not listed in Table 4 are identical to the functions mentioned in Table 3.
Table 5. Input and Output Channel Connections
SIGNAL INPUTS AND OUTPUTS
5.2
JUNCTION NUMBERS
FUNCTION
J20
SDI_IO+ (BNC Single-Ended)
J21
SDI_OUT+ (BNC Single-Ended)
J22, J23
OUT0+, OUT0– (SMA)
J24, J25
IN0+, IN0– (SMA)
Software/Hardware Description and Setup
By factory default, the LMH1297EVM is configured in CD Mode to accept a valid SDI signal on IN0 and
output the retimed data on OUT0, SDI_IO, and SDI_OUT without programming the LMH1297 beforehand.
The LMH1297EVM can also be configured by the user to operate in EQ Mode.
The general procedure for setting up and testing with the LMH1297EVM is as follows. For hardware setup
and connections in the steps below, reference the illustrations in Figure 4 and Figure 5.
1. Connect 2.5-V power (0.5-A maximum) to the EVM and install the appropriate shunt jumpers to
operate in SMBus Mode:
1. Connect J3: VIN = 2.5 V and J1: GND.
1. Install shunt jumper on J4 Pins 1-2.
2. Set the following jumper settings for appropriate operation:
1. Install shunt jumper on J5 Pins 1-2.
2. Install shunt jumper on J7 Pins 1-2.
3. Install shunt jumpers on J9 Pins 7-8 and Pins 9-10.
4. Install shunt jumper on J11 Pins 3-5.
5. Install shunt jumper on J13 Pins 3-5.
6. Install shunt jumper on J16 Pins 3-5 and J17 Pins 3-5. (SMBus Address = 0x5A)
7. Install shunt jumper on J18 Pins 3-5.
3. CD Mode Only: Install shunt jumper on J10 Pins 1-3.
4. EQ Mode Only: Install shunt jumper on J10 Pins 3-5.
2. Connect PC to LMH1297EVM with a USB-to-miniUSB cable through the miniUSB port located on J31.
The LMH1297's control and signal integrity settings are programmable with SigCon Architect, a GUI
which supports full register access through SMBus communication. For more information about SigCon
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Architect, reference the SigCon Architect: Installation and Starter's Guide.
3. CD Mode Only: Connect the LMH1297EVM to the system under test.
1. The input signal on J24 and J25 can be connected to a video signal generator over matched 100Ω differential cables. Either an LMH1219EVM or a second LMH1297EVM in EQ Mode can be used
as a 75-Ω single-ended to 100-Ω differential converter before the DUT. In this case, either the
LMH1219's 100-Ω OUT0± output or the second LMH1297's 100-Ω OUT0± output can be
connected to IN0± on J24 and J25.
2. The output signal OUT0± on J22 and J23 can be connected with matched 100-Ω differential cables
to a high-speed scope to view the output eye diagram. Alternatively, this 100-Ω output can be used
as the source for another SDI cable driver.
3. The output signals on J20 and J21 are dual cable driver outputs. SDI_IO+ on J20 can be
connected with 75-Ω coax cable to a video pattern analyzer, while the secondary SDI_OUT+
output on J21 can be used as a duplicate cable driver output.
4. EQ Mode Only: Connect the LMH1297EVM to the system under test.
1. The input signal on J20 can be connected to a video signal generator over a 75-Ω coax cable.
Either an LMH1218EVM or a second LMH1297EVM in CD Mode can be used as a 100-Ω
differential to 75-Ω single-ended converter before the DUT. In this case, either the LMH1218's 75Ω OUT0+ output or the second LMH1297's 75-Ω SDI_IO+ output can be connected to SDI_IO+ on
J20.
2. The output signal OUT0± on J22 and J23 can be connected with matched 100-Ω differential cables
to a high-speed scope to view the output eye diagram.
3. The output signal SDI_OUT+ on J21 can be connected with a 75-Ω coax cable to a video pattern
analyzer as a loop through output.
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GND
2.5-V Power
Supply
= Shunt Jumper Connection
OUT0+
Primary Output to Video Pattern
Analyzer over 75-Q ^]vPo -ended
Coax Cable
75-Q ^]vPo -ended
Coax Cable
SDI_IO+
OUT0-
100-Q D š Z
Differential Coax Cables
DCAJ or Equivalent
Oscilloscope
(For Eye Monitor and
Jitter Decomposition)
100-Q D š Z
Differential Coax Cables
Video Pattern
Generator Output
OR
LMH1219 OUT0±
IN0+
Secondary Output to Video
Pattern Analyzer over 75-Q
Single-ended Coax Cable
75-Q ^]vPo -ended
Coax Cable
SDI_OUT+
IN0-
Control Pin Configuration Notes:
J10 (EQ/CD_SEL) = Level H
x LMH1297 placed in CD Mode. I/O configured as output.
x SDI_IO EQ automatically powered down
J11 (OUT0_SEL) = Level L
x OUT0 powered up and enabled.
J12 (HOST_EQ0) = Level F
x IN0 EQ set to normal adaptive operation
x Set OUT0 VOD = 570 mVpp, DE = -0.4 dB.
J13 (MODE_SEL) = Level L
x Operate in SMBus Mode
J14 (OUT_CTRL) = Level F
x Reclocked data path (EQ and Reclocker Enabled) on
both OUT0± and SDI_OUT+.
J15 (SDI_VOD) = Level F
x Output nominal VOD on SDI_IO and SDI_OUT (800
mVpp)
J16, J17 (ADDR0, ADDR1) = Level L
x ADDR[1:0] = 00'b, meaning 7-bit slave address 0x2D, or
8-bit address (with Write Command) 0x5A.
J18 (SDI_OUT_SEL) = Level L
x SDI_OUT powered up and enabled.
PC can be used to communicate with LMH1297
via SMBus Mode.
USB-to-miniUSB Cable
Figure 4. LMH1297EVM CD Mode Default Setup for SMBus Operation With SigCon Architect
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GND
2.5-V Power
Supply
= Shunt Jumper Connection
OUT0+
Video Pattern Generator over
75-Q ^]vPo -ended Coax Cable
OR
LMH1218 OUT0+ Output
75-Q ^]vPo -ended
Coax Cable
Video Pattern Analyzer over 75-Q
Single-ended Coax Cable
75-Q ^]vPo -ended
Coax Cable
SDI_IO+
OUT0-
SDI_OUT+
100-Q D š Z
Differential Coax Cables
DCAJ or Equivalent
Oscilloscope
(For Eye Monitor and
Jitter Decomposition)
IN0+
IN0-
Control Pin Configuration Notes:
J10 (EQ/CD_SEL) = Level L
x LMH1297 placed in EQ Mode. I/O configured as input.
x IN0 automatically powered down
J11 (OUT0_SEL) = Level L
x OUT0 powered up and enabled.
x In EQ Mode, OUT0 is always enabled.
J12 (HOST_EQ0) = Level F
x IN0 EQ settings ignored, since IN0 is powered down.
x Set OUT0 VOD = 570 mVpp, DE = -0.4 dB.
J13 (MODE_SEL) = Level L
x Operate in SMBus Mode
J14 (OUT_CTRL) = Level F
x Reclocked data path (EQ and Reclocker Enabled) on
both OUT0± and SDI_OUT+.
J15 (SDI_VOD) = Level F
x Output nominal VOD on SDI_OUT (800 mVpp)
J16, J17 (ADDR0, ADDR1) = Level L
x ADDR[1:0] = 00'b, meaning 7-bit slave address 0x2D, or
8-bit address (with Write Command) 0x5A.
J18 (SDI_OUT_SEL) = Level L
x SDI_OUT powered up and enabled.
PC can be used to communicate with LMH1297
via SMBus Mode.
USB-to-miniUSB Cable
Figure 5. LMH1297EVM EQ Mode Default Setup for SMBus Operation With SigCon Architect
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5.3
Retimed Output at 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, and 270 Mbps
The eye diagrams in the left column of this subsection show the reclocked output eye of SDI_IO+ in CD
Mode under the following conditions:
• Input Signal: PRBS-10, 800-mVp-p Launch Amplitude on IN0±
• VIN = 2.5 V, T = 25°C
The eye diagrams in the right column of this subsection show the reclocked output eye of differential
OUT0± in EQ Mode under the following conditions:
• Input Signal: PRBS-10, 800-mVp-p Launch Amplitude on SDI_IO+
• VIN = 2.5 V, T = 25°C
Figure 6. CD Mode at 11.88 Gbps, Measured at SDI_IO+,
Reclocked Output
Figure 7. EQ Mode at 11.88 Gbps, Measured at OUT0±,
Reclocked Output
Figure 8. CD Mode at 5.94 Gbps, Measured at SDI_IO+,
Reclocked Output
Figure 9. EQ Mode at 5.94 Gbps, Measured at OUT0±,
Reclocked Output
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Figure 10. CD Mode at 2.97 Gbps, Measured at SDI_IO+,
Reclocked Output
Figure 11. EQ Mode at 2.97 Gbps, Measured at OUT0±,
Reclocked Output
Figure 12. CD Mode at 1.485 Gbps, Measured at SDI_IO+,
Reclocked Output
Figure 13. EQ Mode at 1.485 Gbps, Measured at OUT0±,
Reclocked Output
Figure 14. CD Mode at 270 Mbps, Measured at SDI_IO+,
Reclocked Output
Figure 15. EQ Mode at 270 Mbps, Measured at OUT0±,
Reclocked Output
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SigCon Architect LMH1297 GUI Profile
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6
SigCon Architect LMH1297 GUI Profile
SigCon Architect GUI can be used to access the LMH1297 register controls easily. There are four pages
associated with the LMH1297 profile:
• Configuration Page
• Low Level Page
• High Level Page
• Eye Monitor Page
This section provides a brief overview of the LMH1297 GUI profile.
6.1
Configuration Page
The Configuration Page is the first page of the SigCon Architect LMH12097 GUI. In this page, the user
can control the following:
• Change the Slave Address
• Toggle MSP430 LED
• Enable or Disable Demo Mode
Figure 16 shows the Configuration Page.
Figure 16. LMH1297EVM Configuration Page
To configure a live LMH1297 using the GUI, the following steps should be taken:
1.
2.
3.
4.
5.
Connect the LMH1297EVM through a USB cable to the PC.
Select the USB2ANY Device in the USB2ANY Details drop-down menu.
Select the correct LMH1297 Slave Address (this can be verified and modified with J16 and J17).
Uncheck the Demo Mode Checkbox. Click Apply.
Verify that the status indicator at the bottom right of the GUI turns green and displays CONNECTED.
NOTE: In Demo Mode, the Apply button must still be clicked to unlock the Low Level, High Level,
and Eye Monitor Pages of the GUI.
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6.2
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Low Level Page
The Low Level Page allows the user to access the LMH1297 registers individually. This page is described
in two main sections:
• Register Map
• Field Description
Figure 17 shows the Low Level Page.
Figure 17. LMH1297EVM Low Level Page
6.2.1
Register Map
The Register Map section contains the three main register pages: Shared Registers, CTLE-CDR
Registers, and Config IO Registers. Within these register pages, the following can be observed:
• Name of each register
• Each register's address and default value
• Register accessibility as read-only or read/write
The register value can be overwritten by typing the desired value in either the Data box or by clicking the
appropriate checkboxes in the top right of the Low Level Page. Only bits that are read/write accessible can
be modified.
6.2.2
Field Description
The Field Description section allows the user to view the detailed name, access type, and description for
the register selected from the Register Map section.
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6.3
High Level Page
The High Level Page provides an intuitive control interface with a simplified block diagram of the
LMH1297. This page is described in two main sections:
• High Level Interface
• Macro Scripting Utility
Figure 18 shows the High Level Page.
Figure 18. LMH1297EVM High Level Page
6.3.1
High Level Interface
This interface is dynamic and allows the user to view and control a variety of functions in the LMH1297
concurrently. In this page, the user can easily control functions such as the following:
• Configure the LMH1297 as CD or EQ Mode
• Power Up or Down Different Output Channels
• Modify the Signal Output from the Output Mux
• Reset the CDR
• Change the IN0 CTLE Index Boost Value
NOTE: Configuration pins SDI_OUT_SEL, OUT0_SEL, and EQ_CD_SEL will be overwritten with
the default values displayed on the High Level Page when first loading SigCon Architect.
These configuration pins are also overwritten by the High Level Page values any time the
Apply button is clicked. By default, SDI_OUT_SEL is powered down, OUT0_SEL is powered
up, and EQ_CD_SEL is set low (EQ Mode) by the GUI.
NOTE: Right-clicking the Cable Driver and OUT0 blocks in the High Level Page enables a dropdown menu for the user to select additional output override options such as VOD amplitude,
pre-emphasis, or de-emphasis controls.
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SigCon Architect LMH1297 GUI Profile
6.3.2
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Macro Scripting Utility
The Macro Scripting Utility in the High Level Page allows the user to create and upload a text file (.txt
extension) with instructions to write to multiple devices and registers simultaneously. After a macro file is
uploaded and run, SigCon Architect generates a log file showing the device slave address, register
address, data written, and data that is read back after each write. Figure 19 shows the required syntax for
the macro scripts.
Figure 19. Macro Utility Syntax
NOTE: All parameters on the text file should be separated by a tab in order for the Macro utility to
identify and accept the format.
Figure 10 shows an example of a macro script that programs two LMH1297 devices, one with SMBus
Address 0x5C and another with SMBus Address 0x5A. After this file is saved as a .txt file, the user can
run the macro by entering the appropriate file path in the Custom Macro Scripting Utility box. When ready,
click Run to execute the script.
Figure 20. Macro Utility Example
After the script completes, the log file can be accessed by clicking View Log File and opening the
appropriate log file .txt file. Figure 21 shows an example of a log file based on the macro utility example in
Figure 20.
16
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Figure 21. Macro Utility Example Log File
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SigCon Architect LMH1297 GUI Profile
6.4
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Eye Monitor Page
The LMH1297 has on-chip eye monitor that can be accessed on the Eye Monitor Page. In this page, the
user can control the following:
• Perform a single or continuous capture of the eye diagram
• Measure the HEO (Horizontal Eye Opening) in either time (ps) or unit intervals (UI)
• Measure the VEO (Vertical Eye Opening)
• Read back the detected data rate
Figure 22 shows the Eye Monitor Page.
Figure 22. LMH1297EVM Eye Monitor Page
18
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Bill Of Materials
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7
Bill Of Materials
NO.
DESIGNATOR
QUANTITY DESCRIPTION
MANUFACTURER
PART NUMBER
1
!PCB
1
Printed-Circuit Board
Any
SV601292
2
C1
1
CAP, CERM, 10uF, 16V, +/-20%,
X5R, 0805
AVX
0805YD106MAT2A
AVX
0805YD105KAT2A
3
C2, C3, C23
3
CAP, CERM, 1uF, 16V, +/-10%,
X5R, 0805, CAP, CERM, 1uF, 16V,
+/-10%, X5R, 0805, CAP, CERM, 1
µF, 16 V, +/- 10%, X5R, 0805
4
C4. C5. C7
3
CAP, CERM, 0.1 µF, 6.3 V, +/10%, X5R, 0402
TDK
C1005X5R0J104K050BA
5
C6
1
CAP, CERM, 1 µF, 6.3 V, +/- 20%,
X5R, 0402
TDK
C1005X5R0J105M050BB
6
C10, C11, C12, C13, C14,
C15, C16, C17
8
CAP, CERM, 4.7 µF, 10 V, +/- 10%,
TDK
X5R, 0402
C1005X5R1A475K050BC
7
C21
1
CAP, CERM, 2.2uF, 16V, +/-10%,
X5R, 0805
AVX
0805YD225KAT2A
8
C22
1
CAP, AL, 22 µF, 10 V, +/- 20%,
ohm, SMD
Chemi-Con
EMVE100ADA220ME55G
9
C24
1
CAP, CERM, 0.01 µF, 50 V, +/10%, X7R, 0603
TDK
C1608X7R1H103K080AA
10
C25, C31, C32, C34
4
CAP, CERM, 0.1uF, 16V, +/-5%,
X7R, 0603
AVX
0603YC104JAT2A
11
C26, C27
2
CAP, CERM, 220pF, 50V, +/-1%,
C0G/NP0, 0603
AVX
06035A221FAT2A
12
C28, C29
2
CAP, CERM, 30pF, 100V, +/-5%,
C0G/NP0, 0603
MuRata
GRM1885C2A300JA01D
13
C30
1
CAP, CERM, 2200pF, 50V, +/-10%,
Kemet
X7R, 0603
C0603X222K5RACTU
14
C33
1
CAP, CERM, 0.47uF, 10V, +/-10%,
X7R, 0603
MuRata
GRM188R71A474KA61D
15
D1, D3
2
LED, Green, SMD
Lumex
SML-LX0603GW-TR
16
D2
1
Diode, Zener, 7.5 V, 550 mW, SMB
ON Semiconductor
1SMB5922BT3G
Taiyo Yuden
BK1608HS600-T
17
FB1
1
Ferrite Bead, 60 ohm @ 100 MHz,
0.8 A, 0603
18
FID1, FID2, FID3, FID4,
FID5, FID6
6
Fiducial mark. There is nothing to
buy or mount.
N/A
N/A
19
H1, H2, H3, H4, H5, H6
6
Machine Screw, Round, #4-40 x
1/4, Nylon, Philips panhead
B&F Fstener
NY PMS 440 0025 PH
20
H7, H8, H9, H10, H11, H12
6
Standoff, Hex, 0.5"L #4-40 Nylon
Keystone
1902C
Keystone
1212-ST
21
J1, J2, J3
3
Disconnect Terminal, 5.08mm, 2x1,
Tin, TH
22
J4, J6, J7
3
Header, 100mil, 2x1, Tin, TH
TE Connectivity
5-146278-2
23
J5
1
Header, 100mil, 3x1, Tin, TH
TE Connectivity
5-146278-3
TE Connectivity
5103308-1
24
J8
1
Header (shrouded), 100mil, 5x2,
Gold, TH
25
J9
1
Header, 100mil, 5x2, Tin, TH
Sullins Connector
Solutions
PEC05DAAN
26
J10, J11, J12, J13, J14,
J15, J16, J17, J18, J19
10
Header, 100mil, 3x2, Tin, TH
TE Connectivity
5-146254-3
27
J20, J21
2
Connector, BNC Edge Mount, SMD
Samtec
BNC7T-J-P-GN-ST-EM1D
142-0771-821
28
J22, J23, J24, J25
4
Connector, TH, End launch SMA 50 Emerson Network
ohm
Power
29
J31
1
Connector, Receptacle, Mini-USB
Type B, R/A, Top Mount SMT
TE Connectivity
1734035-2
30
J33
1
Header, 100mil, 2x2, Gold, TH
Samtec
TSW-102-07-G-D
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LMH1297EVM Evaluation Board
19
Bill Of Materials
NO.
QUANTITY DESCRIPTION
MANUFACTURER
PART NUMBER
31
Q1
1
MOSFET, N-CH, 50 V, 0.22 A,
SOT-23
Fairchild
Semiconductor
BSS138
32
R1, R2
2
RES, 2.00k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04022K00FKED
33
R3, R4, R5, R6, R7, R8,
R9, R10, R11, R12, R13,
R14, R15, R16, R17, R18,
R19, R20, R41, R42
20
RES, 1.00k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04021K00FKED
34
R21
1
RES, 220 ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW0402220RJNED
Vishay-Dale
CRCW04023K16FKED
35
R22, R23, R24
3
RES, 3.16k ohm, 1%, 0.063W,
0402
36
R25, R26, R27
3
RES, 9.76k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04029K76FKED
37
R28, R29
2
RES, 75.0 ohm, 1%, 0.063W, 0402
Vishay-Dale
CRCW040275R0FKED
38
R31, R32
2
RES, 33 ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW040233R0JNED
39
R33
1
RES, 1.5 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04021K50JNED
40
R34, R36
2
RES, 33k ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW040233K0JNED
41
R35
1
RES, 1.2Meg ohm, 5%, 0.1W, 0603 Vishay-Dale
CRCW06031M20JNEA
42
R37
1
RES, 200 ohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW0603200RFKEA
43
R43, R44, 445, R46, R47,
R48, R49, R50, R51, R52
10
RES, 20.0k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW040220K0FKED
44
S1
1
Switch, Tactile, SPST-NO, SMT
Panasonic
EVQ-PSD02K
45
SH-J1, SH-J2, SH-J3, SHJ4, SH-J5, SH-J6, SH-J7,
SH-J8, SH-J9, SH-J10, SHJ11, SH-J12, SH-J13
13
Shunt, 100mil, Gold plated, Black
3M
969102-0000-DA
46
U1
1
12G UHD Bidirectional I/O with
Integrated Reclocker, RTV0032E
Texas Instruments
LMH1297RTV
1
500mA, Low Quiescent Current,
Ultra-Low Noise, High PSRR LowDropout Linear Regulator,
DRB0008A
Texas Instruments
TPS73533DRBR
1
ESD-Protection Array for HighSpeed Data Interfaces, 4 Channels,
Texas Instruments
-40 to +85 degC, 6-pin SON (DRY),
Green (RoHS & no Sb/Br)
TPD4E004DRYR
Texas Instruments
MSP430F5529IPN
ECS Inc.
ECS-240-20-5PX-TR
47
48
20
DESIGNATOR
www.ti.com
U2
U3
49
U4
1
25 MHz Mixed Signal
Microcontroller with 128 KB Flash,
8192 B SRAM and 63 GPIOs, -40
to 85 degC, 80-pin QFP (PN),
Green (RoHS & no Sb/Br)
50
Y1
1
Crystal, 24.000MHz, 20pF, SMD
LMH1297EVM Evaluation Board
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Schematics
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8
Schematics
VDD_LDO
VDD_CDR
VIN
C10
75 ohm single ended trace
4.7µF
J20
i
C6
1µF
C7
0.1µF
5
4
C5
0.1µF
C11
75 ohm single ended trace
BNC7T-J-P-GN-ST-EM1D
4.7µF
i
R28
C14
50 ohm single ended trace
4.7µF
J22
i
GND
U1
21
142-0771-821
J25
4.7µF
142-0771-821
GND
MODE_SEL
EQ_CD_SEL
OUT0_SEL
OUT_CTRL
HOST_EQ0
ENABLE
SDI_VOD
12
5
4
17
9
32
24
LOCK_N
27
SS_N_ADDR0
MISO_ADDR1
SCK_SCL
MOSI_SDA
11
28
29
13
IN0+
IN0-
SDI_OUTSDI_OUT+
C15
7
8
50 ohm single ended trace
142-0771-821
4.7µF
J23
i
SDI_OUT_SEL
RSV1
RSV2
RSV3
RSV4
RSV5
10
15
16
25
26
RSV1
MOSI
VSS
VSS
VSS
EP
3
6
20
33
SSN
SCK
75 ohm single ended trace
142-0771-821
4.7µF
i
R29
75 ohm single ended trace
75.0
C13
4.7µF
J21
i
MOSI_SDA
C12
SCK_SCL
3P3V
GND
MISO
MOSI
SSN
SCK
MOSI_SDA
SCK_SCL
1
LOCK
SS_ADDR0
MISO_ADDR1
SCK_SCL
MOSI_SDA
MISO
1
14
SDI_OUT_SEL
MODE_SEL
EQ/CD_SEL
OUT0_SEL
OUT_CTRL
HOST_EQ0
ENABLE
SDI_VOD
23
22
GND
5
4
3
2
OUT0+
OUT0-
3P3V
1
5
4
3
2
19
18
50 ohm single ended trace
C17
i
2
3
4
5
1
VDD_LDO
4.7µF
2
3
4
5
1
1
2
5
4
J24
SDI_IO+
SDI_IO-
VDD_CDR
31
50 ohm single ended trace
C16
i
75.0
VIN
3
2
30
3
2
1
C4
0.1µF
BNC7T-J-P-GN-ST-EM1D
GND
Shunt Jumper Settings:
LMH1297RTV
GND
J8
1
3
5
7
9
MISO
3P3V
2
4
6
8
10
3P3V
R25 9.76k
R269.76k
GND
R279.76k
SSN R22 3.16k
MOSI R23 3.16k
GND
SCK R24 3.16k
R1
R2
J9
MOSI_SDA
SCK_SCL
5103308-1
2.00k
2.00k
2 SS_N_ADDR0
4 MOSI_SDA
6 SCK_SCL
8
10
1
3
5
7
9
For SMBUS MODE:
J9 - Install pin 7-8 and 9-10 for 2kohm pull to 3.3V
PIN 1-6 LEAVE OPEN
For SPI MODE:
J9 - Install pin 1-2 and 3-4 and 5-6 for SPI 3.3V to 2.5V level shift
J6 - Intall pin 1-2
PIN 7-10 LEAVE OPEN
PEC05DAAN
J1
1
2
GND
J5
C1
10µF
1212-ST
C2
1µF
J2
VIN
EQ_CD_SEL
R3
1.00k 1
1
2
VDD_CDR
2 GND
4
6
3
5
GND
R4
VIN
OUT_CTRL
R43 20.0k
1.00k
R11 1.00k 1
2 GND
4
6
3
5
R12 1.00k
VIN
SDI_OUT_SEL
R47 20.0k
J10
R19 1.00k 1
2 GND
4
6
3
5
R20 1.00k
VIN
ENABLE
GND
1
2
3
MISO_ADDR1
MISO
1
2
R51 20.0k
J14
5-146278-3
J18
1212-ST
J6
J4
J3
1
2
1212-ST
VIN
OUT0_SEL
1
2
VIN
C3
1µF
GND
R5
2 GND
4
6
3
5
R6
5-146278-2
1.00k 1
GND
VIN
SDI_VOD
R44 20.0k
1.00k
R13 1.00k 1
2 GND
4
6
3
5
R14 1.00k
GND
VIN
RSV1
R48 20.0k
J11
J15
R41 1.00k 1
2 GND
4
6
3
5
R42 1.00k
5-146278-2
R52 20.0k
J19
GND
R7
1.00k 1
2 GND
4
6
3
5
R8
GND
VIN
SS_N_ADDR0
R45 20.0k
1.00k
R15 1.00k 1
2 GND
4
6
3
5
R16 1.00k
1.00k 1
2 GND
4
6
3
5
R10 1.00k
5-146278-2
J16
GND
R9
R17 1.00k 1
2 GND
4
6
3
5
R18 1.00k
R46 20.0k
R50 20.0k
J17
GND
D1
Green
GND
VIN
MISO_ADDR1
J13
2
1 LOCK_N
R49 20.0k
J12
VIN
MODE_SEL
GND
1
VIN
HOST_EQ0
2
J7
GND
R21
220
VIN
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 23. LMH1297 Schematic Page
SNAU205A – March 2017 – Revised August 2019
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21
Schematics
www.ti.com
VBUS
J31
1
2
3
4
5
R31
DM
33
R32
DP
33
USB Mini Type B
R33
U3
GND
PWR
1.5k
S1
C25
0.1µF
3
U4
1
2
TPD4E004DRYR
33k
VUSB
4
3
BSL
R35
1.2Meg
GND
C26
220pF
GND
C31
0.1µF
3P3V
MOSI
SSN
SCK
MOSI_SDA
SCK_SCL
GND
GND
MISO
37
38
39
40
41
42
43
44
P3.0/UCB0SIMO/UC B0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
P3.7/TB0OUTH/ SVMOUT
9
10
69
70
12
13
55
56
P5.0/A8/ VREF+/VEREF+
P5.1/A9/VREF-/VEREFP5.2/XT2IN
P5.3/XT2OUT
P5.4/XIN
P5.5/XOUT
P5.6/TB0.0
P5.7/TB0.1
5
6
7
8
57
58
59
60
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P7.4/TB0.2
P7.5/TB0.3
P7.6/TB0.4
P7.7/TB0CL K/MCLK
C28
GND
MOSI
30pF
SSN
2
MISO
3P3V
Y1
SCK
C29
1
GND
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CL K/CBOUT
P1.7/TA1.0
GND
GND
3P3V
21
22
23
24
25
26
27
28
24MHz
MOSI_SDA
30pF
SCK_SCL
67
20
GND
C33
0.47µF
V18
VCORE
VBUS
VUSB
GND
29
30
31
32
33
34
35
36
SSN
P4.0/PM_UCB1STE/PM_UCA1CLK
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.6/PM_NONE
P4.7/PM_NONE
45
46
47
48
51
52
53
54
MOSI_SDA
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
77
78
79
80
1
2
3
4
P8.0
P8.1
P8.2
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
RST/NMI/SBWTDIO
TEST/SBWTCK
GND
C27
220pF
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CL K/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCL K/DMAE0
P2.7/UCB0STE/UCA0CLK
65
66
11
18
50
3P3V
PU.0/DP
PU.1/DM
PUR
VBUS
VUSB
AVCC1
DVCC1
DVCC2
VSSU
AVSS1
AVSS2
DVSS1
DVSS2
SCK
3P3V
SCK_SCL
MOSI
1
VCC
4
5
MISO
D3
Green
J33
1
3
2
IO3
IO4
2
4
R37
200
TSW-102-07-G-D
GND
3
6
R34
IO1
IO2
Q1
BSS138
1
15
16
17
2
1
2
72
73
74
75
GND
76
71
DP
62
64
DM
63
PWR
61
14
68
19
49
3P3V
R36
33k
C30
2200pF
MSP430F5529IPN
C32
0.1µF
VBUS
C34
0.1µF
GND
3P3V
U2
8
FB1
5
60 ohm
C22
22µF
D2
7.5V
GND
C23
1µF
GND
GND
2
6
7
IN
OUT
EN
NR
NC
NC
NC
GND
PAD
GND
1
C21
2.2µF
3
4
9
C24
0.01µF
GND
GND
TPS73533DRBR
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 24. MSP430 USB2ANY Schematic Page
22
LMH1297EVM Evaluation Board
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EVM Layout
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9
EVM Layout
The following figures show the LMH1297EVM layout. The evaluation board controls signal integrity control
settings through jumper pins.
The LMH1297EVM allows access to all input channels (SDI_IO+ and IN0±) and output channels
(SDI_IO+, OUT0±, and SDI_OUT+). It is very compact and low power. The QFN package offers an
exposed thermal pad to enhance electrical and thermal performance. This must be soldered to the copper
landing on the PWB.
Figure 25. LMH1297EVM Top Layer
Figure 26. LMH1297EVM Bottom Layer
SNAU205A – March 2017 – Revised August 2019
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LMH1297EVM Evaluation Board
23
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STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.
www.ti.com
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
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Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
3
www.ti.com
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
www.ti.com
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
5
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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