Texas Instruments | DS160PR410EVM-SMA Evaluation Module (EVM) | User Guides | Texas Instruments DS160PR410EVM-SMA Evaluation Module (EVM) User guides

Texas Instruments DS160PR410EVM-SMA Evaluation Module (EVM) User guides
User's Guide
SNLU251A – August 2019 – Revised January 2020
DS160PR410EVM-SMA Evaluation Module (EVM)
The DS160PR410EVM-RSC and DS160PR410EVM-SMA evaluation modules provide a complete highbandwidth platform for evaluating the signal conditioning features of the Texas Instruments DS160PR410
Quad-Channel PCI-Express Gen-4 Linear Redriver. These evaluation boards can be used for standard
compliance testing, performance evaluation, and initial system prototyping.
Figure 1. DS160PR410EVM-SMA - Top Side Photo
1
2
3
4
5
Contents
Introduction ................................................................................................................... 3
1.1
Features .............................................................................................................. 3
1.2
Applications .......................................................................................................... 3
1.3
Description ........................................................................................................... 4
1.4
Quick-Start Guide (Pin Mode) ..................................................................................... 9
1.5
Quick-Start Guide (SMBus Slave Mode) ....................................................................... 10
Test Setup and Results.................................................................................................... 11
Board Layout ................................................................................................................ 12
Schematic and Bill of Materials ........................................................................................... 14
4.1
Schematic .......................................................................................................... 14
4.2
Bill of Materials .................................................................................................... 19
4.3
REACH Compliance .............................................................................................. 24
References .................................................................................................................. 24
List of Figures
1
DS160PR410EVM-SMA - Top Side Photo ............................................................................... 1
2
SigCon Architect DS160PR410 High Level Page
3
4
5
6
7
8
9
10
.....................................................................
Example Test Setup and Results ........................................................................................
Top Layer ...................................................................................................................
Bottom Layer................................................................................................................
Top Level Schematic Page ...............................................................................................
Control and Status Schematic Page .....................................................................................
Voltage Regulator Schematic Page......................................................................................
Device Schematic Page ...................................................................................................
Hardware Page .............................................................................................................
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
10
11
12
13
14
15
16
17
18
1
www.ti.com
List of Tables
1
4-Level Control Pin Settings................................................................................................ 4
2
Modes of Operation
3
SMBus / I2C Slave Address Settings ..................................................................................... 5
4
Equalization Control Settings
5
6
7
8
9
10
.........................................................................................................
4
.............................................................................................. 6
4-Level Control Pin Settings................................................................................................ 6
VOD Control .................................................................................................................. 7
GAIN Control ................................................................................................................. 7
EVM Global Controls ........................................................................................................ 8
Bill of Materials ............................................................................................................. 19
REACH Affected Components............................................................................................ 24
Trademarks
All trademarks are the property of their respective owners.
2
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Introduction
www.ti.com
1
Introduction
The DS160PR410EVM-RSC evaluation module option features eight DS160PR410 linear redrivers that
can extend the transmission distance of a PCIe Gen-4 x16 bus. It can directly be plugged into a PCIe slot
on a Server / PC motherboard using one end of the board, and paired up with a PCIe Riser Card using
the straddle mount connector attached to the other end of the board.
The DS160PR410EVM-SMA evaluation board option features a single, standalone DS160PR410 device
with the high-speed I/Os routed to SMA connectors. The SMA connectors can interface to multiple
connector types through commercially available breakout cables, adaptors, and boards (not included).
This document describes the DS160PR410EVM-SMA evaluation module.
1.1
Features
•
•
•
•
•
•
1.2
One standalone 4-channel redriver with the high-speed I/Os routed to SMA connectors
Linear equalization for seamless support of link training and PCIe channel extension
CTLE boosts up to 18 dB at 8 GHz
Programmable device configuration through GPIO or I2C / SMBus
Industrial temperature range: –40ºC to 85ºC
Flow-through layout in 4-mm × 6-mm 40-pin, leadless WQFN 0.4-mm pitch package
Applications
•
•
•
•
•
PCI Express Gen-1, 2, 3, and 4
High-speed interfaces up to 25 Gbps
Enterprise server motherboard, workstation
Enterprise storage
Enterprise add-in card, end-point
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
3
Introduction
1.3
1.3.1
www.ti.com
Description
DS160PR410 4-Level I/O Control Inputs
The DS160PR410 has six (GAIN, VOD, EQ1_ADDR1, EQ0_ADDR0, EN_SMB, and RX_DET) 4-level
input pins that are used to control the configuration of the device. These 4-level inputs use a resistor
divider to help set the four valid levels and provide a wider range of control settings.
Table 1. 4-Level Control Pin Settings
PIN LEVEL
1.3.2
PIN SETTING
L0
1 kΩ to GND
L1
13 kΩ to GND
L2
Float
L3
59 kΩ to GND
DS160PR410 Modes of Operation
The DS160PR410 can be configured to operate in either Pin Mode, SMBus / I2C Slave Mode, or SMBus /
I2C Master Mode. The mode of operation of the DS160PR410 is determined by the pin strap setting on
the EN_SMB pin as shown in Table 2.
Table 2. Modes of Operation
EN_SMB PIN LEVEL
4
MODE OF OPERATION
L0
Pin Mode
L1
SMBus / I2C Master Mode
L2
Reserved
L3
SMBus / I2C Slave Mode
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Introduction
www.ti.com
1.3.3
DS160PR410 SMBus / I2C Register Control Interface
The DS160PR410 may be configured through a standard I2C or SMBus interface that may operate up to 1
MHz. The slave address of the DS160PR410 is determined by the pin strap settings on the EQ1_ADDR1
and EQ0_ADDR0 pins. The device can be configured for best signal integrity and power settings in the
system using the I2C or SMBus interface. Certain status information is also available through this
interface. The possible SMBus / I2C slave addresses are shown in Table 3.
Table 3. SMBus / I2C Slave Address Settings
EQ1_ADDR1 PIN LEVEL
EQ0_ADDR0 PIN LEVEL
8-BIT WRITE ADDRESS
(HEX)
7-BIT ADDRESS (HEX)
L0
L0
0x30
0x18
L0
L1
0x32
0x19
L0
L2
0x34
0x1A
L0
L3
0x36
0x1B
L1
L0
0x38
0x1C
L1
L1
0x3A
0x1D
L1
L2
0x3C
0x1E
L1
L3
0x3E
0x1F
L2
L0
0x40
0x20
L2
L1
0x42
0x21
L2
L2
0x44
0x22
L2
L3
0x46
0x23
L3
L0
0x48
0x24
L3
L1
0x4A
0x25
L3
L2
0x4C
0x26
L3
L3
0x4E
0x27
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
5
Introduction
1.3.4
www.ti.com
DS160PR410 Equalization Control
Each channel of the DS160PR410 features a continuous-time linear equalizer (CTLE) that applies highfrequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss
effects of the passive channel. Table 4 shows available equalization gain that can be set through
EQ0_ADDR0 and EQ1_ADDR1 control pins when operating in Pin Mode.
Table 4. Equalization Control Settings
EQ INDEX
EQ1_ADDR1 PIN LEVEL
EQ0_ADDR0 PIN LEVEL
CTLE BOOST AT 4 GHz
(dB)
CTLE BOOST AT 8 GHz
(dB)
0
L0
L0
–0.3
–0.8
1
L0
L1
0.4
1.3
2
L0
L2
3.3
5.7
3
L0
L3
3.8
7.1
4
L1
L0
4.9
8.4
5
L1
L1
5.2
9.1
6
L1
L2
5.4
9.8
7
L1
L3
6.5
10.7
8
L2
L0
6.7
11.3
9
L2
L1
7.7
12.6
10
L2
L2
8.7
13.6
11
L2
L3
9.1
14.4
12
L3
L0
9.4
15.0
13
L3
L1
10.3
15.9
14
L3
L2
10.6
16.5
15
L3
L3
11.8
17.8
The equalization gain of each channel can also be set by writing to SMBus / I2C registers in Slave or
Master Modes. Refer to the DS160PR410 Programming Guide (SNLU255) for details.
1.3.5
DS160PR410 RX Detect State Machine
The DS160PR410 deploys an RX Detect state machine that governs the RX detection cycle as defined in
the PCI Express specification. At power up or after a manually triggered event, the redriver determines
whether or not a valid PCI Express termination is present at the far end of the link. The RX_DET pin of
DS160PR410 provides additional flexibility to system designers to appropriately set the device in their
desired mode, according to Table 5.
Table 5. 4-Level Control Pin Settings
6
PWDN PIN LEVEL
RXDET PIN LEVEL
DESCRIPTION
L
L0
Reserved
L
L1
Reserved
L
L2
PCI Express RX detection state machine is
enabled. Recommended for PCI Express use
cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
L
L3
PCI Express RX detection state machine is
disabled. Recommended for non-PCI Express use
cases. Inputs are always 50 Ω.
H
X
Manual reset, inputs are Hi-Z
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Introduction
www.ti.com
1.3.6
DS160PR410 Equalization DC Gain Control
When operating in Pin Mode, the VOD and GAIN pins can be used to set the overall datapath DC (low
frequency) gain of the DS160PR410 as shown in Table 6 and Table 7.
Table 6. VOD Control
VOD PIN LEVEL
VOD SETTING
L0
–6 dB
L1
–3.5 dB
L2
0 dB (Recommended for most use cases)
L3
–1.6 dB
Table 7. GAIN Control
GAIN PIN LEVEL
GAIN SETTING
L0
Reserved
L1
Reserved
L2
0 dB (Recommended for most use cases)
L3
3.5 dB
The DC gain of each channel can also be set by writing to SMBus / I2C registers in Slave or Master
Modes. Refer to the DS160PR410 Programming Guide (SNLU255) for details.
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
7
Introduction
1.3.7
www.ti.com
DS160PR410EVM-SMA Device Controls and Access Points
Table 8 shows DS160PR410EVM-SMA global controls.
Table 8. EVM Global Controls
COMPONENT
FUNCTION / DESCRIPTION
J1
3x2 Header
EN_SMB control tied to EN_SMB pin
L0: Device set to Pin Mode (Default)
L1: Device set to SMBus / I2C Master Mode
L2: Reserved
L3: Device set to SMBus / I2C Slave Mode
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to
achieve L2 level on the pin.
J2
5x2 Header
SMBus / I2C interface. The DS160PR410 device registers can be accessed
through this interface.
J3
3x1 Header
PWDN control tied to PWDN1 and PWDN2 pins
PWDN tied to GND: Device enabled (Default)
PWDN tied to 3.3V_REG: Device disabled.
PWDN floating: Not recommended
J4
3x1 Header
Access point to the WP (write protect) pin of the onboard EEPROM device
WP tied to GND: I2C Access to the EEPROM enabled
WP floating: I2C Access to the EEPROM disabled (default)
J11
2x1 Header
3.3-V supply input. Apply power to this connector to power the EVM.
Access point to the GND reference.
J12
2x1 Header
J21 - J28
SMA Connectors
Access points for all RX inputs
J32 - J39
SMA Connectors
Access points for all TX outputs
J29
8
NAME
12x2 Header
DS160PR410EVM-SMA Evaluation Module (EVM)
Additional Device Controls
Use pins 1-6 for configuring EQ1_ADDR1 pin of SA1 device.
Use pins 7-12 for configuring EQ0_ADDR0 pin of SA1 device.
Use pins 13-18 for configuring VOD pin of SA1 device.
Use pins 19-20 for configuring GAIN pin of SA1 device.
Use pins 21-22 for configuring RXDET pin of SA1 device.
Use pins 23-24 for accessing READ_EN_N pin of SA1 device.
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to
achieve L2 level on the pin.
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Introduction
www.ti.com
1.4
Quick-Start Guide (Pin Mode)
1. Check that the shunts are at the following default positions as shown in Figure 1.
• The redriver is configured to operate in Pin Mode (EN_SMB pin tied to L0 using J1 header).
• The redriver is enabled (PWDN pins tied to GND using J3 header).
• DC Gain of the RX CTLE is set to 0 dB by leaving J29 (pins 19-20) open.
• VOD is set to 0 dB by leaving J29 (pins 13-18) open.
• RX_Detect state machine is enabled by leaving J29 (pins 21-22) open. Disable the state machine
by installing a shunt across pins 21-22 of J29.
• EQ level of the RX CTLEs of all channels is set to 13.6 dB at 8 GHz by leaving J29 (pins 1-12)
open.
2. If necessary, adjust EQ levels by arranging shunts on J29 (pins 1-12).
3. Connect a pattern or data generator to one or all RX inputs (J21-J28).
4. Optionally, insert a lossy channel between a pattern generator and RX inputs to test EQ capability of
the device.
5. Apply 3.3-V supply between J11 and J12.
6. Observe one or all TX outputs (J32-J39) using a BERT or a high-bandwidth oscilloscope.
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
9
Introduction
1.5
www.ti.com
Quick-Start Guide (SMBus Slave Mode)
1. Configure the devices to operate in the SMBus Slave Mode by setting its EN_SMB pin to the L3 level.
This is accomplished by placing a shunt on J1 to L3 location.
2. Enable the devices by pulling its PWDN pins to GND. This is accomplished by placing a shunt on J3
between PWDN and GND.
3. Connect USB2ANY Adapter to J2 (Note that the USB2ANY Adapter is not supplied with the
DS160PR410EVM-SMA).
4. Install SigCon Architect Version 3.0.0.10 application. It comes with the DS160PR410 profile.
5. Apply 3.3-V supply between J11 and J12.
6. Start the SigCon Architect application.
7. In the DS160PR410 Configuration Page, click on "Auto Detect" box to detect the EVM Model. If
necessary, edit the devices addresses in the Edit Device Addresses box.
8. Select Low Level Page to initialize the register map tree in the application. Failure to perform this step
may cause the application to crash.
9. In the DS160PR410 High Level Page, select Block Diagram as shown in Figure 2.
10. Select desired EQ Settings and Driver VOD.
11. Click Apply to All Channels.
12. Connect a pattern or data generator to one or all RX inputs (J21 - J28).
13. Optionally, insert a lossy channel between a pattern generator and RX inputs to test EQ capability of
the device.
14. Observe one or all TX outputs (J32 - J39) using a BERT or a high-bandwidth oscilloscope.
Figure 2. SigCon Architect DS160PR410 High Level Page
10
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Test Setup and Results
www.ti.com
2
Test Setup and Results
Figure 3 shows an electric link that models a single channel of a PCIe link and displays eye diagrams
measured at different locations along the link. The source that models a PCIe TX sends a 16-Gbps PRBS15 signal with P7 presets. After a transmission channel with –30 dB at 8-GHz insertion loss, the eye
diagram is fully closed. The DS160PR410 with its CTLE set to the maximum (18-dB boost) together with
the source TX equalization compensates for the losses of the pre-channel (TL1) and opens the eye at the
output of the DS160PR410.
PCIe Root
Complex
RX CTLE: 12 dB
TL1
-30 dB @ 8 GHz
Pre-Cursor: 3.5 dB
Post-Cursor: -6 dB
DS160PR410
RX EQ Boost: 18 dB
TL2
-15 dB @ 8 GHz
PCIe
End Point
Figure 3. Example Test Setup and Results
The post-channel (TL2) losses mandate the use of PCIe RX equalization functions such as CTLE and
DFE that are normally available in PCIe compliant receivers.
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
11
Board Layout
3
www.ti.com
Board Layout
Figure 4. Top Layer
12
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Board Layout
www.ti.com
Figure 5. Bottom Layer
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
13
Schematic and Bill of Materials
4
Schematic and Bill of Materials
4.1
Schematic
www.ti.com
Figure 6. Top Level Schematic Page
14
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Schematic and Bill of Materials
www.ti.com
Figure 7. Control and Status Schematic Page
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
15
Schematic and Bill of Materials
www.ti.com
Figure 8. Voltage Regulator Schematic Page
16
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Schematic and Bill of Materials
www.ti.com
Figure 9. Device Schematic Page
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
17
Schematic and Bill of Materials
www.ti.com
Figure 10. Hardware Page
18
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Schematic and Bill of Materials
www.ti.com
4.2
Bill of Materials
Table 9. Bill of Materials
DESIGNATOR
QTY
VALUE
DESCRIPTION
PACKAGE
REFERENCE
PART NUMBER
MANUFACTURER
!PCB1
1
C1, C2
2
1uF
CAP, CERM, 1 uF, 25 V, +/- 10%,
X5R, 0402
0402
HSDC058
Any
C1005X5R1E105K050BC
TDK
C9
1
100uF
CAP, CERM, 100 uF, 6.3 V, +/20%, X5R, 0805
0805
GRM21BR60J107M
MuRata
C12
1
10uF
CAP, CERM, 10 uF, 6.3 V, +/10%, X5R, 0805
0805
GRM219R60J106KE19D
MuRata
C14
1
1uF
CAP, CERM, 1 uF, 6.3 V, +/- 10%, 0603
X7R, 0603
GRM188R70J105KA01D
MuRata
C141, C142, C143, C144, C145, C146, C147, C148, C155,
C156, C157, C158, C159, C160, C161, C162
16
0.22uF
CAP, CERM, 0.22 uF, 10 V, +/20%, X5R, 0201
0201
LMK063BJ224MP-F
Taiyo Yuden
C149, C150, C151, C152, C153, C154
6
0.1uF
CAP, CERM, 0.1 uF, 6.3 V, +/10%, X5R, 0201
0201
C0603X5R0J104K030BC
TDK
D2, D3
2
Green
LED, Green, SMD
2x1.4mm
LG M67K-G1J2-24-Z
OSRAM
H1, H3, H5, H7
4
Standoff, Hex, 0.5"L #4-40 Nylon
Standoff
1902C
Keystone
H2, H4, H6, H8
4
Machine Screw, Round, #4-40 x
1/4, Nylon, Philips panhead
Screw
NY PMS 440 0025 PH
B and F Fastener
Supply
J1
1
Header, 100mil, 3x2, Gold, TH
3x2 Header
TSW-103-07-G-D
Samtec
J2
1
Header, 100mil, 5x2, Gold, TH
5x2 Header
TSW-105-07-G-D
Samtec
J3, J4
2
Header, 2.54mm, 3x1, Gold, TH
Header,
2.54mm, 3x1,
TH
961103-6804-AR
3M
J11, J12
2
Header, 2.54mm, 2x1, TH
Header,
2.54mm, 2x1,
TH
961102-6404-AR
3M
J21, J22, J27, J28, J32, J33, J38, J39
8
SMA, Straight Jack, SMT
SMA
Connector,
SMT
732511352
Molex
J23, J24, J25, J26, J34, J35, J36, J37
8
SMA JACK 50 OHM, R/A, SMT
SMA JACK,
R/A, SMT
32K243-40ML5
Rosenberger
J29
1
Header, 100mil, 12x2, Gold, TH
12x2 Header
TSW-112-07-G-D
Samtec
LBL1
1
Thermal Transfer Printable Labels, PCB Label
0.650" W x 0.200" H - 10,000 per
0.650 x 0.200
roll
inch
THT-14-423-10
Brady
R4, R5
2
RES, 2.2 k, 5%, 0.063 W, AECQ200 Grade 0, 0402
CRCW04022K20JNED
Vishay-Dale
Printed Circuit Board
2.2k
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
0402
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
19
Schematic and Bill of Materials
www.ti.com
Table 9. Bill of Materials (continued)
DESIGNATOR
QTY
VALUE
DESCRIPTION
PACKAGE
REFERENCE
PART NUMBER
MANUFACTURER
R6
1
1.00k
RES, 1.00 k, 1%, 0.1 W, 0402
0402
ERJ-2RKF1001X
Panasonic
R7, R105, R108, R111
4
13.0k
RES, 13.0 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040213K0FKED
Vishay-Dale
R8, R106, R109, R112, R113, R114
6
59.0k
RES, 59.0 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040259K0FKED
Vishay-Dale
R9
1
249
RES, 249, 1%, 0.1 W, AEC-Q200
Grade 0, 0402
0402
ERJ-2RKF2490X
Panasonic
R10
1
10.0k
RES, 10.0 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
AC0402FR-0710KL
Yageo America
R12, R13
2
330
RES, 330, 5%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW0402330RJNED
Vishay-Dale
R103
1
4.70k
RES, 4.70 k, 1%, 0.063 W, 0402
0402
CRG0402F4K7
TE Connectivity
R104, R107, R110
3
1.00k
RES, 1.00 k, 1%, 0.063 W, 0402
0402
MCR01MZPF1001
Rohm
SA1
1
DS160PR410, RNQ0040A
(WQFN-40)
RNQ0040A
DS160PR410
Texas Instruments
SH-J1, SH-J7, SH-J8, SH-J9, SH-J10
5
Shunt, 100mil, Flash Gold, Black
Closed Top
100mil Shunt
SPC02SYAN
Sullins Connector
Solutions
SW1
1
Switch, Tactile, SPST-NO, 0.02A,
15V, TH
6.0x5.0x6mm
EVQ-21505R
Panasonic
U1
1
I2C-Compatible (2-wire) Serial
SOIC-8
EEPROM 2-Kbit (256 x 8), SOIC-8
AT24C02D-SSHM-T
Atmel
U2
1
Quadruple Bus Buffer Gate With 3- PW0014A
State Outputs, PW0014A, LARGE
T and R
SN74LVC125APWRG3
Texas Instruments
C3
0
0.1uF
CAP, CERM, 0.1 uF, 25 V, +/10%, X5R, 0402
0402
GRM155R61E104KA87D
MuRata
C4
0
100uF
CAP, TA, 100 uF, 25 V, +/- 10%,
0.1 ohm, SMD
7360-38
T495E107K025ATE100
Kemet
C5, C6
0
22uF
CAP, CERM, 22 uF, 25 V, +/20%, X5R, 1206_190
1206_190
TMK316BBJ226ML-T
Taiyo Yuden
C7, C17
0
4.7uF
CAP, CERM, 4.7 uF, 25 V, +/10%, X6S, 0603
0603
GRM188C81E475KE11D
MuRata
C8
0
1uF
CAP, CERM, 1 uF, 25 V, +/- 10%,
X5R, 0402
0402
C1005X5R1E105K050BC
TDK
C10
0
100uF
CAP, CERM, 100 uF, 6.3 V, +/20%, X5R, 0805
0805
GRM21BR60J107M
MuRata
C11
0
47uF
CAP, CERM, 47 uF, 6.3 V, +/20%, X5R, 0805
0805
GRM219R60J476ME44D
MuRata
20
1x2
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Schematic and Bill of Materials
www.ti.com
Table 9. Bill of Materials (continued)
DESIGNATOR
QTY
VALUE
DESCRIPTION
PACKAGE
REFERENCE
PART NUMBER
MANUFACTURER
C13
0
4.7uF
CAP, CERM, 4.7 uF, 6.3 V, +/10%, X5R, 0603
0603
GRM188R60J475KE19D
MuRata
C15
0
0.47uF
CAP, CERM, 0.47 uF, 6.3 V, +/10%, X7R, 0603
0603
GRM188R70J474KA01D
MuRata
C16
0
0.1uF
CAP, CERM, 0.1 uF, 6.3 V, +/10%, X7R, 0603
0603
GRM188R70J104KA01D
MuRata
C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28,
C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39,
C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C109,
C110, C111, C112, C113, C114, C115, C116, C117, C118,
C119, C120, C121, C122, C123, C124, C125, C126, C127,
C128, C129, C130, C131, C132, C133, C134, C135, C136,
C137, C138, C139, C140
0
0.22uF
CAP, CERM, 0.22 uF, 10 V, +/20%, X5R, 0201
0201
LMK063BJ224MP-F
Taiyo Yuden
C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60
0
1pF
CAP, CERM, 1 pF, 50 V, +/- 10%,
C0G/NP0, 0402
0402
GJM1555C1H1R0BB01D
MuRata
C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71,
C72, C73, C74, C75, C76, C77, C78, C79, C80, C81, C82,
C83, C84, C85, C86, C87, C88, C89, C90, C91, C92, C93,
C94, C95, C96, C97, C98, C99, C100, C101, C102, C103,
C104, C105, C106, C107, C108
0
0.1uF
CAP, CERM, 0.1 uF, 6.3 V, +/10%, X5R, 0201
0201
C0603X5R0J104K030BC
TDK
D1
0
Green
LED, Green, SMD
2x1.4mm
LG M67K-G1J2-24-Z
OSRAM
DS1, DS2, DS3, DS4, US1, US2, US3, US4
0
DS160PR410, RNQ0040A
(WQFN-40)
RNQ0040A
DS160PR410
Texas Instruments
FID1, FID2, FID3, FID4, FID5, FID6
0
Fiducial mark. There is nothing to
buy or mount.
N/A
N/A
N/A
H9, H10
0
MACHINE SCREW PAN
PHILLIPS 4-40
Machine
Screw, 4-40,
1/4 inch
PMSSS 440 0025 PH
B and F Fastener
Supply
J5, J10
0
Header, 2.54mm, 2x1, TH
Header,
2.54mm, 2x1,
TH
961102-6404-AR
3M
J6, J7, J8, J9
0
Header, 2.54mm, 3x1, Gold, TH
Header,
2.54mm, 3x1,
TH
961103-6804-AR
3M
J14, J15, J17, J18
0
Header, 100mil, 12x2, Gold, TH
12x2 Header
TSW-112-07-G-D
Samtec
J16, J19
0
Header, 100mil, 5x2, Gold, TH
5x2 Header
TSW-105-07-G-D
Samtec
J20
0
Receptacle, 1mm, 82x2, Gold,
SMT
Receptacle,
1mm, 82x2,
SMT
GWE82DHRN-T9410
Sullins Connector
Solutions
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
21
Schematic and Bill of Materials
www.ti.com
Table 9. Bill of Materials (continued)
DESIGNATOR
QTY
J30, J31, J40, J41
0
L1
0
MP1
0
R11
0
R14
R15
DESCRIPTION
PACKAGE
REFERENCE
PART NUMBER
MANUFACTURER
SMA, Straight Jack, SMT
SMA
Connector,
SMT
732511352
Molex
Inductor, Drum Core, Ferrite, 6.8
uH, 3.2 A, 0.04 ohm, SMD
SDR0805
SDR0805-6R8ML
Bourns
PCI bracket
PCI_BRCKT_N 9B90-0000A
PTH_2
Gompf Brackets,
Inc.
330
RES, 330, 5%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW0402330RJNED
Vishay-Dale
0
165k
RES, 165 k, 1%, 0.1 W, 0603
0603
RC0603FR-07165KL
Yageo
0
120k
RES, 120 k, 1%, 0.1 W, 0603
0603
RC0603FR-07120KL
Yageo
R16
0
10.0k
RES, 10.0 k, 1%, 0.063 W, 0402
0402
RC0402FR-0710KL
Yageo America
R17
0
105k
RES, 105 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW0402105KFKED
Vishay-Dale
R18, R19, R20
0
100k
RES, 100 k, 1%, 0.0625 W, 0402
0402
RC0402FR-07100KL
Yageo America
R21
0
5.76k
RES, 5.76 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW04025K76FKED
Vishay-Dale
R22
0
165k
RES, 165 k, 1%, 0.1 W, AECQ200 Grade 0, 0402
0402
ERJ-2RKF1653X
Panasonic
R23
0
37.4k
RES, 37.4 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040237K4FKED
Vishay-Dale
R24
0
42.2k
RES, 42.2 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040242K2FKED
Vishay-Dale
R25
0
2.05k
RES, 2.05 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW04022K05FKED
Vishay-Dale
R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36
0
43
RES, 43, 5%, 0.063 W, AEC-Q200 0402
Grade 0, 0402
CRCW040243R0JNED
Vishay-Dale
R37, R38, R39, R40, R70, R71, R72, R73
0
4.70k
RES, 4.70 k, 1%, 0.063 W, 0402
0402
CRG0402F4K7
TE Connectivity
R41, R44, R47, R50, R53, R56, R61, R67, R74, R77, R80,
R83, R86, R89, R94, R100
0
1.00k
RES, 1.00 k, 1%, 0.063 W, 0402
0402
MCR01MZPF1001
Rohm
R42, R45, R48, R51, R54, R57, R63, R68, R75, R78, R81,
R84, R87, R90, R96, R101
0
13.0k
RES, 13.0 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040213K0FKED
Vishay-Dale
R43, R46, R49, R52, R55, R59, R65, R69, R76, R79, R82,
R85, R88, R92, R98, R102
0
59.0k
RES, 59.0 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040259K0FKED
Vishay-Dale
R58, R91
0
249
RES, 249, 1%, 0.1 W, AEC-Q200
Grade 0, 0402
0402
ERJ-2RKF2490X
Panasonic
R60, R93
0
3.24k
RES, 3.24 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW04023K24FKED
Vishay-Dale
22
VALUE
6.8uH
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Schematic and Bill of Materials
www.ti.com
Table 9. Bill of Materials (continued)
DESIGNATOR
QTY
VALUE
DESCRIPTION
PACKAGE
REFERENCE
PART NUMBER
MANUFACTURER
R62, R64, R66, R95, R97, R99
0
14.7k
RES, 14.7 k, 1%, 0.063 W, AECQ200 Grade 0, 0402
0402
CRCW040214K7FKED
Vishay-Dale
SH-J2, SH-J3, SH-J4, SH-J5, SH-J6, SH-J11, SH-J12, SH-J13,
SH-J14, SH-J15, SH-J16, SH-J17, SH-J18, SH-J19, SH-J20,
SH-J21, SH-J22, SH-J23, SH-J24, SH-J25, SH-J26
0
1x2
Shunt, 100mil, Flash Gold, Black
Closed Top
100mil Shunt
SPC02SYAN
Sullins Connector
Solutions
U3
0
1.5-V to 16-V VIN, 4.5-V to 22-V
VDD, 25-A SWIFT Synchronous
Step-Down Converter with Full
Differential Sense, RVF0040A
(LQFN-CLIP-40)
RVF0040A
TPS548B22RVFR
Texas Instruments
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
DS160PR410EVM-SMA Evaluation Module (EVM)
Copyright © 2019–2020, Texas Instruments Incorporated
23
Schematic and Bill of Materials
4.3
www.ti.com
REACH Compliance
In compliance with the Article 33 provision of the EU REACH regulation we are notifying you that this EVM
includes component(s) containing at least one Substance of Very High Concern (SVHC) above 0.1%.
These uses from Texas Instruments do not exceed 1 ton per year. The SVHC’s are shown in Table 10.
Table 10. REACH Affected Components
5
COMPONENT
MANUFACTU
RER
COMPONENT TYPE
COMPONENT
PART
NUMBER
SVHC SUBSTANCE
SVHC CAS (WHEN
AVAILABLE)
Molex
50 Ohms, SMA Jack, Vertical,
PCB SMT, Gold (Au) Body
732511352
Lead
7439-92-1
References
For references, see the following:
1. Texas Instruments, DS160PR410 4-Channel PCI-Express Gen-4 Linear Redriver Datasheet
(SNLS645)
2. Texas Instruments, DS160PR410 Programming Guide (SNLU255)
3. Texas Instruments, Understanding EEPROM Programming for DS160PR410 PCI-Express Gen-4
Redriver (SNLA320)
24
DS160PR410EVM-SMA Evaluation Module (EVM)
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Revision History
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2019) to A Revision ..................................................................................................... Page
•
•
Changed List Item 1 . ..................................................................................................................... 9
Added List Item 8 ........................................................................................................................ 10
SNLU251A – August 2019 – Revised January 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Revision History
25
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising