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Texas Instruments DS90UH941AS-Q1EVM (Rev. A) User guides
User's Guide
SNLU241A – December 2018 – Revised April 2019
DS90Ux941AS-Q1EVM User's Guide
The DS90Ux941AS-Q1EVM (Evaluation Module) converts DSI to FPD-Link III. This kit will demonstrate
the functionality and operation of the DS90Ux941AS-Q1. The DS90Ux941AS-Q1 is a DSI to FPD-Link III
Serializer which, in conjunction with the DS90Ux940-Q1/DS90Ux948-Q1 Deserializers, takes the data
from a DSI serial stream and translates it into either single- or dual-lane FPD-Link III interface. The
DS90Ux941AS-Q1 serializes a MIPI DSI input supporting video resolutions up to 2K, WUXGA and
1080p60 with 24-bit color depth.
Contents
1
General Description ......................................................................................................... 3
2
Features ....................................................................................................................... 3
3
System Requirements ....................................................................................................... 4
4
Contents of the Demo Evaluation Kit ..................................................................................... 4
5
Applications Diagram ........................................................................................................ 4
6
Typical Configuration ........................................................................................................ 4
7
Quick Start Guide ............................................................................................................ 5
8
Default Jumper Settings .................................................................................................... 6
9
Default Switch Settings ..................................................................................................... 6
10
Demo Board Connections .................................................................................................. 6
11
ALP Software Setup ....................................................................................................... 10
12
Troubleshooting ALP Software ........................................................................................... 19
13
Typical Connection and Test Equipment ................................................................................ 23
14
Equipment References .................................................................................................... 24
15
Cable References .......................................................................................................... 24
Appendix A
EVM PCB Schematics ............................................................................................ 29
Appendix B
Board Layout ....................................................................................................... 36
List of Figures
1
Applications Diagram ........................................................................................................ 4
2
Typical Configuration ........................................................................................................ 4
3
Interfacing to the EVM ...................................................................................................... 5
4
Launching ALP ............................................................................................................. 11
5
Initial ALP Screen .......................................................................................................... 11
6
Follow-Up Screen .......................................................................................................... 12
7
ALP Information Tab ....................................................................................................... 13
8
ALP Pattern Generator Tab ............................................................................................... 14
9
ALP Registers Tab ......................................................................................................... 15
10
ALP Device ID Selected ................................................................................................... 16
11
ALP Device ID Expanded ................................................................................................. 17
12
ALP Scripting Tab .......................................................................................................... 18
13
USB2ANY Setup ........................................................................................................... 19
14
Remove Incorrect Profile .................................................................................................. 19
15
Add Correct Profile ......................................................................................................... 20
16
Finish Setup ................................................................................................................. 20
17
ALP No Devices Error ..................................................................................................... 21
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1
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18
Windows 10, ALP USB Driver ............................................................................................ 21
19
ALP in Demo Mode ........................................................................................................ 22
20
ALP Preferences Menu .................................................................................................... 22
21
Typical Test Setup for Video Application
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
...............................................................................
Typical Test Setup for Evaluation .......................................................................................
Top Level Schematic ......................................................................................................
Main Schematic ............................................................................................................
Configuration Schematic ..................................................................................................
Schematic Connectors ....................................................................................................
Power Schematic ...........................................................................................................
Audio Schematic ...........................................................................................................
USB2Any Schematic.......................................................................................................
Top Overlay .................................................................................................................
Top Solder ..................................................................................................................
Layer1 Top ..................................................................................................................
Layer 6 Bottom .............................................................................................................
Layer6 Solder Bottom .....................................................................................................
Layer6 Bottom Overlay ....................................................................................................
Drill Drawing ................................................................................................................
Board Dimensions ..........................................................................................................
23
23
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
List of Tables
1
Default Board Jumper Settings ............................................................................................ 6
2
Default Board Switch Settings
3
Power Supply
4
5
6
7
8
9
10
11
12
13
14
............................................................................................. 6
................................................................................................................ 6
FPD-Link III Output Signals P1 ............................................................................................ 6
DSI Input Signals ............................................................................................................ 7
USB2ANY Connector ....................................................................................................... 7
I2C/CCI Interface Header ................................................................................................... 7
GPIO/Audio Interface ....................................................................................................... 7
SPI/D_GPIO Interface....................................................................................................... 8
MODE_SEL[1:0] Settings ................................................................................................... 8
Configuration Select (MODE_SEL0) - SW-DIP8 - S2 .................................................................. 8
Configuration Select (MODE_SEL1) - SW-DIP8 - S6 .................................................................. 9
IDx SW-DIP8 - S3 .......................................................................................................... 9
Bill of Materials ............................................................................................................. 25
Trademarks
All trademarks are the property of their respective owners.
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General Description
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1
General Description
The DS90Ux941AS-Q1EVM (Evaluation Module) converts DSI to FPD-Link III. This kit will demonstrate
the functionality and operation of the DS90Ux941AS-Q1. The DS90Ux941AS-Q1 is a DSI to FPD-Link III
Serializer which, in conjunction with the DS90Ux940-Q1/DS90Ux948-Q1 Deserializers, takes the data
from a DSI serial stream and translates it into either single- or dual-lane FPD-Link III interface. The
DS90Ux941AS-Q1 serializes a MIPI DSI input supporting video resolutions up to 2K, WUXGA and
1080p60 with 24-bit color depth.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including
I2C communication, over the same differential link. Consolidation of video data and control over two
differential pairs reduces the interconnect size and weight and simplifies system design. EMI is minimized
by the use of low voltage differential signaling, data scrambling, and randomization.
The demo board is not intended for EMI testing. The demo board was designed for easy accessibility to
device pins with tap points for monitoring or applying signals, additional pads for termination, and multiple
connector options.
2
Features
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified for Automotive Applications With the Following Results:
– Device Temperature Grade 2: −40℃ to +105℃ Ambient Operating Temperature
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C5
Supports Pixel Clock Frequency up to 210 MHz for 2K (2880x1080), WUXGA (1920x1200), or
1080p60 (1920x1080) Resolutions with 24-Bit Color Depth
MIPI D-PHY / Display Serial Interface (DSI) Receiver Provides a High-Bandwidth Interface to Video
Processor or FPGA
– DSI Input Port with Up to 4 Data Lanes
– Up to 1.5 Gbps Per Lane
– ECC and CRC Generation
– Virtual Channel Capability
Single and Dual FPD-Link III Outputs
– Single Link: Up to 105-MHz Pixel Clock
– Dual Link: Up to 210-MHz Pixel Clock
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System Requirements
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System Requirements
To demonstrate, the following is required:
1. FPD-Link III compatible Deserializer
1. DS90Ux940-Q1, DS90Ux948-Q1 up to 1080p60
2. DSI source
3. Optional I2C controller
4. Power supply for 12 V at 1 A (required)
4
Contents of the Demo Evaluation Kit
One EVM board with the DS90Ux941A-Q1
5
Applications Diagram
FPD-Link
(Open LDI)
FPD-Link III
CLK0+/-
DSI
DOUT0+
RIN0+
DOUT0-
RIN0-
DOUT1+
RIN1+
D2+/-
DOUT1-
RIN1-
D3+/-
D0+/D1+/-
CLK+/D0+/-
Processor
D1+/D2+/-
DS90Ux941AS
Serializer
DS90Ux948
Deserializer
CLK1+/-
LVDS
Display
or Graphic
Processor
D4+/-
D3+/-
D5+/I2C
IDx
I2C
IDx
D6+/-
HS_GPIO
(SPI)
HS_GPIO
(SPI)
D7+/-
Figure 1. Applications Diagram
6
Typical Configuration
Video Processor Board
( Video Data+ Ctrl + PCLK)
Video
Processor
DS90Ux941AS
(I2C)
Dual FPD- LINK III
Cluster, Head Unit
FPD- Link III
Deserializer
( OpenLDI)
Display
(I2C)
Figure 2. Typical Configuration
Figure 1 and Figure 2 show the use of the chipset in a display application.
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Quick Start Guide
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7
Quick Start Guide
1. Configure switches S2, S3, S5 and S6 to set device’s operating modes
• S2: MODE_SEL0 = 4 (default factory setting)
• S3: IDx = 1 (address 0x18 - default factory setting)
• S6: MODE_SEL1 = 1 (default factory setting)
• S5: PDB and INTB = OFF (PDB and INTB will be pulled up to VDDIO - default factory setting)
2. Connect P1 (DOUT[1:0]+/-) to a compatible Deserializer (for example, the DS90Ux940Q1/DS90Ux948-Q1) using STP cable (default)
3. Connect J28 to 12V.
a. Optional power options available (see Table 3)
4. Plug in DSI source to J8
5. Connect J14 with miniUSB (5-pin_ to USB A (4-pin)) cable to PC USB port
For details of pin names and pin functions, refer to the DS90Ux941AS-Q1 data sheets.
Figure 3. Interfacing to the EVM
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Default Jumper Settings
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Default Jumper Settings
Ensure that the board has the default board jumper settings:
Table 1. Default Board Jumper Settings
9
JUMPER
JUMPER SETTINGS
J3
Connect 2 and 3
J22/J23
Connect J22 pin 2 to J23 pin 2
J24
Connect 1 and 2
J25
Connect 1 and 2
J32
Connect 1 and 2
Default Switch Settings
Ensure that the board has the default board switch settings:
Table 2. Default Board Switch Settings
10
SWITCH
SWITCH SETTINGS
S1
1-3 ON
S2
4 ON, 1-3, 5-8 OFF
S3
1 ON, 2-8 OFF
S5
1-2 OFF
S6
1 ON, 2-8 OFF
Demo Board Connections
Table 3. Power Supply
DESIGNATOR
SIGNAL
DESCRIPTION
J28
+12 V
12 V ±5% Main Power
Single +12V power connector that supplies power to the entire board.
J27.1 (Optional)
+1.1 V
1.1 V ±5%
Alternative to Main Power. If used, remove R103.
J30.1 (Optional)
+1.8 V
1.8 V ±5%
Alternative to Main Power. If used, remove R109.
J31.1 (Optional)
+3.3 V
3.3 V ±5%
Alternative to Main Power. If used, remove R113.
J23.1 (Optional)
+5 V
5 V ±5%
Alternative to Main Power. If used, remove jumper to J22.
Table 4. FPD-Link III Output Signals P1
DESIGNATOR
P1.1
P1.3
P1.2
P1.4
6
DS90Ux941AS-Q1EVM User's Guide
PORT
SIGNAL
DOUT0-
FPD-Link III Port 0
DOUT0+
DOUT1-
FPD-Link III Port 1
DOUT1+
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Table 5. DSI Input Signals
DESIGNATOR
SIGNAL
DESCRIPTION
J8.33
J8.35
DSI0_D0_P
DSI0_D0_N
DSI0 D0 input
J8.25
J8.27
DSI0_D1_P
DSI0_D1_N
DSI0 D1 input
J8.17
J8.19
DSI0_CLK_P
DSI0_CLK_N
DSI0 CLK input
J8.9
J8.11
DSI0_D2_P
DSI0_D2_N
DSI0 D2 input
J8.1
J8.3
DSI0_D3_P
DSI0_D3_N
DSI0 D3 input
J8.34
J8.36
DSI1_D0_P
DSI1_D0_N
DSI1 D0 input
J8.26
J8.28
DSI1_D1_P
DSI1_D1_N
DSI1 D1 input
J8.18
J8.20
DSI1_CLK_P
DSI1_CLK_N
DSI1 CLK input
J8.10
J8.12
DSI1_D2_P
DSI1_D2_N
DSI1 D2 input
J8.2
J8.4
DSI1_D3_P
DSI1_D3_N
DSI1 D3 input
Table 6. USB2ANY Connector
DESIGNATOR
DESCRIPTION
J14
mini USB 5 pin
Table 7. I2C/CCI Interface Header
DESIGNATOR
SIGNAL
J11.1
VDDI2C
J11.2
SCL
J11.3
SDA
J1.4
GND
Table 8. GPIO/Audio Interface
DESIGNAT
OR
SIGNAL
DESCRIPTION
J12.2
I2S_DC/GPIO2
Slave Mode I2S Data Input / Remote or Local I/O
J12.4
I2S_DD/GPIO3
Slave Mode I2S Data Input / Remote or Local I/O
J12.8
I2S_DB/GPIO5_REG
Slave Mode I2S Data Input / Remote or Local I/O
J12.10
I2S_DA/GPIO6_REG
Slave Mode I2S Data Input / Remote or Local I/O
J12.12
I2S_WC/GPIO7_REG
Slave Mode I2S Word Clock Input / Remote or Local I/O
J12.14
I2S_CLK/GPIO8_REG
Slave Mode I2S Clock Input / Remote or Local I/O
J12.18
SDIN/GPIO0
Master I2S Data Input / Remote or Local I/O
J12.20
SWC/GPIO1
Master I2S Word Clock Input / Remote or Local I/O
J12.22
SCLK
Master I2S Clock Input
J12.24
MCLK
Master Mode I2S System Clock
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Demo Board Connections
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Table 9. SPI/D_GPIO Interface
DESIGNATOR
SIGNAL
DESCRIPTION
J12.26
D_GPIO0/MOSI
I/O in FPD-Link III mode / Master
Out, Slave In
J12.28
D_GPIO1/MISO
I/O in FPD-Link III mode / Master
In, Slave Out
J12.30
D_GPIO2/SPLK
I/O in FPD-Link III mode / Serial
Clock
J12.32
D_GPIO3/SS
I/O in FPD-Link III mode / Slave
Select
Configuration of the device may be done through the MODE_SEL[1:0]. These modes are latched into
register location during power-up:
Table 10. MODE_SEL[1:0] Settings
MODE
SETTING
Split
DSI Lanes
Non-continuous Clock Mode
COAX
Disable DSI
FUNCTION
0
Disable
1
Enable
00
1 DSI Lane
01
2 DSI Lanes
10
3 DSI Lanes
11
4 DSI Lanes
0
Continuous mode
1
Non-continuous mode
0
Enable FPD-Link III for twisted pair cabling
1
Enable FPD-Link III for coaxial cabling
0
Enable DSI
1
Disable DSI
Table 11. Configuration Select (MODE_SEL0) - SW-DIP8 - S2 (1)
VTARGET VOLTAGE RANGE
MODE
NO.
(1)
8
VTARGET
STRAP
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL)
SPLIT
DSI LANES
10.0
0
1
(V); V(VDD18) =
1.8 V
R3 (kΩ )
R4 (kΩ )
0
OPEN
VMIN
VTYP
VMAX
0
0
0
0.126 ×
V(VDD18)
1
0.179 ×
V(VDD18)
0.211 ×
V(VDD18)
0.244 ×
V(VDD18)
0.380
73.2
20.0
0
2
2
0.272 ×
V(VDD18)
0.325 ×
V(VDD18)
0.364 ×
V(VDD18)
0.585
60.4
30.1
0
3
3
0.404 ×
V(VDD18)
0.441 ×
V(VDD18)
0.472 ×
V(VDD18)
0.794
51.1
40.2
0
4
4
0.526 ×
V(VDD18)
0.556 ×
V(VDD18)
0.590 ×
V(VDD18)
1.001
40.2
51.1
1
1
5
0.643 ×
V(VDD18)
0.673 ×
V(VDD18)
0.708 ×
V(VDD18)
1.211
30.1
61.9
1
2
6
0.763 ×
V(VDD18)
0.790 ×
V(VDD18)
0.825 ×
V(VDD18)
1.421
18.7
71.5
1
3
7
0.880 ×
V(VDD18)
V(VDD18)
1.8
10
OPEN
1
4
V(VDD18)
Only set one high
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Table 12. Configuration Select (MODE_SEL1) - SW-DIP8 - S6 (1)
VTARGET VOLTAGE RANGE
MODE
NO.
(1)
VTARGET
STRAP
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL)
(V); V(VDD18)
= 1.8 V
R5 (kΩ )
R6 (kΩ )
0
OPEN
CLOCK
COAX
10.0
0
0
VMIN
VTYP
VMAX
0
0
0
0.126 ×
V(VDD18)
1
0.179 ×
V(VDD18)
0.211 ×
V(VDD18)
0.244 ×
V(VDD18)
0.380
73.2
20.0
0
0
2
0.272 ×
V(VDD18)
0.325 ×
V(VDD18)
0.364 ×
V(VDD18)
0.585
60.4
30.1
0
1
3
0.404 ×
V(VDD18)
0.441 ×
V(VDD18)
0.472 ×
V(VDD18)
0.794
51.1
40.2
0
1
4
0.526 ×
V(VDD18)
0.556 ×
V(VDD18)
0.590 ×
V(VDD18)
1.001
40.2
51.1
1
0
5
0.643 ×
V(VDD18)
0.673 ×
V(VDD18)
0.708 ×
V(VDD18)
1.211
30.1
61.9
1
0
6
0.763 ×
V(VDD18)
0.790 ×
V(VDD18)
0.825 ×
V(VDD18)
1.421
18.7
71.5
1
1
7
0.880 ×
V(VDD18)
V(VDD18)
1.8
10
OPEN
1
1
V(VDD18)
DISABLE
DSI
0
1
0
1
0
1
0
1
Only set one high
The strapped values can be viewed and/or modified in the following register locations:
• SPLIT : Latched into DUAL_CTL(0x5B[2:0]).
• DSI LANES : Latched into BRIDGE_CTL (0x4F[3:2]).
• CLOCK : Latched into BRIDGE_CTL (0x4F[7]).
• COAX : Latched into DUAL_CTL(0x5B[7]).
• DISABLE DSI : Latched into RESET (0x01[3]).
Table 13. IDx SW-DIP8 - S3 (1)
(1)
DESIGNATOR
7-BIT ADDRESS
S3.1 (Default)
0x0C
8-BIT ADDRESS
0x18
S3.2
0x0E
0x1C
S3.3
0x10
0x20
S3.4
0x12
0x24
S3.5
0x14
0x28
S3.6
0x16
0x2C
S3.7
0x18
0x30
S3.8
0x1A
0x34
Only set one high.
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ALP Software Setup
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ALP Software Setup
11.1 System Requirements
Operating System:
USB:
USB2ANY Firmware Version:
Windows 10 64-bit
USB2ANY
2.7.0.0
11.2 Download Contents
TI Analog LaunchPAD can be downloaded from: http://www.ti.com/tool/alp.
Download and extract the “snlc048.zip” file to a temporary location that can be deleted later.
Make sure J14 on the DS90Ux941AS-Q1 is connected to a PC USB port with USB cable and power is
applied to the DS90Ux941AS-Q1 EVM.
The following installation instructions are for the Windows 10 64-bit Operating System.
11.3 Installation of the ALP Software
Execute the ALP Setup Wizard program called “ALPF_setup_v_x_x_x.exe” that was extracted to a
temporary location on the local drive of your PC.
There are 7 steps to the installation once the setup wizard is started:
1. Select the "Next" button.
2. Select “I accept the agreement” and then select the “Next” button.
3. Select the location to install the ALP software and then select the “Next” button.
4. Select the location for the start menu shortcut and then select the “Next” button.
5. There will then be a screen that allows the creation of a desktop icon. After selecting the desired
choices select the “Next” button.
6. Select the “Install” button, and the software will then be installed to the selected location.
7. Uncheck “Launch Analog LaunchPAD” and select the “Finish” button. The ALP software will start if
“Launch Analog LaunchPAD” is checked, but it will not be useful until the USB driver is installed and
board is attached.
Connect J14 USB jack of the DS90Ux941AS-Q1Q EVM board to a PC/laptop USB port using a Type A
1
2
3
4
A to mini-B
1 2 3
4
MINI
USB cable. Power the DS90Ux941AS-Q1Q EVB board with a 12
VDC power supply. The “Found New Hardware Wizard” will open on the PC/laptop.
11.4 Installation of the Device Profiles
There are 2 steps to add the DS90Ux941AS-Q1 profile:
1. Download the ALP-PROFILE-UPDATE, snlc062.zip, from the TI Analog LaunchPAD page:
http://www.ti.com/tool/alp.
2. Extract the files and run the executable file ALP_PROFILE_UPDATE_v02_setup_v_x_x_x.exe. The
profile will be installed to the profile folder found at: C:\Program Files (x64)\Texas Instruments\Analog
LaunchPAD vx.x.x\Profiles\.
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11.5 Start-Up - Software Description
Make sure all the software has been installed and the hardware is powered on and connected to the PC.
Execute “Analog LaunchPAD” shortcut from the start menu. The default start menu location is under All
Programs > Texas Instruments > Analog LaunchPAD vx.x.x > Analog LaunchPAD to start MainGUI.exe.
Figure 4. Launching ALP
The application should come up in the state shown in the figure below. If it does not, see Section 12,
“Troubleshooting ALP Software”.
Under the Devices tab click on “DS90Ux941AS-Q1” to select the device and open up the device profile
and its associated tabs.
Figure 5. Initial ALP Screen
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After selecting the DS90Ux941AS-Q1, the screen shown in Figure 6 should appear.
Figure 6. Follow-Up Screen
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11.6 Information Tab
The Information tab is shown in Figure 7. Note that the device revision could be different.
Figure 7. ALP Information Tab
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ALP Software Setup
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11.7 Pattern Generator Tab
The SER Pattern Generator tab is shown in Figure 8.
Figure 8. ALP Pattern Generator Tab
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11.8 Registers Tab
The Register tab is shown in Figure 9.
Figure 9. ALP Registers Tab
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ALP Software Setup
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11.9 Registers Tab - Address 0x00 Selected
Figure 10 shows the Address 0x00 selected. Note that the “Value:” box (
hex value of that register.
) will now show the
Figure 10. ALP Device ID Selected
16
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ALP Software Setup
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11.10 Registers Tab - Address 0x00 Expanded
To expand Address 0x00, double-click the Address bar
or single-click the
. The expanded Address 0x00 reveals the content for each bits. Any register
address displayed can be expanded.
Figure 11. ALP Device ID Expanded
Users can change any RW Type register (
) by writing the hex value into the “Value:” box (
) or by clicking the checkboxes next to each register bit. A check mark indicates a "1" or R,
while a blank checkbox indicates a “0” or W. Click the “Apply” button to write to the register, and “refresh”
to see the new value of the selected (highlighted) register.
The box toggles on every mouse click.
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17
ALP Software Setup
www.ti.com
11.11 Scripting Tab
The Scripting tab is shown in Figure 12.
Figure 12. ALP Scripting Tab
The script window provides a full Python scripting environment to run scripts and interact with the device
in an interactive or automated fashion.
WARNING
Directly interacting with devices either through register
modifications or calling device support library functions can effect
the performance and/or functionality of the user interface and may
even crash the ALP Framework application.
18
DS90Ux941AS-Q1EVM User's Guide
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Troubleshooting ALP Software
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12
Troubleshooting ALP Software
12.1 ALP Loads the Incorrect Profile
If ALP opens with the incorrect profile loaded the correct profile can be loaded from the
USB2ANY/Aardvark Setup found under the tools menu.
Figure 13. USB2ANY Setup
Highlight the incorrect profile in the Defined ALP Devices list and press the remove button.
Figure 14. Remove Incorrect Profile
Find the correct profile under the Select a Daughter Board list, highlight the profile and press Add.
SNLU241A – December 2018 – Revised April 2019
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Troubleshooting ALP Software
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Figure 15. Add Correct Profile
Select Ok and the correct profile should now be loaded.
Figure 16. Finish Setup
20
DS90Ux941AS-Q1EVM User's Guide
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Troubleshooting ALP Software
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12.2 ALP Does Not Detect the EVM
If the window shown in Figure 17 opens after starting the ALP software, double-check the hardware setup.
Figure 17. ALP No Devices Error
It may also be that the USB driver is not installed. Check the device manager. There should be a “HIDcompliant device” under the “Human Interface Devices” as shown in Figure 18.
Figure 18. Windows 10, ALP USB Driver
The software should start with only “DS90Ux941AS-Q1” in the “Devices” drop-down menu. If there are
more devices then the software is most likely in demo mode. When the ALP is operating in demo mode
there is a “(Demo Mode)” indication in the lower left of the application status bar as shown in Figure 19.
SNLU241A – December 2018 – Revised April 2019
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Troubleshooting ALP Software
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Figure 19. ALP in Demo Mode
Disable the demo mode by selecting the “Preferences” drop-down menu and un-checking “Enable Demo
Mode”.
Figure 20. ALP Preferences Menu
After demo mode is disabled, the ALP software will poll the ALP hardware. The ALP software will update
and have only “DS90Ux941AS-Q1” under the “Devices” drop-down menu.
22
DS90Ux941AS-Q1EVM User's Guide
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Typical Connection and Test Equipment
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13
Typical Connection and Test Equipment
The following is a list of typical test equipment that may be used to generate signals for the Serializer
inputs:
1. Digital Video Source – for generation of specific display timing such as Digital Video Processor or
Graphics Controller (GPU) with OpenLDI output.
2. Any other signal generator / video source - This video generator may be used for video signal sources
for DVI or DP++
3. Any other signal / video generator that provides the correct input levels as specified in the data sheet.
Figure 21 shows a typical test setup using a Graphics Controller and display.
DS90Ux941A
EVM Board
Deserializer
Board
OpenLDI
LVDS
DSI
Generator
Display
FPD-Link III
Contents of Demo Kit
Graphics Controller /
Video Processor Board
Figure 21. Typical Test Setup for Video Application
Figure 22 shows a typical test setup using a video generator and logic analyzer.
Figure 22. Typical Test Setup for Evaluation
SNLU241A – December 2018 – Revised April 2019
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23
Equipment References
14
www.ti.com
Equipment References
NOTE: The following references are supplied only as a courtesy to our valued customers. It is not
intended to be an endorsement of any particular equipment or supplier.
Digital Video Pattern Generator:
Astrodesign
www.astro-americas.com
Logic Analyzer:
Keysight
www.keysight.com
Corelis CAS-1000-I2C/E I2C Bus Analyzer and Exerciser Products:
www.corelis.com/products/I2C-Analyzer.htm
Aardvark I2C/SPI Host Adapter Part Number: TP240141
www.totalphase.com/products/aardvark_i2cspi
15
Cable References
For optimal performance, TI recommends a Shielded Twisted-Pair (STP), 100-Ω differential impedance
and 24 AWG (or larger diameter) cable for high-speed data applications.
Leoni Dacar 538 series cable:
www.leoni-automotive-cables.com
Rosenberger HSD connector:
www.rosenberger.de/en/Products/35_Automotive_HSD.php
24
DS90Ux941AS-Q1EVM User's Guide
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SNLU241A – December 2018 – Revised April 2019
Bill of Materials
Table 14. Bill of Materials
ITEM DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QTY
1
!PCB1
Printed Circuit Board
Any
HSDC031
1
2
C1, C5, C6, C10, C11, C13,
C17, C32, C36, C43, C53,
C68, C72
CAP, CERM, 10 uF, 10 V, +/- 10%, X7R, 0805
MuRata
GRM21BR71A106KE51L
13
3
C2, C7, C12, C14, C15, C16,
CAP, CERM, 0.1 uF, 16 V, +/- 10%, X7R, 0402
C18, C19, C22, C23, C24,
C27, C28, C29, C35, C37,
C38, C41, C42, C52, C55,
C58, C61, C64, C67, C70, C71
MuRata
GRM155R71C104KA88D
27
4
C3, C9, C62
CAP, CERM, 0.01 uF, 100 V, +/- 5%, X7R, 0603
AVX
06031C103JAT2A
3
5
C4, C8
CAP, TA, 1 uF, 16 V, +/- 10%, 9.3 ohm, SMD
Vishay-Sprague
293D105X9016A2TE3
2
6
C20, C21
CAP, CERM, 4.7 pF, 25 V, +/- 5%, C0G/NP0,
0402
MuRata
GRM1555C1E4R7CA01D
2
7
C25, C26
CAP, CERM, 220 pF, 50 V, +/- 1%, C0G/NP0,
0603
AVX
06035A221FAT2A
2
8
C30, C31
CAP, CERM, 30 pF, 100 V, +/- 5%, C0G/NP0,
0603
MuRata
GRM1885C2A300JA01D
2
9
C33
CAP, CERM, 2200 pF, 50 V, +/- 10%, X7R, 0603
Kemet
C0603X222K5RACTU
1
10
C34
CAP, CERM, 0.47 uF, 16 V, +/- 10%, X7R, 0603
MuRata
GRM188R71C474KA88D
1
11
C39
CAP, CERM, 1.8 pF, 50 V, +/- 5%, C0G/NP0,
0402
MuRata
GRM1555C1H1R8CA01D
1
12
C40, C51, C66
CAP, CERM, 10 pF, 50 V, +/- 5%, C0G/NP0,
0402
MuRata
GRM1555C1H100JA01D
3
13
C44
CAP, CERM, 47 uF, 16 V, +/- 20%, X5R, 1210
MuRata
GRM32ER61C476ME15L
1
14
C45
CAP, TA, 100 uF, 16 V, +/- 20%, 0.1 ohm, SMD
Kemet
T495D107M016ATE100
1
15
C46
CAP, CERM, 1 uF, 16 V, +/- 10%, X7R, 0603
TDK
C1608X7R1C105K080AC
1
16
C47
CAP, CERM, 3300 pF, 50 V, +/- 10%, X7R, 0402
MuRata
GRM155R71H332KA01D
1
17
C48, C50
CAP, CERM, 1 uF, 16 V, +/- 10%, X5R, 0603
MuRata
GRM185R61C105KE44D
2
18
C49, C56
CAP, TA, 22 uF, 25 V, +/- 20%, 0.7 ohm, SMD
Vishay-Sprague
293D226X0025D2TE3
2
19
C54, C60, C63, C69
CAP, CERM, 4.7 µF, 25 V,+/- 10%, X7R, AECQ200 Grade 1, 0805
TDK
CGA4J1X7R1E475K125A
C
4
20
C57
CAP, TA, 2.2 uF, 25 V, +/- 10%, 6.3 ohm, SMD
Vishay-Sprague
293D225X9025A2TE3
1
21
C59, C65
CAP, CERM, 20 pF, 50 V, +/- 5%, C0G/NP0,
0402
MuRata
GRM1555C1H200JA01D
2
22
C75, C83, C90, C97, C104,
C112
CAP, CERM, 10 uF, 10 V, +/- 10%, X5R, 0805
Kemet
C0805C106K8PACTU
6
23
C76, C84, C91, C93, C98,
C105, C106, C107, C108,
C109, C110, C111, C113
CAP, CERM, 1 uF, 16 V, +/- 10%, X5R, 0603
Kemet
C0603C105K4PACTU
13
24
C77, C78, C79, C80, C85,
C86, C87, C92, C94, C99,
C100, C101, C114
CAP, CERM, 0.1 uF, 25 V, +/- 10%, X7R, 0603
AVX
06033C104KAT2A
13
25
C115, C116, C117, C118
CAP, CERM, 0.1 uF, 50 V, +/- 10%, X7R, 0402
TDK
C1005X7R1H104K050BB
4
26
C119, C120
CAP, CERM, 0.012 uF, 16 V, +/- 10%, X7R,
0402
MuRata
GRM155R71C123KA01D
2
27
D1
LED, Green, SMD
Lite-On
LTST-C190GKT
1
28
D2
Diode, Schottky, 40 V, 1 A, SOD-123
Diodes Inc.
1N5819HW-7-F
1
29
D3, D4
LED, Orange, SMD
Lite-On
LTST-C190KFKT
2
SNLU241A – December 2018 – Revised April 2019
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Bill of Materials
25
www.ti.com
Table 14. Bill of Materials (continued)
26
ITEM DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QTY
30
F1
Fuse, 7 A, 24VAC/VDC, SMD
Littelfuse
0429007.WRML
1
31
GND1, TP4, VDD1
Terminal, Turret, TH, Double
Keystone
1502-2
3
32
H1, H4, H6, H8
Machine Screw, Round, #4-40 x 1/4, Nylon,
Philips panhead
B and F Fastener
Supply
NY PMS 440 0025 PH
4
33
H2, H3, H5, H7
Standoff, Hex, 0.5"L #4-40 Nylon
Keystone
1902C
4
34
J1
Audio Jack, 3.5mm, Stereo, R/A, SMT
CUI Inc.
SJ-3523-SMT
1
35
J2, J4, J5, J6, J7, J9, J10, J15,
J16, J17, J18, J19, J21, J24,
J25, J26, J27, J30, J31, J32
Header, 100mil, 2x1, Gold, TH
TE Connectivity
5-146261-1
20
36
J3, J22, J23, J29
Header, 100mil, 3x1, Gold, TH
Samtec
TSW-103-07-G-S
4
37
J8
Receptacle, Differential, 0.5mm, 10 pair x2, Gold,
SMT
Samtec
QSH-020-01-H-D-DP-A
1
38
J11
Header (friction lock), 100mil, 4x1, Gold, TH
Molex
0022112042
1
39
J12
Header, 100mil, 16x2, Gold, TH
Samtec
TSW-116-07-G-D
1
40
J13
Header, 100mil, 4x1, Gold, TH
Samtec
TSW-104-07-G-S
1
41
J14
Connector, Receptacle, Mini-USB Type B, R/A,
Top Mount SMT
TE Connectivity
1734035-2
1
42
J28
Connector, DC Jack 2.1X5.5 mm, TH
CUI Inc.
PJ-102A
1
43
L1, L2, L5
Ferrite Bead, 330 ohm @ 100 MHz, 1.5 A, 0603
MuRata
BLM18SG331TN1D
3
44
L6
Inductor, Shielded Drum Core, Ferrite, 4.7 uH,
4.2 A, 0.02 ohm, SMD
Wurth Elektronik
7440650047
1
45
L7
Ferrite Bead, 1000 ohm @ 100 MHz, 0.3 A, 0805
Taiyo Yuden
BK2125HS102-T
1
46
L8, L9, L10
Ferrite Bead, 120 ohm @ 100 MHz, 3 A, 0603
MuRata
BLM18SG121TN1D
3
47
LBL 1
Thermal Transfer Printable Labels, 1.250" W x
0.250" H - 10,000 per roll
Brady
THT-13-457-10
1
48
P1
HSD Right Angle Plug, 4-Leads, 2mm Pitch, TH
Rosenberger
D4S20F-40MA5-Z
1
49
Q1, Q2, Q3
MOSFET, N-CH, 50 V, 0.22 A, SOT-23
Fairchild
Semiconductor
BSS138
3
50
R1, R2
RES, 100, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW0402100RFKED
2
51
R3, R7, R8, R10, R67, R70,
R71, R72, R73, R74, R75,
R76, R77, R78, R79, R105,
R112, R114, R115, R121,
R122, R123, R124, R125,
R126, R127, R129, R130,
R131, R132, R133, R134,
R135, R136, R137, R138,
R139, R140
RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0402
Panasonic
ERJ-2GE0R00X
38
52
R4, R5, R6, R9, R18, R27,
R29, R38, R54, R56, R66,
R85, R86, R95, R98, R101
RES, 10.0 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040210K0FKED
16
53
R12, R21, R35, R44, R48, R62 RES, 64.9 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040264K9FKED
6
54
R13, R22, R34, R43, R49, R61 RES, 40.2 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040240K2FKED
6
55
R14, R23, R33, R42, R50, R60 RES, 41.2 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040241K2FKED
6
56
R15, R24, R32, R41, R51, R59 RES, 30.9 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040230K9FKED
6
57
R16, R25, R31, R40, R52
RES, 16.2 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040216K2FKED
5
58
R17, R26, R30, R39, R53, R57 RES, 10.7 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040210K7FKED
6
59
R65
RES, 1.00 k, 1%, 0.1 W, 0402
Panasonic
ERJ-2RKF1001X
1
60
R68, R69, R116, R117, R118,
R128
RES, 4.7 k, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW04024K70JNED
6
61
R80, R81
RES, 33, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040233R0JNED
2
62
R82, R87, R88
RES, 1.5 k, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW04021K50JNED
3
Bill of Materials
SNLU241A – December 2018 – Revised April 2019
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www.ti.com
Table 14. Bill of Materials (continued)
ITEM DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QTY
63
R83, R90
RES, 33 k, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040233K0JNED
2
64
R84
RES, 1.2 M, 5%, 0.1 W, AEC-Q200 Grade 0,
0603
Vishay-Dale
CRCW06031M20JNEA
1
65
R89
RES, 200, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW0402200RJNED
1
66
R91
RES, 22.1 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040222K1FKED
1
67
R92
RES, 121 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW0402121KFKED
1
68
R93, R102, R110, R111
RES, 100 k, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW0402100KJNED
4
69
R94, R96, R103, R109, R113
RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CRCW06030000Z0EA
5
70
R97
RES, 29.4 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040229K4FKED
1
71
R99, R100
RES, 3.24 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW04023K24FKED
2
72
R104
RES, 1.87 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW04021K87FKED
1
73
R106
RES, 4.99 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW04024K99FKED
1
74
R107
RES, 23.2 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040223K2FKED
1
75
R108
RES, 12.1 k, 1%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW040212K1FKED
1
76
R119, R120
RES, 470, 5%, 0.063 W, AEC-Q200 Grade 0,
0402
Vishay-Dale
CRCW0402470RJNED
2
77
S1
Switch, Slide, SPST 3 poles, SMT
CTS
Electrocomponents
219-3LPST
1
78
S2, S3, S6
Switch, Slide, SPST 8 poles, SMT
CTS
Electrocomponents
219-8MST
3
79
S4, S7, S8
SWITCH TACTILE SPST-NO 0.02A 15V, TH
Panasonic
EVQ-PAD04M
3
80
S5
Switch, 2 SPST, 0.15 A, 30 V, TH
Grayhill
78B02ST
1
81
SH-J1, SH-J2, SH-J3, SH-J4,
SH-J5
Shunt, 2mm, Gold plated, Black
Samtec
2SN-BK-G
5
82
U1
99dB SNR Stereo ADC with Single-Ended Inputs, Texas Instruments
PW0014A (TSSOP-14)
PCM1808PWR
1
83
U2
ESD-Protection Array for High-Speed Data
Interfaces, 4 Channels, -40 to +85 degC, 6-pin
SON (DRY), Green (RoHS and no Sb/Br)
Texas Instruments
TPD4E004DRYRG4
1
84
U3
6-Bit Bidirectional Voltage-Level Translator with
Auto Direction Sensing and +/-15-kV ESD
Protect, PW0016A (TSSOP-16)
Texas Instruments
TXB0106PWR
1
85
U4
TCA9406 Dual Bidirectional 1-MHz I2C-BUS and
SMBus Voltage Level-Translator, 1.65 to 3.6 V,
-40 to 85 degC, 8-pin US8 (DCU), Green (RoHS
and no Sb/Br)
Texas Instruments
TCA9406DCUR
1
86
U5
25 MHz Mixed Signal Microcontroller with 128 KB Texas Instruments
Flash, 8192 B SRAM and 63 GPIOs, -40 to 85
degC, 80-pin QFP (PN), Green (RoHS and no
Sb/Br)
MSP430F5529IPN
1
87
U6
4.5V to 18V Input, 2A Synchronous Step-Down
Converter, PWP0014E (TSSOP-14)
Texas Instruments
TPS54225PWPR
1
88
U7
1A Low Dropout Adjustable Regulator,
NGN0008A (WSON-8)
Texas Instruments
LM2941LD/NOPB
1
89
U8
Single Output LDO, 500 mA, Adjustable 0.8 to
3.6 V Output, 0.8 to 5.5 V Input, with
Programmable Soft Start, 10-pin SON (DRC), -40
to 125 degC, Green (RoHS and no Sb/Br)
Texas Instruments
TPS74701DRCR
1
90
U9
Dual Output LDO, 1 A, Fixed 1.8, 3.3 V Output,
2.7 to 10 V Input, 28-pin HTSSOP (PWP), -40 to
125 degC, Green (RoHS and no Sb/Br)
Texas Instruments
TPS767D318PWP
1
SNLU241A – December 2018 – Revised April 2019
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Bill of Materials
27
www.ti.com
Table 14. Bill of Materials (continued)
28
ITEM DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QTY
91
U10
Ultra-Low Jitter Programmable Oscillator with
Internal EEPROM, SIA0008B (QFM-8)
Texas Instruments
LMK61E0M-SIAR
1
92
U11
DSI to FPD-Link III Bridge Serializer with HDCP,
RTD0064F (VQFNP-64)
Texas Instruments
DS90UH941ASRTDRQ1
or
DS90UB941ASRTDRQ1
1
93
Y1
OSC, 12.288 MHz, 3.3 Vdc, SMD
ECS Inc.
ECS-8FA3X-122.8-TR
1
94
Y2
Crystal, 24.000 MHz, 20pF, SMD
ECS Inc.
ECS-240-20-5PX-TR
1
Bill of Materials
SNLU241A – December 2018 – Revised April 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
Appendix A
SNLU241A – December 2018 – Revised April 2019
EVM PCB Schematics
REF OSC
LEDs
FPD3
DSI
DS90UX941AS-Q1
FPD3
USB-2-ANY
EXT UC
MODE_SEL
I2C
EXT CONN
IDx
SPI/D_GPIO
GPIO
I2S
INTB
5V
USB
3.3V
Power
Power
Audio
1.8V
1.1V
ADC
Figure 23. Top Level Schematic
SNLU241A – December 2018 – Revised April 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
EVM PCB Schematics
29
Appendix A
www.ti.com
L7
by pin 51
VDD18
VDD1V8
by pin 24
by pin 64
C73
47uF
C74
4.7uF
by pin 42
L8
VDD18
by pin 9
VDDL11
VDD11
1000 ohm
C75
10uF
C76
1uF
C77
0.1uF
C78
0.1uF
C79
0.1uF
C80
0.1uF
C81
47uF
C82
4.7uF
C83
10uF
C84
1uF
C85
0.1uF
C86
0.1uF
C87
0.1uF
L9
GND
by pin 50
GND
120 ohm
by pin 33
C88
47uF
C89
4.7uF
VDDL11
120 ohm
C90
10uF
by pin 33
C91
1uF
by pin 16
C92
0.1uF
C93
1uF
by pin 16
VDDIO
C95
47uF
VDDIO
C96
4.7uF
C94
0.1uF
C97
10uF
C98
1uF
C99
0.1uF
C104
C105
C106
120 ohm
C102
47uF
C103
4.7uF
10uF
1uF
1uF
by pin 21
C107
1uF
by pin 25
C108
1uF
VDDP11
0.1uF
by pin 12
VDDHS11
GND
VDDHS11
by pin 64
C109
1uF
VDDP11
C101
0.1uF
by pin 28
L10
GND
by pin 17
C100
C110
1uF
C111
1uF
GND
VDD33
VDD33
U10
C112
10uF
C113
1uF
C114
0.1uF
6
7
OSC EN
VDDHS11
J32
VDDHS11
8
GND
1
U11
VDD
OUTP
SDA
OUTN
SCL
ADD
OE
GND
REFCLK
4
5
R115
2
0
3
SH-J5
DSI0_D1_P
DSI0_D1_N
DSI0_D2_P
DSI0_D2_N
DSI0_D3_P
DSI0_D3_N
DSI0_D0_P
DSI0_D0_N
58
57
DSI0_D1_P
DSI0_D1_N
56
55
DSI0_D2_P
DSI0_D2_N
54
53
DSI0_D3_P
DSI0_D3_N
52
51
DSI1_CLK_P
DSI1_CLK_N
DSI1_CLK_P
DSI1_CLK_N
DSI1_D0_P
DSI1_D0_N
DSI1_D1_P
DSI1_D1_N
DSI1_D2_P
DSI1_D2_N
DSI1_D3_P
DSI1_D3_N
PDB
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
I2S_DA/GPIO6_REG
I2S_DB/GPIO5_REG
I2S_DC/GPIO2
I2S_DD/GPIO3
8
7
DSI1_D0_P
DSI1_D0_N
6
5
DSI1_D1_P
DSI1_D1_N
4
3
DSI1_D2_P
DSI1_D2_N
2
1
DSI1_D3_P
DSI1_D3_N
63
62
R131
0
31
R134
R135
R136
R138
R139
R140
0
0
0
0
0
0
34
35
36
37
38
39
VDD11_DSI
DSI0_CLKP
DSI0_CLKN
DSI0_D0P
DSI0_D0N
DOUT0+
DOUT0DOUT1+
DOUT1LFDSI
DSI0_D1P
DSI0_D1N
DSI0_D2P
DSI0_D2N
REFCLK0
LFT
IDX
DSI0_D3P
DSI0_D3N
DSI1_CLKP
DSI1_CLKN
DSI1_D0P
DSI1_D0N
DSI1_D1P
DSI1_D1N
DSI1_D2P
DSI1_D2N
DSI1_D3P
DSI1_D3N
PDB
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
I2S_DA/GPIO6_REG
I2S_DB/GPIO5_REG
I2S_DC/GPIO2
I2S_DD/GPIO3
25
12
C115
50V
DOUT0_P
0.1uF
DOUT0_P
17
C116
DOUT0_N
50V
0.1uF
DOUT0_N
R117
4.7k
MODE_SEL0
MODE_SEL1
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
I2C_SDA
I2C_SCL
INTB
REM_INTB
RES2
GPIO0
GPIO1
REFCLK1
RES
RES
PAD
GND
R118
4.7k
GND
SCL_MSP
27
26
DOUT0_A_P
DOUT0_A_N
C117
DOUT1_P
50V
0.1uF
DOUT1_P
23
22
DOUT1_B_P
DOUT1_B_N
C118
50V DOUT1_N
0.1uF
DOUT1_N
49
C119
41
SDA_MSP
12nF
VDD5V
REFCLK
C120
20
12nF
GND
GND
19
IDx
1
DSI0_D0_P
DSI0_D0_N
60
59
VDDP11
R116
4.7k
VDDIO
18
LABEL REM_INTB
D4
Orange
Orange
LABEL INTB
MODE_SEL0
32
MODE_SEL1
R121
R122
R123
R124
46
45
44
43
48
47
30
10
R125
R126
13
14
15
11
R129
R130
R132
R133
29
40
D3
2
DSI0_CLK_P
DSI0_CLK_N
DSI0_CLK_P
DSI0_CLK_N
VDDS11
VDDA11
LMK61E0M-SIAR
VDDP11
0
0
0
0
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
0
0
R127
R128
R137
0
0
0
0
SDA
SCL
0
4.7k
SDA
SCL
INTB
VDDIO
REM_INTB
SCLK
SDIN/GPIO0
SWC/GPIO1
MCLK
R119
470
R120
470
Q2
Q3
3
64
VDDL11
VDDL11
VDDP11
1
GND
1
REM_INTB
INTB
2
9
42
50
21
28
1
VDDL11
VDDIO
VDDIO
VDD11P
VDDHS11
VDDHS11
2
VDDIO
16
33
VDD18
VDD18
3
24
61
2
VDD18
GND
0
65
DS90UH941ASRTDRQ1
GND
Figure 24. Main Schematic
30
EVM PCB Schematics
SNLU241A – December 2018 – Revised April 2019
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VDD18
VDD18
R11
0
R12
64.9k
R13
40.2k
R14
41.2k
R15
30.9k
R16
16.2k
R17
10.7k
R18
10.0k
R19
0
R20
0
R21
64.9k
R22
40.2k
R23
41.2k
R24
30.9k
R25
16.2k
R26
10.7k
R27
10.0k
R28
0
R29
10.0k
R30
10.7k
R31
16.2k
R32
30.9k
R33
41.2k
R34
40.2k
R35
64.9k
R36
0
R37
0
R38
10.0k
R39
10.7k
R40
16.2k
R41
30.9k
R42
41.2k
R43
40.2k
R44
64.9k
R45
0
R46
0
GND
GND
16
15
14
13
12
11
10
9
GND
16
15
14
13
12
11
10
9
GND
S2
S3
1
2
3
4
5
6
7
8
I2C Address Select (IDx)
1
2
3
4
5
6
7
8
Mode Select 0 (MODE_SEL0)
MODE_SEL0
IDx
1
2
3
4
5
6
7
8
J4
J5
'b
8
C16
x
1
0
8
x
1
0
C
x
2
0
x
2
0
4
x
2
0
8
x
2
0
C
x
3
0
x
3
0
4
C15
16V
0.1uF
7'b
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x20
16V
0.1uF
GND
GND
VDD18
R47
0
R48
64.9k
R49
40.2k
R50
41.2k
R51
30.9k
R52
16.2k
R53
10.7k
R54
10.0k
R55
0
R56
10.0k
R57
10.7k
R58
16.2k
R59
30.9k
R60
41.2k
R61
40.2k
R62
64.9k
R63
0
R64
0
VDDIO
J6
PDB
INTB
R67
0
4
GND
R66
10.0k
2
GND
R65
10.0k
4
3
SW4
B3F-1000
16
15
14
13
12
11
10
9
PDB / INTB Switches
GND
C17
10µF
GND
1
2
3
4
5
6
7
8
D
B
P
N
IT
B
S6
Mode Select 1 (MODE_SEL1)
3
1
1
2
S5
GND
1
2
3
4
5
6
7
8
MODE_SEL1
J7
C18
16V
0.1uF
GND
Figure 25. Configuration Schematic
SNLU241A – December 2018 – Revised April 2019
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31
Appendix A
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NT1
4
3
DOUT0_P
DOUT0_P
NT2
2
DOUT0_N
DOUT0_N
1
L3
P1
D4S20F-40MA5-Z
DSI
J8
DSI0_D2_P
DSI0_D2_N
1
3
2
4
5
7
6
8
9
11
10
12
13
15
14
16
17
19
18
20
21
23
22
24
25
27
26
28
29
31
30
32
33
35
34
36
37
39
38
40
DSI1_D3_P
DSI1_D3_N
DSI1_D3_P
DSI1_D3_N
PAIR A1
SMAD1_N
J9
DSI1_D2_P
DSI1_D2_N
1
3
2
4
PAIR A2
REM_INTB
DSI1_D2_P
DSI1_D2_N
NT3
DOUT1_P
DOUT1_P
SMAD1_P
3
DSI0_D2_P
DSI0_D2_N
DSI0_D3_P
DSI0_D3_N
4
DSI0_D3_P
DSI0_D3_N
SMAD0_N
SMAD0_P
L4
GND
DSI0_D1_P
DSI0_D1_N
DSI0_D1_P
DSI0_D1_N
DSI1_CLK_P
DSI1_CLK_N
DSI1_CLK_P
DSI1_CLK_N
DOUT1_N
DOUT1_N
2
DSI0_CLK_P
DSI0_CLK_N
1
GND
DSI0_CLK_P
DSI0_CLK_N
NT4
J10
DSI1_D1_P
DSI1_D1_N
INTB
DSI1_D1_P
DSI1_D1_N
GND
DSI0_D0_P
DSI0_D0_N
DSI0_D0_P
DSI0_D0_N
PDB
SDA
PDB
SDA
MP1
MP3
DSI1_D0_P
DSI1_D0_N
DSI1_D0_P
DSI1_D0_N
VDDIO
SCL
SCL
R68
4.7k
MP2
MP4
SCL
SDA
SCL
SDA
C19
16V
0.1uF
R69
4.7k
R70
R71
0
J11
GND
0
C20
50V
4.7pF
GND
VDDIO
1
2
3
4
C21
50V
4.7pF
Ground
GND
J12
PDB_CTRL
INTB_CTRL
GPIO0/I2C(SDA)
GPIO1/I2C(SCL)
GPIO4/SPI(SIMO)/UART(TXD)
GPIO5/SPI(SOMI)/UART(RXD)
GPIO2/SPI(SCLK)
GPIO6/PWM1/SPI(CS)
R72
R73
R74
R75
R76
R77
R78
R79
0
0
0
0
0
0
0
0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
PDB
INTB
SDA
SCL
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
I2S_DC/GPIO2
I2S_DD/GPIO3
I2S_DB/GPIO5_REG
I2S_DA/GPIO6_REG
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
SDIN/GPIO0
SWC/GPIO1
SCLK
MCLK
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
J13
GND
1
2
3
4
DAOUT
LRCK
BCK
SCKIN
Figure 26. Schematic Connectors
32
EVM PCB Schematics
SNLU241A – December 2018 – Revised April 2019
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C39 50V
C40 50V
1.8pF
10pF
R91
R92
22.1k
121k
5V
GND
U6
C41
VDD_EXT
13
14
GND
5V_SW
1
VIN
VBST
VCC
SW1
SW2
VO
PG
2
4
C47
50V
3300pF
7
VFB
VREG5
SS
GND
EN
PGND1
PGND2
PAD
VDD5V
VBUS
5V_LDO
12
J22 J23
3
2
1
L6
16V
0.1uF
10
11
5V_SW
4.7uH
R93
6
C42
16V
0.1uF
100k
3
C43
10V
10µF
VBUS
5V_LDO
5V_SW
C44
16V
47uF
5V
1
2
3
C45
100uF
SH-J2
TP1
5
C46
16V
1uF
8
9
15
5V_LDO DISABLE
VDD_EXT
5V@1A LDO POWER SUPPLY
R94
R95
U7
0
10.0k
3
J24
J25
1
R98
5V_SW DISABLE
R100
VDD_EXT
GND
R99
3.24k
10.0k
SH-J3
IN
OUT
ON/OFF
ADJ
NC
NC
GND
GND
DAP
GND
GND
C48 16V
7
2
9
C50
16V
1uF
LM2941LD/NOPB
0
R97
29.4k
R101
10.0k
GND
C49
22uF
TP2
R102
TP3
GND
100k
R103
1
2
VDD5V
C54
C55
16V
0.1uF
R105
0
5
4
7
C60
4.7µF
C61
16V
0.1uF
C62
TP4
VDD11
IN
IN
PG
FB
EN
OUT
OUT
BIAS
EP
GND
SS
3
8
R104
9
10
1.87k
TP5
C51
50V
10pF
C52
16V
0.1uF
11
6
C53
10V
10µF
J27
1V1
GND
D2
J28
R106
4.99k
TPS74701DRCR
VDD_EXT
1
3
2
GND
0.01uF
C59
50V
20pF
C56
22uF
12V@1A
GND
GND
GND
1
2
7
8
13
14
15
VDD5V
C64
16V
0.1uF
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C65 20pF
5
6
11
12
1IN
1IN
1OUT
1OUT
2IN
2IN
2OUT
2OUT
1RESET
2RESET
GND
0
TP9
R114
0
TP10
4
10
1EN
2EN
GND
50V
10pF
GND
R112
GND
R107 23.2k
R108 C66
12.1k
C70
16V
0.1uF
C58
16V
0.1uF
GND1
16
19
20
21
25
26
27
U9A
C69
4.7µF
C57
2.2uF
U9B TPS767D318PWP
GND
C63
4.7µF
GND
0
U8
4.7µF
R96
5
8
1uF
4
6
J26
3.24k
GND
5V_LDO
GND
GND
TPS54225PWPR
GND
J21
EP
1GND
2GND
50V
TP6
R109 0
23
24
C67
16V
0.1uF
17
18
28
22
R110
R111
100k
100k
TP7
TP8
C68
10V
10µF
VDD1V8
J30
1V8
GND
GND
29
3
9
VDD1
R113
0
VDD33
TPS767D318PWP
GND
C71
16V
0.1uF
GND
C72
10V
10µF
J31
3V3
GND
GND
Figure 27. Power Schematic
SNLU241A – December 2018 – Revised April 2019
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33
Appendix A
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VDD5V
L1
10V
10µF
2
16V
0.1uF
3
4
VDD33
C11
5
10V
10µF
C12
16V
0.1uF
C3 0.01uF
6
7
VREF
VINR
AGND
VINL
VCC
FMT
VDD
MD1
DGND
MD0
SCKI
LRCK
C4
R1
U1
1
C7
L2
C10
10V
10µF
GND
DOUT
BCK
14
1uF
2
3
1
100
13
R2
12
FMT
11
MD1
10
MD0
FMT
C9
MD1
100
C8
J1
GND
1uF
0.01uF
MD0
9
GND
8
PCM1808PWR
VDD33
R5
GND
10V
10µF
C14
16V
0.1uF
Y1
0
J2
4
1
VCC
OUTPUT
TRI-STATE
GND
R7
3
2
R8
R9
10.0k
R10
0
0
0
DAOUT
10.0k
R3
GND
C13
R4
C6
10V
10µF
C2
16V
0.1uF
10.0k
C5
10V
10µF
10.0k R6
C1
GND
BCK
LRCK
FMT
MD0
SCKIN
MD0
MD1
S1B
6
S1C
1
2
SH-J1
3
5
J3
4
3
2
1
MD1
FMT
S1A
GND
GND
Figure 28. Audio Schematic
34
EVM PCB Schematics
SNLU241A – December 2018 – Revised April 2019
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Appendix A
8
9
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J14
VBUS
DD+
ID
R80
33
R81
33
DM
4
DP
5
2
1
IO2
IO1
VCC
6
7
PUR
1.5k
IO4
IO3
GND
1
2
R84
1.2M
GND
4
3
BSL
GND
U3
2
GND
VUSB
1
3
4
5
6
7
PDB_CTRL
INTB_CTRL
GPIO6/PWM1/SPI(CS)
GPIO2/SPI(SCLK)
GPIO4/SPI(SIMO)/UART(TXD)
GPIO5/SPI(SOMI)/UART(RXD)
C25
220pF
GND
GND
R85
VDDIO
VDD33_UC
C23
16V
0.1uF
5
4
3
C22
J15
S7
C24
16V
0.1uF
33k
VDD33_UC
VDDIO
R82
U2
R83
VBUS
F1
2
3
6
GND
Fuse 7A, 24VAC / VDC
1
8
16V
0.1uF
VCCA
15
VCCB
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
OE
GND
GND
16
14
13
12
11
10
SCLK
SIMO
SOMI
PDB_MS430
INTB_MS430
CS
SCLK
SIMO
SOMI
9
10.0k
GND
TXB0106PWR
GND
SDA_MSP
SCL_MSP
U4
5
4
GPIO1/I2C(SCL)
GPIO0/I2C(SDA)
V18
R86
C26
220pF
10.0k
6
3
7
VDDIO
SCL_A
SDA_A
SCL_B
SDA_B
8
1
OE
VCCA
VCCB
GND
2
VDD33_UC
TCA9406DCUR
GND
C27
16V
0.1uF
J16
C28
16V
0.1uF
GND
U5
R88
1.5k
37
38
39
40
41
42
43
44
GPIO11/VEREF+
C29
16V
0.1uF
J18
9
10
69
70
12
13
55
56
GND
C30
30pF
100V
Y2
24MHz
C31
5
6
7
8
57
58
59
60
30pF
100V
GND
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
P5.0/A8/VREF+/VEREF+
P5.1/A9/VREF-/VEREFP5.2/XT2IN
P5.3/XT2OUT
P5.4/XIN
P5.5/XOUT
P5.6/TB0.0
P5.7/TB0.1
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P7.4/TB0.2
P7.5/TB0.3
P7.6/TB0.4
P7.7/TB0CLK/MCLK
J20
V18
VCORE
VBUS
VDD33
65
66
VUSB
L5
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P8.0
P8.1
P8.2
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
RST/NMI/SBWTDIO
TEST/SBWTCK
67
20
V18
C34
16V
0.47uF
P4.0/PM_UCB1STE/PM_UCA1CLK
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.6/PM_NONE
P4.7/PM_NONE
VDD33_UC
11
18
50
330 ohm
PU.0/DP
PU.1/DM
PUR
VBUS
VUSB
AVCC1
DVCC1
DVCC2
VSSU
AVSS1
AVSS2
DVSS1
DVSS2
29
30
31
32
33
34
35
36
CS
INTB_MS430
1
J17
D1
Green
PDB_MS430
SCLK
45
46
47
48
51
52
53
54
VDD33_UC
2
R87
1.5k
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
SCLK
R89
200
SIMO
SOMI
SIMO
SOMI
3
VDD33_UC
VDD33_UC
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
1
Q1
77
78
79
80
1
2
3
4
2
21
22
23
24
25
26
27
28
J19
MSP430 RESET
GND
S8
1
2
15
16
17
4
3
VDD33_UC
C32
10V
10µF
72
73
74
75
GND
VDD33_UC
R90
33k
GND
76
71
62
64
DP
DM
63
PUR
C33
2200pF
GND
61
14
68
19
49
GND
C35
16V
0.1uF
C36
10V
10µF
C37
16V
0.1uF
C38 MSP430F5529IPN
16V
0.1uF
GND
GND
Figure 29. USB2Any Schematic
SNLU241A – December 2018 – Revised April 2019
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EVM PCB Schematics
Copyright © 2018–2019, Texas Instruments Incorporated
35
Appendix B
SNLU241A – December 2018 – Revised April 2019
Board Layout
Figure 30. Top Overlay
36
Board Layout
SNLU241A – December 2018 – Revised April 2019
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Appendix B
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Figure 31. Top Solder
SNLU241A – December 2018 – Revised April 2019
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Board Layout
37
Appendix B
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Figure 32. Layer1 Top
38
Board Layout
SNLU241A – December 2018 – Revised April 2019
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Appendix B
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Figure 33. Layer 6 Bottom
SNLU241A – December 2018 – Revised April 2019
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Board Layout
39
Appendix B
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Figure 34. Layer6 Solder Bottom
40
Board Layout
SNLU241A – December 2018 – Revised April 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
Appendix B
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Figure 35. Layer6 Bottom Overlay
SNLU241A – December 2018 – Revised April 2019
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Board Layout
41
Appendix B
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Figure 36. Drill Drawing
42
Board Layout
SNLU241A – December 2018 – Revised April 2019
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Appendix B
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Figure 37. Board Dimensions
SNLU241A – December 2018 – Revised April 2019
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Board Layout
43
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2018) to A Revision ................................................................................................ Page
•
•
•
44
Changed Typical Connection and Test Equipment Images ........................................................................ 23
Changed Bill of Materials ............................................................................................................... 25
Changed schematics, layouts and board shots ...................................................................................... 29
Revision History
SNLU241A – December 2018 – Revised April 2019
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STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.
www.ti.com
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
www.ti.com
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
3
www.ti.com
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
www.ti.com
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
5
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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