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Texas Instruments TPD3S014-Q1 Evaluation Module User guides
User's Guide
SLVUAQ0 – April 2016
TPD3S014-Q1 Evaluation Module
This user's guide describes the characteristics, operation, and use of the TPD3S014-Q1 EVM evaluation
module (EVM). This EVM includes five TPD3S014-Q1s in various configurations for testing. One
TPD3S014-Q1 is configured for IEC61000-4-2 compliance testing, one is configured for 4-port sparameter analysis, one is pinned out for evaluating the current limiting switch, one is configured for
throughput on USB 2.0 Type A connectors for throughput analysis, and one is configured for the capture
of clamping waveforms during an ESD event. This user's guide includes setup instructions, schematic
diagrams, a bill of materials, and printed-circuit board layout drawings for the evaluation module.
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5
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Contents
Introduction ...................................................................................................................
Definitions .....................................................................................................................
Setup ..........................................................................................................................
3.1
U1 .....................................................................................................................
3.2
U2 .....................................................................................................................
3.3
U4 ....................................................................................................................
3.4
U3 .....................................................................................................................
Board Layout .................................................................................................................
Schematics ...................................................................................................................
Bill of Materials ...............................................................................................................
2
2
3
3
3
3
5
6
8
9
List of Figures
.........................
1
Ideal Contact Discharge Waveform of the Output Current of the ESD Simulator at 4 kV
2
System Level ESD Test Setup ............................................................................................. 4
3
3
TPD3S014-Q1EVM Top Layer ............................................................................................. 6
4
TPD3S014-Q1EVM Bottom Layer ......................................................................................... 7
5
TPD3S014-Q1EVM Schematic ............................................................................................ 8
List of Tables
.................................................................................................
1
IEC61000-4-2 Test Levels
2
Waveform Parameters in Contact Discharge Mode ..................................................................... 2
3
Bill of Materials ............................................................................................................... 9
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1
Introduction
1
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Introduction
Texas Instrument’s TPD3S014-Q1 evaluation module helps designers evaluate the operation and
performance of the TPD3S014-Q1 device. The TPD3S014-Q1 is a current limiting switch intended for
applications such as USB where heavy capacitive loads and short-circuits are likely to be encountered;
TPD3S014-Q1 provides short-circuit and over-current protection. This device has a fixed current-limit
threshold of 0.5 A. ESD protection for D+ and D– is also provided.
The EVM contains five TPD3S014-Q1s. TPD3S014-Q1 (U1) is configured with two USB2.0 Type A
connectors (USB1 and USB2) for capturing Eye Diagrams and evaluating current limiting with a system.
TPD3S014-Q1 (U2) is configured with 4 SMA (J1 – J4) connectors to allow 4-port analysis with a vector
network analyzer. TPD3S014-Q1 (U4) is configured with test points for striking ESD to the protection pins.
TPD3S014-Q1 (U3) is configured for capturing clamping waveforms with an oscilloscope during an ESD
test. Caution must be taken when capturing clamping waveforms during an ESD event so as not to
damage the oscilloscope. A proper procedure is outlined in Section 3.4.1.
2
Definitions
Contact Discharge — a method of testing in which the electrode of the ESD simulator is held in contact
with the device-under-test (DUT).
Air Discharge — a method of testing in which the charged electrode of the ESD simulator approaches
the DUT, and a spark to the DUT actuates the discharge.
ESD Simulator — a device that outputs IEC61000-4-2 compliance ESD waveforms shown in Figure 1
with adjustable ranges shown in Table 1 and Table 2.
IEC61000-4-2 has 4 classes of protection levels. Classes 1 – 4 are shown in Table 1. Stress tests
should be incrementally tested to level 4 as shown in Table 2 until the point of failure. If the DUT
does not fail at 8-kV, testing can continue in 2-kV increments until failure.
Table 1. IEC61000-4-2 Test Levels
Contact Discharge
Air Discharge
Class
Test Voltage [± kV]
Class
Test Voltage [± kV]
1
2
1
2
2
4
2
4
3
6
3
8
4
8
4
15
Table 2. Waveform Parameters in Contact Discharge Mode
2
Stress Level Step
Simulator Voltage
[kV]
Ipeak ±15% [A]
Rise Time ±25%
[nS]
Current at 30ns
±30% [A]
Current at 60ns
±30% [A]
1
2
7.5
0.8
4
2
2
4
15
0.8
8
4
3
6
22.5
0.8
12
6
4
8
30
0.8
16
8
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Setup
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Figure 1. Ideal Contact Discharge Waveform of the Output Current of the ESD Simulator at 4 kV
3
Setup
This section describes the intended use of the EVM. A generalized outline of the procedure given in IEC61000-4-2 is described here. IEC-61000-4-2 should be referred to for a more specific testing outline. Basic
configurations for collecting S-parameters, Eye Diagrams, and ESD clamping waveforms are outlined as
well. Attach 5 V to the +5-V test point and ground to GND. Tests can be performed will device enable pins
set HI or LO. For TPD3S014-Q1 the device is active-low, so set EN to LO to enable the devices on the
board.
3.1
U1
A single TPD3S014-Q1 (U1) is configured with two USB2.0 Type A connectors (USB1 & USB2) for
capturing Eye Diagrams. Using USB2 as input and USB1 as output, attach to a USB 2.0 compliant Eye
Diagram tester setup for the intended application, either transmitter or receiver.
3.2
U2
A TPD3S014-Q1 (U2) is configured with 4 SMA (J1 – J4) connectors to allow 4-port analysis with a vector
network analyzer. Connect Port 1 to J1, Port 2 to J2, Port 3 to J3, and Port 4 to J4. This configuration
allows for the following terminology in 4 port analysis:
• S11: Return loss
• S21: Insertion loss
• S31: Near end cross talk
• S41: Far end cross talk
3.3
U4
A TPD3S014-Q1 (U3) has an SMB connector (J7) for capturing clamping waveforms with an oscilloscope
during an ESD strike. Caution must be taken when capturing clamping waveforms during an ESD event so
as not to damage the oscilloscope.
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Setup
3.3.1
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Test Method and Set-Up
An example test setup is shown in Figure 2. Details of the testing table and ground planes can be found in
the IEC 61000-4-2 test procedure. Ground the EVM using the banana connector labeled GND (J9).
Discharge the ESD simulator on any of the Test Points TP1 – TP10. Contact and air-gap discharge are
tested using the same simulator with the same discharge waveform. While the simulator is in direct
contact with the test point during contact, it is not during air-gap.
ESD Simulator
DUT or System
Typical Position for
Direct Discharge
Power and Ground Connection
Horizontal Coupling
Plane (HCP)
To Wall
Ground
470 kO
470 kO
Ground Reference Plane
Non-conducting Table
Figure 2. System Level ESD Test Setup
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Setup
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3.3.2
Evaluation of Test Results
Connect the tested device on the EVM to a curve tracer both before and after ESD testing. After each
incremental level, if the IV curve of the ESD protection diode shifts ±0.1 V, or leakage current increases by
a factor of ten, then the device is permanently damaged by ESD.
3.4
U3
A TPD3S014-Q1 (U3) has an SMB connector (J7) for capturing clamping waveforms with an oscilloscope
during an ESD strike. Caution must be taken when capturing clamping waveforms during an ESD event so
as not to damage the oscilloscope.
3.4.1
Oscilloscope Setup
Without a proper procedure, capturing ESD clamping waveforms exposes the oscilloscope to potential
voltages higher than the rating of the equipment. Proper methodology can mitigate any risk in this
operation.
Recommended Equipment:
• Minimum of 1 GHz bandwidth oscilloscope.
• Either of the following:
– 2 10X 50 Ω attenuators and a 0 Ω resistor (to be installed at R1).
– 1 10X 50 Ω attenuator and a 150 Ω resistor (already installed at R1).
• 50 Ω shielded SMB cable.
Procedure
In order to protect the oscilloscope, attenuation of the measured signal is required. Here are two possible
procedures for testing U3:
1. Using two 10X attenuators:
• Install a 0 Ω resistor in R1
• Attach two 10X attenuators to the oscilloscope channel being used.
• Attach the 50 Ω shielded SMB cable between J7 and the attenuator.
• Set the scope attenuation factor to 100X.
• Set the oscilloscope to trigger on a positive edge for (+) ESD and a negative edge for (–) ESD
strikes. The magnitude should be set to 20 V.
• Following Section 3.3.1, strike contact ESD to TP10.
2. Using one 10X attenuator:
• Attach one 10X attenuator to the oscilloscope.
• Attach the 50 Ω shielded SMB cable between J7 and the attenuator.
• Set the scope attenuation factor to 40X.
• Set the oscilloscope to trigger on a positive edge for (+) ESD and a negative edge for (–) ESD
strikes. The magnitude should be set to 20 V.
• Following Section 3.3.1, strike contact ESD to TP10.
Recommended settings for the time axis is 20 ns/div and for the voltage axis is 10 V division.
The voltage levels of the ESD applied to TP10 should not exceed ±8kV while capturing clamping
waveforms.
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Board Layout
4
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Board Layout
This section provides the TPD3S014-Q1EVM board layout. TPD3S014-Q1EVM is a 4-layer board of FR-4
at 0.062 inch thickness. Layers 2 and 3 are ground and power planes, respectively, and not shown.
Figure 3. TPD3S014-Q1EVM Top Layer
6
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Board Layout
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Figure 4. TPD3S014-Q1EVM Bottom Layer
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Schematics
5
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Schematics
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Figure 5. TPD3S014-Q1EVM Schematic
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Bill of Materials
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Bill of Materials
Table 3. Bill of Materials
Count
RefDes
Description
Package
Reference
Part Number
MFR
1
+5V
Test Point, Miniature, Red,
TH
Red Miniature
Test point
5000
Keystone
5
C1, C4, C6, C8,
C10
CAP, TA, 150uF, 6.3V, +/10%, 0.15 ohm, SMD
6032-28
TPSC157K006R0150
AVX
1206
GMK316F106ZL-T
Taiyo Yuden
5
C2, C3, C5, C7, C9 CAP, CERM, 10 uF, 50V, +/10%, X7R, 1206
2
EN_ALL, EN_U5
Header, Male 3-pin, 100mil
spacing,
0.100 inch x 3
PEC03SAAN
Sullins
3
GND, J5, J6
Standard Banana Jack,
Uninsulated, 5.5mm
Keystone 575-4
575-4
Keystone
4
H1, H2, H3, H4
Machine Screw, Round, #440 x 1/4, Nylon, Philips
panhead
Screw
NY PMS 440 0025 PH
B&F Fastener Supply
4
H5, H6, H7, H8
Standoff, Hex, 0.5"L #4-40
Nylon
Standoff
1902C
Keystone
4
J1, J2, J3, J4
Connector, TH, SMA
SMA
142-0701-231
Emerson Network
Power
1
J7
Connector, SMB, Vertical
RCP 0-4GHz, 50 ohm, TH
SMB
131-3701-261
Emerson Network
Power
1
R1
RES, 150 ohm, 1%, 0.1W,
0603
603
CRCW0603150RFKEA
Vishay-Dale
5
U1, U2, U3, U4, U5
IC, Low-Capacitance 4Chan ±15-kV ESDProtection Array For HighSeed Data Interfaces
SOT-23
TPD3S014-Q1DBV
TI
1
USB1
Connector, Receptacle, USB
TYPE A, 4POS SMD
USB Type A
connector,
receptacle, 4
POS SMD
896-43-004-00-000000
Mill-Max
1
USB2
Connector, USB Type A,
4POS R/A, SMD
USB Type A right
angle
48037-1000
Molex
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