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Texas Instruments DS90Ux947-Q1EVM Evaluation Board (Rev. A) User guides
DS90Ux947-Q1EVM User's Guide
User's Guide
Literature Number: SNLU140A
November 2014 – Revised August 2015
Contents
1
DS90Ux947-Q1EVM User's Guide ........................................................................................... 5
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
General Description ......................................................................................................... 5
Features ....................................................................................................................... 5
System Requirements ....................................................................................................... 6
Contents of the Demo Evaluation Kit ..................................................................................... 6
Applications Diagram ........................................................................................................ 6
Typical Configuration ........................................................................................................ 7
Quick Start Guide ............................................................................................................ 8
Default Jumper Settings ................................................................................................... 10
Default Switch Settings .................................................................................................... 10
Demo Board Connections ................................................................................................. 11
ALP Software Setup ....................................................................................................... 15
1.11.1 System Requirements ........................................................................................... 15
1.11.2 Download Contents .............................................................................................. 15
1.11.3 Installation of the ALP Software ................................................................................ 15
1.11.4 Installation of the Device Profiles .............................................................................. 15
1.11.5 Startup - Software Description.................................................................................. 15
1.11.6 Information Tab ................................................................................................... 17
1.11.7 Pattern Generator Tab........................................................................................... 18
1.11.8 Registers Tab ..................................................................................................... 19
1.11.9 Registers Tab - Address 0x00 selected ....................................................................... 20
1.11.10 Registers Tab - Address 0x00 expanded .................................................................... 21
1.11.11 Scripting Tab .................................................................................................... 22
Troubleshooting ALP Software ........................................................................................... 23
1.12.1 ALP Loads the Incorrect Profile ................................................................................ 23
1.12.2 ALP does not detect the EVM .................................................................................. 25
Typical Connection and Test Equipment ................................................................................ 27
Equipment References .................................................................................................... 28
Cable References .......................................................................................................... 28
2
Bill of Materials .................................................................................................................. 29
A
EVM PCB Schematics ......................................................................................................... 35
B
Board Layout ..................................................................................................................... 45
Revision History .......................................................................................................................... 54
2
Contents
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List of Figures
1-1.
Applications Diagram ........................................................................................................ 6
1-2.
Typical Configuration ........................................................................................................ 7
1-3.
Interfacing to the EVM
1-4.
Launching ALP
1-5.
1-6.
1-7.
1-8.
1-9.
1-10.
1-11.
1-12.
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
1-19.
1-20.
1-21.
1-22.
...................................................................................................... 9
............................................................................................................. 16
Initial ALP Screen .......................................................................................................... 16
Follow-up Screen ........................................................................................................... 17
ALP Information Tab ....................................................................................................... 17
ALP Pattern Generator Tab ............................................................................................... 18
ALP Registers Tab ......................................................................................................... 19
ALP Device ID Selected ................................................................................................... 20
ALP Device ID Expanded ................................................................................................. 21
ALP Scripting Tab .......................................................................................................... 22
USB2ANY Setup ........................................................................................................... 23
Remove Incorrect Profile .................................................................................................. 23
Add Correct Profile ......................................................................................................... 24
Finish Setup ................................................................................................................. 24
ALP No Devices Error ..................................................................................................... 25
Windows 7, ALP USB Driver ............................................................................................. 25
ALP in Demo Mode ........................................................................................................ 26
ALP Preferences Menu .................................................................................................... 26
Typical Test Setup for Video Application ................................................................................ 27
Typical Test Setup for Evaluation ........................................................................................ 27
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List of Figures
3
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List of Tables
1-1.
Default Board Jumper Settings ........................................................................................... 10
1-2.
Default Board Switch Settings ............................................................................................ 10
1-3.
Power Supply ............................................................................................................... 11
1-4.
FPD-Link III Output Signals P1 ........................................................................................... 11
1-5.
Alternative FPD-Link III Output Signals
1-6.
1-7.
1-8.
1-9.
1-10.
1-11.
1-12.
1-13.
1-14.
2-1.
4
.................................................................................
OpenLDI Input Signals.....................................................................................................
USB2ANY Connector ......................................................................................................
I2C/CCI Interface Header J20 ............................................................................................
GPIO/Audio Interface ......................................................................................................
SPI/D_GPIO Interface .....................................................................................................
MODE_SEL[1:0] Settings .................................................................................................
Configuration Select (MODE_SEL0) - SW-DIP8 - S2 .................................................................
Configuration Select (MODE_SEL1) - SW-DIP8 - S6 .................................................................
IDx SW-DIP8 - S3 .........................................................................................................
Bill of Materials .............................................................................................................
List of Tables
11
11
12
12
12
12
12
13
13
13
29
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Chapter 1
SNLU140A – November 2014 – Revised August 2015
DS90Ux947-Q1EVM User's Guide
1.1
General Description
The DS90Ux947-Q1EVM (Evaluation Module) converts OpenLDI to FPD-Link III. This kit will demonstrate
the functionality and operation of the DS90Ux947-Q1. The DS90Ux947-Q1 is an OpenLDI to FPD-Link III
Serializer which, in conjunction with the DS90Ux940-Q1/DS90Ux948-Q1 Deserializers, takes the data
from OpenLDI serial stream and translates it into either single- or dual-lane FPD-Link III interface. The
DS90Ux947-Q1 supports video resolutions up to WUXGA and 1080p60 with 24-bit color depth.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including
I2C and SPI communication, over the same differential link. In backward compatible mode, the device
supports up to WXGA and 720p resolutions with 24-bit color depth over a single differential link.
The device supports up to 7.1 audio channels. Audio data received from external I2S is encrypted,
serialized, and sent out on the FPD-Link III stream to a compatible deserializer. Up to 8-channel I2S
interface with maximum bit rate of 192 kHz.
The demo board is not intended for EMI testing. The demo board was designed for easy accessibility to
device pins with tap points for monitoring or applying signals, additional pads for termination, and multiple
connector options.
1.2
Features
•
•
•
•
•
•
•
•
•
•
•
Supports Pixel Clock Frequency up to 170 MHz for WUXGA (1920x1200) and 1080p60 resolutions
with 24-bit Color Depth
OpenLDI Receiver to accept OpenLDI as input
Dual FPD-Link III output interface
– Single Channel: Up to 96 MHz Pixel Clock
– Dual Channel: Up to 170 MHz Pixel Clock
Up to 15 meters over Single-Ended Coaxial or Differential Shielded Twisted-Pair (STP) cable
Backwards Compatible with DS90Ux926Q-Q1 and DS90Ux928Q-Q1 FPD-Link III Deserializers
@Speed BIST
Supports 7.1 multiple I2S (4 data) channels
Single +12V power supply for EVM
1.8V LVCMOS I/O interface
1.8V or 3.3V compatible LVCMOS I2C interface
Automotive grade product: AEC-Q100 Grade 2 qualified
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System Requirements
1.3
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System Requirements
In order to demonstrate, the following is required:
1. FPD-Link III compatible Deserializer
(a) DS90Ux940-Q1, DS90Ux948-Q1 up to 1080p60
(b) DS90Ux926Q-Q1, DS90Ux928Q-Q1 up to 720p60
2. OpenLDI source
3. Optional I2C controller
4. Power supply for 12V @ 1A (required)
1.4
Contents of the Demo Evaluation Kit
1. One EVM board with the DS90Ux947-Q1
1.5
Applications Diagram
FPD-Link
(OpenLDI)
VDDIO
1.8V
1.8V
1.2V
1.1V
3.3V
VDDIO
1.8V or 3.3V
FPD-Link III
2 lanes @3Gbps / per
Lane
FPD-Link
(OpenLDI)
CLK+/-
CLK+/DOUT0+
RIN0+
DOUT0-
RIN0-
D0+/-
D0+/D1+/-
D1+/-
Graphics
Processor
D2+/D3+/-
DOUT1+
RIN1+
DOUT1-
RIN1-
DS90Ux947-Q1
Serializer
D2+/D3+/-
DS90Ux948-Q1
Deserializer
D4+/-
CLK2+/-
LVDS
Display
1080p60
or Graphic
Processor
D4+/D5+/D5+/D6+/-
I2C
IDx
D7+/-
D_GPIO
(SPI)
I2C
IDx
D6+/-
D_GPIO
(SPI)
D7+/-
HDCP ± High-Bandwidth Digital Content Protection
Figure 1-1. Applications Diagram
6
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Typical Configuration
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1.6
Typical Configuration
Video Processor Board
(Video Data + Ctrl + PCLK)
DS90Ux947
Video
Processor
(I2C)
Dual FPD-LINK III
Cluster, Head Unit
FPD-Link III
Deserializer
(OpenLDI )
Display
(I2C)
Figure 1-2. Typical Configuration
Figure 1-1 and Figure 1-2 illustrate the use of the chipset in a display application.
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Quick Start Guide
1.7
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Quick Start Guide
1. Configure switches S2, S3, and S6 to set device’s operating modes
• S2: MODE_SEL0 = 1 (default factory setting)
• S3: IDx = 0x18 (default factory setting)
• S6: MODE_SEL1 = 1 (default factory setting)
2. Connect P1 (DOUT[1:0]+/-) to compatible Deserializer e.g. DS90Ux940-Q1/DS90Ux948-Q1 using STP
cable (default)
3. Connect J36 to 12V.
(a) Optional power options available (see Table 1-3)
4. Plug in OpenLDI source
5. Connect J29 with miniUSB (5-pin_ to USB A (4-pin) cable to PC USB port
For details of pin-names and pin-functions, please refer to the DS90Ux947Q datasheet.
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(5)
Connect to PC for I2C
register access
(3)
APPLY
12V
HERE
IDx
ODD
MODE_SEL0
(1)
MODE_SEL
&
IDx
Settings
(4)
Apply OLDI
Inputs
(2)
EVEN
MODE_SEL1
SV601153
Figure 1-3. Interfacing to the EVM
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Default Jumper Settings
1.8
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Default Jumper Settings
Ensure that the board has the default board jumper settings:
Table 1-1. Default Board Jumper Settings
1.9
Jumper
Jumper Settings
J48
Connect 1 and 2
J16
Connect 1 and 2
J46
Connect 1 and 2
J41
Connect 2 and 3
J33
Connect 1 and 2
J4
Connect 2 and 3
J49
Connect 1 and 2
J37
Connect 1 and 2
J26
Connect 1 and 2
J60
Connect 1 and 2
J40
Connect 2 and 3
J18
Connect 2 and 3
J14
Connect 2 and 3
J19
Connect 2 and 3
Default Switch Settings
Ensure that the board has the default board switch settings:
Table 1-2. Default Board Switch Settings
Switch
10
Switch Settings
S1
1 to 3 ON
S2
1 ON, 2-8 OFF
S3
1 ON, 2-8 OFF
S5
1 ON, 2-8 OFF
S6
1-2 OFF, 3-4 ON
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Demo Board Connections
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1.10 Demo Board Connections
Table 1-3. Power Supply
Designator
Signal
Description
J36
+12V
12V ±5% Main Power
Single +12V power connector that supplies power to the entire board.
J26.2 (Optional)
+1.1V
1.1V ±5%
Alternative to Main Power. If used, remove jumper on J26.
J39.1 (Optional)
+1.8V
1.8V ±5%
Alternative to Main Power. If used, remove R204.
J42.1 (Optional)
+3.3V
3.3V ±5%
Alternative to Main Power. If used, remove R207.
J33.2 (Optional)
+5V
5V ±5%
Alternative to Main Power. If used, remove jumper on J41.
Table 1-4. FPD-Link III Output Signals P1
Designator
Port
P1.1
Signal
DOUT0-
FPD-Link III Port 0
P1.3
P1.2
DOUT0+
DOUT1-
FPD-Link III Port 1
P1.4
DOUT1+
Table 1-5. Alternative FPD-Link III Output Signals
Designator
Port
J11
Signal
DOUT0-
FPD-Link III Port 0
J9
J13
DOUT0+
DOUT1-
FPD-Link III Port 1
J12
DOUT1+
Table 1-6. OpenLDI Input Signals
Designator
Signal
Description
J10.2
J10.3
D0D0+
OpenLDI D0 input
J10.6
J10.7
D1D1+
OpenLDI D1 input
J10.10
J10.11
D2D2+
OpenLDI D2 input
J10.14
J10.15
CLKCLK+
OpenLDI CLK input
J10.18
J10.19
D3D3+
OpenLDI D3 input
J43.2
J43.3
D4D4+
OpenLDI D4 input
J43.6
J43.7
D5D5+
OpenLDI D5 input
J43.10
J43.11
D6D6+
OpenLDI D6 input
J43.18
J43.19
D7D7+
OpenLDI D7 input
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Table 1-7. USB2ANY Connector
Designator
Description
J29
mini USB 5 pin
Table 1-8. I2C/CCI Interface Header J20
Designator
Signal
J20.1
VDDI2C
J20.2
SCL
J20.3
SDA
J20.4
GND
Table 1-9. GPIO/Audio Interface
Designator
Signal
J21.18
GPIO0
Remote or Local I/O
Description
J21.20
GPIO1
Remote or Local I/O
J21.2
I2S_DC/GPIO2
I2S Data Input / Remote or Local I/O
J21.4
I2S_DD/GPIO3
I2S Data Input / Remote or Local I/O
J21.6
VDDIO
J21.8
I2S_DB/GPIO5_RE
G
GPIO Voltage Level 1.8V
I2S Data Input / Local only I/O
J21.10
I2S_DA/GPIO6_RE
G
I2S Data Input / Local only I/O
J21.12
I2S_WC/GPIO7_RE
I2S Word Clock Input / Local only I/O
G
J21.14
I2S_CLK/GPIO8_RE
I2S Clock Input / Local only I/O
G
Table 1-10. SPI/D_GPIO Interface
Designator
Signal
J21.6
VDDIO
Description
GPIO Voltage Level 1.8V
J21.32
D_GPIO3/SS
I/O in Dual FPD-Link III mode / Slave Select
J21.30
D_GPIO2/SCLK
I/O in Dual FPD-Link III mode / Serial Clock
J21.28
D_GPIO1/MISO
I/O in Dual FPD-Link III mode / Master In, Slave Out
J21.26
D_GPIO0/MOSI
I/O in Dual FPD-Link III mode / Master Out, Slave In
Configuration of the device may be done via the MODE_SEL[1:0]. These modes are latched into register
location during power-up:
Table 1-11. MODE_SEL[1:0] Settings
Mode
Setting
OLDI_DUAL: OpenLDI
Interface
0
Single-pixel OpenLDI interface.
1
Dual-pixel OpenLDI interface.
0
Disable.
1
Enable.
REPEATER: Configure
Repeater
0
Disable repeater mode.
1
Enable repeater mode.
MAPSEL: OpenLDI Bit
Mapping
0
OpenLDI bit mapping.
1
SPWG bit mapping.
AUTO_SS: Auto Sleep-State
12
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Table 1-11. MODE_SEL[1:0] Settings (continued)
Mode
Setting
COAX: Cable Type
Function
0
Enable FPD-Link III for twisted pair cabling.
1
Enable FPD-Link III for coaxial cabling.
Table 1-12. Configuration Select (MODE_SEL0) - SW-DIP8 - S2 (1)
#
Ratio
VR4/VDD18
Target VR4
(V)
Suggested
Resistor PullUp R3 kΩ (1%
tol)
Suggested
Resistor PullDown R4 kΩ
(1% tol)
OLDI_DUAL
AUTO_SS
REPEATER
1
0
0
OPEN
40.2
0
0
0
2
0.213
0.383
115
30.9
0
0
1
3
0.328
0.591
107
52.3
0
1
0
4
0.444
0.799
113
90.9
0
1
1
5
0.560
1.008
82.5
105
1
0
0
6
0.676
1.216
51.1
107
1
0
1
7
0.792
1.425
30.9
118
1
1
0
8
1
1.8
40.2
OPEN
1
1
1
(1)
Only set one high
Table 1-13. Configuration Select (MODE_SEL1) - SW-DIP8 - S6 (1)
#
(1)
Ratio
VR6/VDD18
Target VR6
(V)
Suggested
Resistor Pull-Up
R5 kΩ (1% tol)
Suggested
Resistor PullDown R6 kΩ (1%
tol)
MAPSEL
COAX
1
0
0
OPEN
40.2
0
0
2
0.213
0.383
115
30.9
0
0
3
0.328
0.591
107
52.3
0
1
4
0.444
0.799
113
90.9
0
1
5
0.560
1.008
82.5
105
1
0
6
0.676
1.216
51.1
107
1
0
7
0.792
1.425
30.9
118
1
1
8
1
1.8
40.2
OPEN
1
1
Only set one high
The strapped values can be viewed and/or modified in the following locations:
• OLDI_DUAL : Latched into OLDI_IN_MODE (0x4F[6], inverted from strap value).
• AUTO_SS : Latched into SOFT_SLEEP (0x01[7]).
• REPEATER : Latched into TX_RPTR (0xC2[5]).
• MAPSEL : Latched into OLDI_MAPSEL (0x4F[7]).
• COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).
Table 1-14. IDx SW-DIP8 - S3 (1)
(1)
Designator
7-Bit Address
S1.1 (Default)
0x0C
8-Bit Address
0x18
S1.2
0x0E
0x1C
S1.3
0x10
0x20
S1.4
0x12
0x24
S1.5
0x14
0x28
Only set one high.
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Table 1-14. IDx SW-DIP8 - S3 (1) (continued)
14
Designator
7-Bit Address
8-Bit Address
S1.6
0x16
0x2C
S1.7
0x18
0x30
S1.8
0x1A
0x34
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ALP Software Setup
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1.11 ALP Software Setup
1.11.1 System Requirements
Operating System:
USB:
USB2ANY Firmware Version:
Windows 7 64-bit
USB2ANY
2.5.2.0
1.11.2 Download Contents
TI Analog LaunchPAD can be downloaded from: http://www.ti.com/tool/alp.
Download and extract the “snlc048.zip” file to a temporary location that can be deleted later.
Make sure J29 on the DS90Ux947 is connected to a PC USB port with USB cable and power is applied to
the DS90Ux947 EVM.
The following installation instructions are for the Windows 7 64-bit Operating System.
1.11.3 Installation of the ALP Software
Execute the ALP Setup Wizard program called “ALPF_setup_v_x_x_x.exe” that was extracted to a
temporary location on the local drive of your PC.
There are 7 steps to the installation once the setup wizard is started:
1. Select the "Next" button.
2. Select “I accept the agreement” and then select the “Next” button.
3. Select the location to install the ALP software and then select the “Next” button.
4. Select the location for the start menu shortcut and then select the “Next” button.
5. There will then be a screen that allows the creation of a desktop icon. After selecting the desired
choices select the “Next” button.
6. Select the “Install” button, and the software will then be installed to the selected location.
7. Uncheck “Launch Analog LaunchPAD” and select the “Finish” button. The ALP software will start if
“Launch Analog LaunchPAD” is checked, but it will not be useful until the USB driver is installed and
board is attached.
Connect J29 USB jack of the DS90Ux947Q EVM board to a PC/laptop USB port using a Type A
1
2
3
4
A to mini-B
1 2 3
4
MINI
USB cable. Power the DS90Ux947Q EVB board with a 12 VDC
power supply. The “Found New Hardware Wizard” will open on the PC/laptop.
1.11.4 Installation of the Device Profiles
There are 2 steps to add the DS90Ux947 profile:
1. Contact TI for the DS90Ux947 profile
2. Extract the “DS90Ux947.zip” to ALP’s profile folder. The profile folder can be found at: C:\Program
Files (x64)\Texas Instruments\Analog LaunchPAD vx.x.x\Profiles\
1.11.5 Startup - Software Description
Make sure all the software has been installed and the hardware is powered on and connected to the PC.
Execute “Analog LaunchPAD” shortcut from the start menu. The default start menu location is under All
Programs > Texas Instruments > Analog LaunchPAD vx.x.x > Analog LaunchPAD to start MainGUI.exe.
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ALP Software Setup
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Figure 1-4. Launching ALP
The application should come up in the state shown in the figure below. If it does not, see Section 1.12,
“Troubleshooting ALP Software”.
Under the Devices tab click on “DS90Ux947” to select the device and open up the device profile and its
associated tabs.
Figure 1-5. Initial ALP Screen
After selecting the DS90Ux947, the following screen should appear.
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Figure 1-6. Follow-up Screen
1.11.6 Information Tab
The Information tab is shown below. Please note the device revision could be different.
Figure 1-7. ALP Information Tab
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1.11.7 Pattern Generator Tab
The SER Pattern Generator tab is shown below.
Figure 1-8. ALP Pattern Generator Tab
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1.11.8 Registers Tab
The Register tab is shown below.
Figure 1-9. ALP Registers Tab
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1.11.9 Registers Tab - Address 0x00 selected
Address 0x00 selected as shown below. Note that the “Value:” box,
value of that register.
, will now show the hex
Figure 1-10. ALP Device ID Selected
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1.11.10 Registers Tab - Address 0x00 expanded
By double clicking on the Address bar
or a single click on
can be expanded.
. Address 0x00 expanded reveals contents by bits. Any register address displayed
Figure 1-11. ALP Device ID Expanded
Any RW Type register,
, can be written into by writing the hex value into the “Value:” box,
or putting the pointer into the individual register bit(s) box by a left mouse click to put a check mark
(indicating a “1”) or unchecking to remove the check mark (indicating a “0”). Click the “Apply” button to
write to the register, and “refresh” to see the new value of the selected (highlighted) register.
The box toggles on every mouse click.
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ALP Software Setup
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1.11.11 Scripting Tab
The Scripting tab is shown below.
Figure 1-12. ALP Scripting Tab
The script window provides a full Python scripting environment which can be for running scripts and
interacting with the device in an interactive or automated fashion.
WARNING
Directly interacting with devices either through register
modifications or calling device support library functions can effect
the performance and/or functionality of the user interface and may
even crash the ALP Framework application.
22
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Troubleshooting ALP Software
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1.12 Troubleshooting ALP Software
1.12.1 ALP Loads the Incorrect Profile
If ALP opens with the incorrect profile loaded the correct profile can be loaded from the
USB2ANY/Aardvark Setup found under the tools menu.
Figure 1-13. USB2ANY Setup
Highlight the incorrect profile in the Defined ALP Devices list and press the remove button.
Figure 1-14. Remove Incorrect Profile
Find the correct profile under the Select a Daughter Board list, highlight the profile and press Add.
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Troubleshooting ALP Software
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Figure 1-15. Add Correct Profile
Select Ok and the correct profile should now be loaded.
Figure 1-16. Finish Setup
24
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1.12.2 ALP does not detect the EVM
If the following window opens after starting the ALP software, double check the hardware setup.
Figure 1-17. ALP No Devices Error
It may also be that the USB driver is not installed. Check the device manager. There should be a “HIDcompliant device” under the “Human Interface Devices” as shown below.
Figure 1-18. Windows 7, ALP USB Driver
The software should start with only “DS90Ux947” in the “Devices” pull down menu. If there are more
devices then the software is most likely in demo mode. When the ALP is operating in demo mode there is
a “(Demo Mode)” indication in the lower left of the application status bar as shown below.
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Troubleshooting ALP Software
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Figure 1-19. ALP in Demo Mode
Disable the demo mode by selecting the “Preferences” pull down menu and un-checking “Enable Demo
Mode”.
Figure 1-20. ALP Preferences Menu
After demo mode is disabled, the ALP software will poll the ALP hardware. The ALP software will update
and have only “DS90Ux947” under the “Devices” pull down menu.
26
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Typical Connection and Test Equipment
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1.13 Typical Connection and Test Equipment
The following is a list of typical test equipment that may be used to generate signals for the Serializer
inputs:
1. Digital Video Source – for generation of specific display timing such as Digital Video Processor or
Graphics Controller (GPU) with OpenLDI output.
2. Any other signal generator / video source - This video generator may be used for video signal sources
for DVI or DP++
3. Any other signal / video generator that provides the correct input levels as specified in the datasheet.
The picture below shows a typical test set up using a Graphics Controller and display.
DS90Ux947
EVM Board
Deserializer
Board
Display
OpenLDI
LVDS
OpenLDI
Generator
FPD-Link III
Contents of Demo Kit
Graphics Controller /
Video Processor Board
Figure 1-21. Typical Test Setup for Video Application
The picture below shows a typical test set up using a video generator and logic analyzer.
DS90Ux947
EVM Board
DIGITAL
VIDEO
GENERATOR
DIGITAL VIDEO GENERATOR
Deserializer
Board
OpenLDI
OpenLDI LVDS
FPD-Link III
Digital Video Source
Logic Analyzer / Oscilloscope
Contents of Demo Kit
Figure 1-22. Typical Test Setup for Evaluation
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Equipment References
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1.14 Equipment References
NOTE: Please note that the following references are supplied only as a courtesy to our valued
customers. It is not intended to be an endorsement of any particular equipment or supplier.
Digital Video Pattern Generator:
Astrodesign
www.astro-americas.com
Logic Analyzer:
Keysight
www.keysight.com
Corelis CAS-1000-I2C/E I2C Bus Analyzer and Exerciser Products:
www.corelis.com/products/I2C-Analyzer.htm
Aardvark I2C/SPI Host Adapter Part Number: TP240141
www.totalphase.com/products/aardvark_i2cspi
1.15 Cable References
For optimal performance, we recommend Shielded Twisted Pair (STP) 100ohm differential impedance and
24 AWG (or larger diameter) cable for high-speed data applications.
Leoni Dacar 538 series cable:
www.leoni-automotive-cables.com
Rosenberger HSD connector:
www.rosenberger.de/en/Products/35_Automotive_HSD.php
28
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Chapter 2
SNLU140A – November 2014 – Revised August 2015
Bill of Materials
Table 2-1. Bill of Materials
ITEM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QUANTI
TY
1
!PCB1
Printed Circuit Board
Any
SV601153
1
2
C1, C2, C3, C4, C6, C15,
C25, C32, C39, C56
CAP, CERM, 10 µF, 25 V, +/- 10%, Samsung
X5R, 0805
CL21A106KAFN3NE
10
3
C5, C21, C29, C43, C45,
C47, C50, C51, C83,
C106, C116, C123, C133,
C137
CAP, CERM, 10uF, 10V, +/-10%,
X7R, 0805
MuRata
GRM21BR71A106KE51L
14
4
C7, C14, C23, C46, C54,
CAP, CERM, 0.1uF, 16V, +/-10%,
C55, C69, C70, C71, C81, X7R, 0402
C82, C84, C86, C96, C97,
C98, C104, C105, C107,
C108, C110, C111, C113,
C117, C121, C122, C126,
C129, C131, C132, C135,
C136
MuRata
GRM155R71C104KA88D
32
5
C8, C24
CAP, TA, 1uF, 16V, +/-10%, 9.3
ohm, SMD
Vishay-Sprague
293D105X9016A2TE3
2
6
C9, C124
CAP, TA, 22uF, 25V, +/-20%, 0.7
ohm, SMD
Vishay-Sprague
293D226X0025D2TE3
2
7
C10, C127, C130, C134
CAP, CERM, 4.7uF, 16V, +/-10%,
X7R, 0805
MuRata
GRM21BR71C475KA73L
4
8
C11, C13, C20, C31,
C128
CAP, CERM, 0.01uF, 100V, +/-5%, AVX
X7R, 0603
06031C103JAT2A
5
9
C12
CAP, CERM, 0.1uF, 25V, +/-5%,
X7R, 0603
C0603C104J3RAC
1
10
C16,
C33,
C57,
C77,
GCM155R71H103KA55D
17
11
C19, C28, C35, C36, C44, CAP, CERM, 0.1uF, 50V, +/-10%,
C60
X7R, 0402
TDK
CGA2B3X7R1H104K050BB 6
12
C22, C30, C37, C38, C48, CAP, CERM, 1 µF, 35 V, +/- 10%,
C63, C120
JB, 0402
TDK
C1005JB1V105K050BC
7
13
C49
CAP, CERM, 150pF, 50V, +/-5%,
C0G/NP0, 0402
MuRata
GRM1555C1H151JA01D
1
14
C52, C61, C119
CAP, CERM, 1uF, 16V, +/-10%,
X7R, 0603
TDK
C1608X7R1C105K
3
15
C53, C112
CAP, CERM, 10pF, 50V, +/-5%,
C0G/NP0, 0402
MuRata
GRM1555C1H100JA01D
2
16
C62
CAP, TA, 22uF, 20V, +/-20%, 0.7
ohm, SMD
Vishay-Sprague
293D226X0020D2TE3
1
17
C64
CAP, CERM, 1uF, 6.3V, +/-20%,
X5R, 0402
TDK
C1005X5R0J105M
1
18
C65
CAP, TA, 2.2uF, 25V, +/-10%, 3.8
ohm, SMD
Vishay-Sprague
293D225X9025B2TE3
1
19
C66
CAP, CERM, 0.01uF, 100V, +/10%, X7R, 0805
AVX
08051C103KAT2A
1
Kemet
C17, C18, C26, C27, CAP, CERM, 0.01uF, 50V, +/-10%, MuRata
C34, C40, C41, C42, C0G/NP0, 0402
C58, C59, C67, C68,
C80
SNLU140A – November 2014 – Revised August 2015
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Bill of Materials
29
Cable References
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Table 2-1. Bill of Materials (continued)
ITEM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QUANTI
TY
20
C73, C74, C76, C78
CAP, CERM, 0.1 µF, 50 V, +/10%, C0G/NP0, 0402
TDK
C1005X7R1H104K
4
21
C87, C88
CAP, CERM, 4.7pF, 25V, +/-5%,
C0G/NP0, 0402
MuRata
GRM1555C1E4R7CA01D
2
22
C99, C103
CAP, CERM, 220pF, 50V, +/-1%,
C0G/NP0, 0603
AVX
06035A221FAT2A
2
23
C100, C101
CAP, CERM, 20 pF, 100 V, +/- 5%, MuRata
C0G/NP0, 0603
GRM1885C2A200JA01D
2
24
C102
CAP, CERM, 2200pF, 50V, +/10%, X7R, 0603
C0603X222K5RACTU
1
25
C109
CAP, CERM, 0.47uF, 16V, +/-10%, MuRata
X7R, 0603
GRM188R71C474KA88D
1
26
C114
CAP, TA, 100uF, 16V, +/-20%, 0.1
ohm, SMD
Kemet
T495D107M016ATE100
1
27
C115
CAP, CERM, 47uF, 16V, +/-20%,
X5R, 1210
MuRata
GRM32ER61C476ME15L
1
28
C118
CAP, CERM, 3300pF, 50V, +/10%, X7R, 0402
MuRata
GRM155R71H332KA01D
1
29
C125
CAP, TA, 2.2uF, 25V, +/-10%, 6.3
ohm, SMD
Vishay-Sprague
293D225X9025A2TE3
1
30
D1, D6, D7, D9, D10
LED, Green, SMD
Wurth Elektronik eiSos
150060VS75000
5
31
D3
LED, Orange, SMD
Lite-On
LTST-C190KFKT
1
32
D4
LED, Green, SMD
Lite-On
LTST-C190GKT
1
33
D8
Diode, Schottky, 40V, 1A, SOD123
Diodes Inc.
1N5819HW-7-F
1
34
D11
Diode, Zener, 7.5V, 550mW, SMB
ON Semiconductor
1SMB5922BT3G
1
35
F1
Fuse, 7 A, 24 V, SMD
Littelfuse
0429007.WRML
1
36
FID1, FID2, FID3
Fiducial mark. There is nothing to
buy or mount.
N/A
N/A
3
37
H1, H2, H5, H6, H9, H11
Standoff, Hex, 0.5"L #4-40 Nylon
Keystone
1902C
6
38
J1
Connector, Audio Jack, 3.5mm,
Stereo, SMD
CUI Inc.
SJ-3523-SMT
1
30
Bill of Materials
Kemet
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Table 2-1. Bill of Materials (continued)
ITEM
DESIGNATOR
DESCRIPTION
39
J2, J5, J6, J7, J8, J15,
J16, J22, J23, J24, J27,
J28, J30, J32, J35, J39,
J42, J45, J46, J47, J48,
J49, J50, J51, J53, J54,
J55, J56, J58, J59, J61,
J65, J66, J67
40
MANUFACTURER
PART NUMBER
QUANTI
TY
Header, 100mil, 2x1, Gold plated,
TE Connectivity
TH, Header, 100mil, 2x1, Gold
plated, TH, Header, 100mil, 2x1,
Gold plated, TH, Header, 100mil,
2x1, Gold plated, TH, Header,
100mil, 2x1, Gold plated, TH,
Header, 100mil, 2x1, Gold plated,
TH, Header, 100mil, 2x1, Gold
plated, TH, Header, 100mil, 2x1,
Gold plated, TH, Header, 100mil,
2x1, Gold plated, TH, Header,
100mil, 2x1, Gold plated, TH,
Header, 100mil, 2x1, Gold plated,
TH, Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold plated,
TH, Header, 100mil, 2x1, Gold
plated, TH, Header, 100mil, 2x1,
Gold plated, TH, Header, 100mil,
2x1, Gold plated, TH, Header,
100mil, 2x1, Gold plated, TH,
Header, 100mil, 2x1, Gold plated,
TH, Header, 100mil, 2x1, Gold
plated, TH, Header, 100mil, 2x1,
Gold plated, TH, Header, 100mil,
2x1, Gold plated, TH, Header,
100mil, 2x1, Gold plated, TH,
Header, 100mil, 2x1, Gold plated,
TH, Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold, TH,
Header, 100mil, 2x1, Gold plated,
TH, Header, 100mil, 2x1, Gold, TH
(UNSTUFF), Header, 100mil, 2x1,
Gold, TH (UNSTUFF), Header,
100mil, 2x1, Gold, TH (UNSTUFF)
5-146261-1
34
J3, J14, J18, J19, J26,
J33, J37, J40, J41, J44,
J60
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, TH, 100mil, 3x1, Gold
plated, 230 mil above insulator,
Header, 100mil, 3x1, Gold, TH
Samtec, Inc.,
Inc., Samtec,
Samtec, Inc.,
Inc., Samtec,
Samtec, Inc.,
Inc., Samtec,
Samtec, Inc.,
TSW-103-07-G-S
11
41
J4, J62, J63, J64
Header, 100mil, 3x1, Tin, TH
TE Connectivity
5-146278-3
4
42
J9, J11, J12, J13
Connector, End launch SMA, 50
ohm, SMT
Emerson Network
Power
142-0701-851
4
43
J10, J43
Header, TH, 100mil, 10x2, Gold
plated, 230 mil above insulator
Samtec
TSW-110-07-G-D
2
44
J17, J52
RIGHT ANGLE PLUG FOR PCB
Rosenberger
59S20X-400L5-Y
2
Samtec,
Inc.,
Samtec,
Inc.,
Samtec,
Inc.,
Samtec
SNLU140A – November 2014 – Revised August 2015
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Bill of Materials
31
Cable References
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Table 2-1. Bill of Materials (continued)
ITEM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QUANTI
TY
45
J20
Header, 100mil, 4x1, White, TH
Molex
0022112042
1
46
J21
Header, TH, 100mil, 16x2, Gold
plated, 230 mil above insulator
Samtec, Inc.
TSW-116-07-G-D
1
47
J25
Header, TH, 100mil, 4x1, Gold
plated, 230 mil above insulator
Samtec, Inc.
TSW-104-07-G-S
1
48
J29
Connector, Receptacle, Mini-USB
Type B, R/A, Top Mount SMT
TE Connectivity
1734035-2
1
49
J31
Header, 100mil, 7x2, Tin, TH
Sullins Connector
Solutions
PEC07DAAN
1
50
J36
Connector, DC Jack 2.1X5.5 mm,
TH
CUI Inc.
PJ-102A
1
51
J57
Header, 100mil, 5x2, Tin, TH
Sullins Connector
Solutions
PEC05DAAN
1
52
J68
Standard Banana Jack, Insulated,
Black
Keystone
6092
1
53
J69
Standard Banana Jack, Insulated,
Red
Keystone
6091
1
54
L1, L7, L13
1.5A Ferrite Bead, 330 ohm @
100MHz, SMD
MuRata
BLM18SG331TN1D
3
55
L2
EMI Filter
Murata
BLM15AX102SN1D
1
56
L3, L5
1.5A Ferrite Bead, 330 ohm @
100MHz, SMD
TDK
MPZ1608S102A
2
57
L4, L6, L8
1.5A Ferrite Bead, 330 ohm @
100MHz, SMD
MuRata
BLM18SG121TN1D
3
58
L9
Ferrite Bead, 60 ohm @ 100MHz,
0.8A, 0603
Taiyo Yuden
BK1608HS600-T
1
59
L10, L11
Coupled inductor, 0.28 A, 0.41
ohm, +/- 25%, SMD
MuRata
DLW21SN900HQ2L
2
60
L14
Inductor, Shielded Drum Core,
Ferrite, 4.7uH, 4.2A, 0.02 ohm,
SMD
Wurth Elektronik eiSos
7440650047
1
61
LBL1
Thermal Transfer Printable Labels,
0.650" W x 0.200" H - 10,000 per
roll
Brady
THT-14-423-10
1
62
P1
HSD Right Angle Plug for PCB, TH Rosenberger
D4S20D-40ML5-Z
1
63
Q3, Q4
MOSFET, N-CH, 50 V, 0.22 A,
SOT-23
Fairchild
Semiconductor
BSS138
2
64
R1, R2
RES, 100 ohm, 1%, 0.063W, 0402
Vishay-Dale
CRCW0402100RFKED
2
65
R3, R7, R9, R10, R16,
RES, 0 ohm, 5%, 0.063W, 0402
R20, R21, R22, R32, R34,
R38, R39, R42, R43, R73,
R82, R106, R107, R111,
R113, R126, R127, R131,
R134, R135, R136, R137,
R138, R139, R140, R141,
R143, R144, R145, R146,
R147, R163, R198, R203,
R206
Panasonic
ERJ-2GE0R00X
40
32
Bill of Materials
SNLU140A – November 2014 – Revised August 2015
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Table 2-1. Bill of Materials (continued)
ITEM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QUANTI
TY
66
R4, R5, R6, R8, R24, R29,
R103, R104, R112, R116,
R118, R154, R156, R181,
R184, R194, R208
RES, 10.0k ohm, 1%, 0.063W,
0402, RES, 10.0k ohm, 1%,
0.063W, 0402, RES, 10.0k ohm,
1%, 0.063W, 0402, RES, 10.0k
ohm, 1%, 0.063W, 0402, RES,
10.0k ohm, 1%, 0.063W, 0402,
RES, 10.0k ohm, 1%, 0.063W,
0402, RES, 10.0k ohm, 1%,
0.063W, 0402, RES, 10.0k ohm,
1%, 0.063W, 0402, RES, 10.0k
ohm, 1%, 0.063W, 0402, RES,
10.0k ohm, 1%, 0.063W, 0402,
RES, 10.0 k, 1%, 0.063 W, 0402,
RES, 10.0k ohm, 1%, 0.063W,
0402, RES, 10.0k ohm, 1%,
0.063W, 0402, RES, 10.0k ohm,
1%, 0.063W, 0402, RES, 10.0k
ohm, 1%, 0.063W, 0402, RES,
10.0k ohm, 1%, 0.063W, 0402,
RES, 10.0 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040210K0FKED
17
67
R13, R33, R36, R158,
R160, R189, R195, R204,
R207
RES, 0 ohm, 5%, 0.1W, 0603
Vishay-Dale
CRCW06030000Z0EA
9
68
R17, R40, R110
RES, 49.9, 1%, 0.063 W, 0402,
Vishay-Dale
RES, 49.9 ohm, 1%, 0.063W, 0402
(UNSTUFF), RES, 49.9 ohm, 1%,
0.063W, 0402 (UNSTUFF)
CRCW040249R9FKED
3
69
R18, R19
RES, 0, 5%, 0.05 W, 0201
Panasonic
ERJ-1GE0R00C
2
70
R23, R35, R148, R173
RES, 2.4 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04022K40JNED
4
71
R25, R37
RES, 0 ohm, 5%, 0.063W, 0402
(UNSTUFF)
Yageo America
RC0402JR-070RL
2
72
R27, R123, R124
RES, 4.7k ohm, 5%, 0.063W, 0402 Vishay-Dale
CRCW04024K70JNED
3
73
R30
RES, 470 ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW0402470RJNED
1
74
R31, R152
RES, 180, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402180RJNED
2
75
R41, R193, R196, R200,
R205
RES, 100k ohm, 5%, 0.063W,
0402
Vishay-Dale
CRCW0402100KJNED
5
76
R49, R60, R79, R85
RES, 115 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402115KFKED
4
77
R50, R71, R86, R98
RES, 107 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402107KFKED
4
78
R51, R87
RES, 113 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402113KFKED
2
79
R52, R88
RES, 82.5 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040282K5FKED
2
80
R53, R89
RES, 51.1 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040251K1FKED
2
81
R54, R67, R90, R94
RES, 30.9 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040230K9FKED
4
82
R55, R64, R66, R75, R91, RES, 40.2 k, 1%, 0.063 W, 0402
R93
Vishay-Dale
CRCW040240K2FKED
6
83
R58
RES, 133 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402133KFKED
1
84
R59
RES, 147 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402147KFKED
1
85
R61, R69, R78, R96
RES, 90.9 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040290K9FKED
4
86
R62
RES, 66.5 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040266K5FKED
1
87
R63
RES, 21.5 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040221K5FKED
1
88
R68, R95
RES, 52.3 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040252K3FKED
2
89
R70, R97
RES, 105 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402105KFKED
2
90
R72, R99
RES, 118 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402118KFKED
2
91
R76
RES, 35.7 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040235K7FKED
1
92
R77
RES, 71.5 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040271K5FKED
1
93
R80
RES, 137 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402137KFKED
1
SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Bill of Materials
33
Cable References
www.ti.com
Table 2-1. Bill of Materials (continued)
ITEM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QUANTI
TY
94
R81
RES, 80.6 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040280K6FKED
1
95
R102
RES, 1.0 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04021K00JNED
1
96
R108, R109
RES, 1.50k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04021K50FKED
2
97
R115, R117, R119, R120,
R121, R122, R125, R128,
R130
RES, 100, 1%, 0.05 W, 0201
Panasonic
ERJ-1GEF1000C
9
98
R132
RES, 0.51 ohm, 1%, 0.1W, 0603
Panasonic
ERJ-3RQFR51V
1
99
R133, R157, R159
RES, 3.24k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04023K24FKED
3
100
R149, R174
RES, 220, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402220RJNED
2
101
R153, R178
RES, 1.5 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04021K50JNED
2
102
R155
RES, 3.0 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04023K00JNED
1
103
R161
RES, 1.65k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04021K65FKED
1
104
R162
RES, 1.37k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04021K37FKED
1
105
R176, R177
RES, 33 ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW040233R0JNED
2
106
R179, R182
RES, 33k ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW040233K0JNED
2
107
R180
RES, 1.2Meg ohm, 5%, 0.1W,
0603
Vishay-Dale
CRCW06031M20JNEA
1
108
R183
RES, 200 ohm, 5%, 0.063W, 0402
Vishay-Dale
CRCW0402200RJNED
1
109
R187
RES, 22.1k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW040222K1FKED
1
110
R188
RES, 124k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW0402124KFKED
1
111
R197
RES, 1.87k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04021K87FKED
1
112
R199
RES, 4.99k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04024K99FKED
1
113
R209
RES, 0, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04020000Z0ED
1
114
S1
Switch, Slide, SPST 3 poles, SMT
CTS
Electrocomponents
219-3LPST
1
115
S2, S3, S6
Switch, Slide, SPST 8 poles, SMT
CTS
Electrocomponents
219-8MST
3
116
S4, S9
Switch, Normally open, 2.3N force,
200k operations, SMD
C and K Components
KSR221GLFS
2
117
S5
DIP Switch, 4 position slide
actuator, SPST, SMD
Omron Electronic
Components
A6S-4104-H
1
118
SH-J4, SH-J14, SH-J16,
SH-J18, SH-J19, SH-J26,
SH-J33, SH-J37, SH-J40,
SH-J41, SH-J46, SH-J48,
SH-J49, SH-J60
Shunt, 100mil, Gold plated, Black
3M
969102-0000-DA
14
119
U2
1080p OpenLDI to FPD-Link III
Serializer, RGC0064K
Texas Instruments
DS90Ux947RGCQ1
1
120
U3
Single-ended, Analog-input 24-BIT, Texas Instruments
96-kHz Stereo A/D Converter,
PW0014A
PCM1808PW
1
121
U4
IC, Automotive LDO Positive
Voltage Regulators, 5V
Texas Instruments
TL751M05QKVURQ1
1
122
U5
4-channel ESD-Protection Array
For high-speed Data Interfaces,
DRY006A
Texas Instruments
TPD4E004DRY
1
34
Bill of Materials
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Table 2-1. Bill of Materials (continued)
ITEM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
QUANTI
TY
123
U6
Mixed Signal MicroController,
PN0080A
Texas Instruments
MSP430F5529IPN
1
124
U7
TCA9406 Dual Bidirectional 1-MHz Texas Instruments
I2C-BUS and SMBus Voltage
Level-Translator, 1.65 to 3.6 V, -40
to 85 degC, 8-pin US8 (DCU),
Green (RoHS & no Sb/Br)
TCA9406DCUR
1
125
U8
IC, 6-BIT Bidirectional Voltagelevel translator
Texas Instruments
TXB0106PWR
1
126
U10
IC, 1.5A LDO Regulator with SoftStart
Texas Instruments
TPS74701DRC
1
127
U11
Dual Output LDO, 1 A, Fixed 1.8,
Texas Instruments
3.3 V Output, 2.7 to 10 V Input, 28pin HTSSOP (PWP), -40 to 125
degC, Green (RoHS & no Sb/Br)
TPS767D318PWP
1
128
U12
800 mA Fast-Response HighAccuracy Adjustable LDO Linear
Regulator with Enable and SoftStart, 7-pin TO-263
Texas Instruments
LP38851S-ADJ
1
129
U17
500mA, Low Quiescent Current,
Ultra-Low Noise, High PSRR LowDropout Linear Regulator,
DRB0008A
Texas Instruments
TPS73533DRB
1
130
X2
OSC, 170 MHz, 3.3 Vdc, SMD
Fox Electronics
FXO-LC735R-170
1
131
Y1
OSC, 12.288 MHz, 3.3 Vdc, SMD
ECS Inc.
ECS-8FA3X-122.8-TR
1
132
Y2
OSC, 96 MHz, 3.3 Vdc, SMD
Fox Electronics
FXO-HC736R-96
1
133
Y3
Crystal, 24.000MHz, 20pF, SMD
ECS Inc.
ECS-240-20-5PX-TR
1
134
J34
Header, 100mil, 2x1, Gold plated,
TH
TE Connectivity
5-146261-1
0
135
R11, R12, R14, R15
RES, 0, 5%, 0.05 W, 0201
Panasonic
ERJ-1GE0R00C
0
136
R26, R28, R150, R151
RES, 0 ohm, 5%, 0.1W, 0603,
RES, 0 ohm, 5%, 0.1W, 0603,
RES, 0 ohm, 5%, 0.1W, 0603
(UNSTUFF), RES, 0 ohm, 5%,
0.1W, 0603 (UNSTUFF)
Vishay-Dale
CRCW06030000Z0EA
0
137
R44, R45, R46, R47,
R165, R166, R167, R168,
R169, R170, R171, R172,
R190, R191
RES, 51, 5%, 0.063 W, 0402
Vishay-Dale
CRCW040251R0JNED
0
138
R48, R56, R57, R65, R74, RES, 0 ohm, 5%, 0.063W, 0402
R83, R84, R92, R100,
(UNSTUFF)
R101, R142, R192
Panasonic
ERJ-2GE0R00X
0
139
R105
RES, 10.0k ohm, 1%, 0.063W,
0402 (UNSTUFF)
Vishay-Dale
CRCW040210K0FKED
0
140
R114, R164
RES, 3.24k ohm, 1%, 0.063W,
0402
Vishay-Dale
CRCW04023K24FKED
0
141
U1
Single High Speed Differential
Driver, 8-pin Narrow SOIC
National Semiconductor DS90LV017ATM
0
142
U9
IC, 4.5V-18V Input, 2-A Sync.
Step-Down SWIFT Converter
TI
TPS54225PWP
0
143
U15
Low-Capacitance + / - 15 kV ESD- Texas Instruments
Protection Array for High-Speed
Data Interfaces, 2 Channels, -40 to
+85 degC, 5-pin SOT (DRL),
Green (RoHS & no Sb/Br)
TPD2E001DRLR
0
144
H3, H4, H7, H8, H10, H12
Machine Screw, Round, #4-40 x
1/4, Nylon, Philips panhead
NY PMS 440 0025 PH
6
B&F Fastener Supply
SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Bill of Materials
35
Appendix A
www.ti.com
Appendix A
SNLU140A – November 2014 – Revised August 2015
EVM PCB Schematics
1
2
3
4
5
6
Revision History
Revision
Notes
A
A
REF OSC
LEDs
J10 (10x2)
0.5" spacing
pin to pin
100ohm differential traces
OLDI
B
J9 (SMA)
FPD3
100ohm differential trace until the end then 50 ohm single ended
J11 (SMA)
100ohm differential trace
DS90Ux947-Q1
B
100ohm differential trace
P1 (HSD)
100ohm differential traces
FPD3
100ohm differential trace
J12 (SMA)
100ohm differential trace until the end then 50 ohm single ended
J43 (10x2)
J13 (SMA)
USB-2-ANY
EXT UC
MODE_SEL
C
C
I2C
EXT CONN
IDx
All other traces not specified are 50ohm differential trace
SPI/D_GPIO
GPIO
I2S
INTB
5V
USB
3.3V
Power
12v Power Source
1.8V
D
D
Audio
ADC
1.1V
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By: Ryan Bailey
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
36
EVM PCB Schematics
2
3
4
5
Mod. Date: 11/19/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title: Block Diagram
Sheet: 2 of 10
Assembly Variant: 001
File: SV601153A_Cover Sheet_Block.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Appendix A
www.ti.com
1
2
3
4
5
U_DS90UX947-Q1EVM_SV600XXX-00X_CONNECTORS
SV601153A_CONNECTORS.SchDoc
IN_D0_P
IN_D0_N
IN_D1_P
IN_D1_N
A
IN_D2_P
IN_D2_N
IN_D3_P
IN_D3_N
IN_D4_P
IN_D4_N
IN_D5_P
IN_D5_N
IN_D6_P
IN_D6_N
IN_D7_P
IN_D7_N
IN_CLK_P
IN_CLK_N
DOUT0_P
DOUT0_N
B
DOUT1_P
DOUT1_N
SDIN/GPIO0
SWC/GPIO1
I2S_DC/GPIO2
I2S_DD/GPIO3
I2S_DB/GPIO5_REG
I2S_DA/GPIO6_REG
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
SCLK
MCLK
RES0_0
SDA
SCL
6
U_DS90UX947-Q1EVM_SV600XXX-00X_DS90Ux947
SV601153A_DS90Ux947.SchDoc
IN_D0_P
IN_D0_N
IN_D0_P
IN_D0_N
IN_D1_P
IN_D1_N
IN_D1_P
IN_D1_N
IN_D2_P
IN_D2_N
A
IN_D2_P
IN_D2_N
IN_D3_P
IN_D3_N
IN_D3_P
IN_D3_N
IN_D4_P
IN_D4_N
IN_D4_P
IN_D4_N
IN_D5_P
IN_D5_N
IN_D5_P
IN_D5_N
IN_D6_P
IN_D6_N
IN_D6_P
IN_D6_N
IN_D7_P
IN_D7_N
IN_D7_P
IN_D7_N
IN_CLK_P
IN_CLK_N
IN_CLK_P
IN_CLK_N
DOUT0_P
DOUT0_N
DOUT0_P
DOUT0_N
DOUT1_P
DOUT1_N
B
DOUT1_P
DOUT1_N
SDIN/GPIO0
SWC/GPIO1
I2S_DC/GPIO2
I2S_DD/GPIO3
I2S_DB/GPIO5_REG
I2S_DA/GPIO6_REG
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
SDIN/GPIO0
SWC/GPIO1
I2S_DC/GPIO2
I2S_DD/GPIO3
I2S_DB/GPIO5_REG
I2S_DA/GPIO6_REG
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
U_DS90UX947-Q1EVM_SV600XXX-00X_Cover Sheet_Block
SV601153A_Cover Sheet_Block.SchDoc
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
SCLK
MCLK
U_DS90UX947-Q1EVM_SV600XXX-00X_Power
SV601153A_Power.SchDoc
SCLK
MCLK
RES0_0
RES0_0
SDA
SCL
SDA
SCL
C
C
INTB
DAOUT
BCK
LRCK
SCKIN
INTB
INTB
DAOUT
BCK
LRCK
SCKIN
DAOUT
BCK
LRCK
SCKIN
MODE_SEL0
MODE_SEL1
IDx
PDB
U_DS90UX947-Q1EVM_SV600XXX-00X_Audio_IF
SV601153A_Audio_IF.SchDoc
MODE_SEL0
MODE_SEL1
IDx
PDB
MODE_SEL0
MODE_SEL1
IDx
PDB
SCLK
AIN_B_0
AIN_B_1
INTB
SCL
SDA
INTB
U_DS90UX947-Q1EVM_SV600XXX-00X_LED
SV601153A_LED.SchDoc
PDB
INTB
U_DS90UX947-Q1EVM_SV600XXX-00X_CONFIG
SV601153A_CONFIG.SchDoc
SPI_SS
SPI_CLK
SPI_SIMO
SPI_SOMI
GPIO3/PWM2
GPIO7/PWM0
GPIO8/ADC3
GPIO9/ADC2
GPIO10/VEREFGPIO11/VEREF+
D
D
U_DS90UX947-Q1EVM_SV600XXX-00X_MSP430F5529
SV601153A_MSP430F5529.SchDoc
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By: Ryan Bailey
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
2
3
4
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
5
Mod. Date: 11/19/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title: Block Diagram
Sheet: 2 of 10
Assembly Variant: 001
File: SV601153A_Cover Sheet_ANSI-B.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
EVM PCB Schematics
37
Appendix A
www.ti.com
1
2
3
4
5
6
VBUS
VDD33_UC_U17
U17
L9
C62
22µF
8
60 ohm
D11
1SMB5922BT3G
7.5V
C64
1µF
5
2
6
7
A
IN
EN
N/C
N/C
N/C
R13
1
OUT
1
2
C65
2.2µF
9
4
PAD
GND
J30
0
3
NR/FB
5-146261-1
C66
0.01µF
TPS73533DRB
A
J29
GND
VBUS
GND
VOLTAGE LEVEL TRANSLATOR
C96
0.1µF U8
GPIO2/SPI(SCLK)
12
GPIO5/SPI(SOMI)/UART(RXD) 10
3
2
1
13
GPIO4/SPI(SIMO)/UART(TXD) 11
KSR221GLFS
GND
GPIO6/PWM1/SPI(CS)
5-146261-1
S9
GND
IO2
IO1
R179
1
2
C100
C99
220pF
9
DNP
2
R180
1.2Meg
GND
0
VDD33_UC
14
12
10
8
6
4
2
Y3
24MHz
R182
33k
VCCA
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
GND
OE
C97
0.1µF
VDDIO
1
J53
5-146261-1
PDB
2
3
4 SPI_SS_A
SPI_SS_B
SPI_CLK_B
5 SPI_CLK_A
6 SPI_SIMO_A
SPI_SIMO_B
7 SPI_SOMI_A
SPI_SOMI_B
8
J54
5-146261-1
J55
5-146261-1
J56
5-146261-1
INTB
SPI_SS
SPI_CLK
SPI_SIMO
SPI_SOMI
R181
10.0k
GND
GND
C101
1
GND
GND
J31
PEC07DAAN
A1
VCCB
TXB0106PWR
20pF
R209
U5
TPD4E004DRY
B1
1
2
PUR
VUSB
14
1
2
15
SPI_SOMI_A
SPI_SOMI_B
5
6
4
IO3
IO4
VCC
11
8
16
MSP_430_INTB
J61
C98
0.1µF
33k
MSP_430_PDB
VDD33_UC
1.5k
SPI_SIMO_A
SPI_SIMO_B
DP
R178
1
2
DM
R177
1
2
R176
33
33
SPI_CLK_A
SPI_CLK_B
1
2
3
4
5
SPI_SS_A
SPI_SS_B
10
9
F1
0429007.WRML
20pF
VBUS
13
11
9
7
5
3
1
V18
VUSB
USB2ANY CONNECTOR
B
C102
2200pF
V18
B
J57
GPIO0/I2C(SDA) 1
GPIO2/SPI(SCLK) 3
DM
PUR
C103
220pF
GND
2
GPIO1/I2C(SCL)
GPIO3/PWM2
4
6
8 GPIO5/SPI(SOMI)/UART(RXD)
10 GPIO7/PWM0
5
GND
GPIO4/SPI(SIMO)/UART(TXD) 7
GPIO6/PWM1/SPI(CS)
9
DP
GND
PEC05DAAN
GND
8
9
GND
330 ohm
10
GPIO10/VEREF-
11
D4
Green
12
C
C106
10µF
C107
0.1µF
13
14
15
R183
200
16
17
3
18
Q4
1 BSS138
19
C108
0.1µF
GND
C109
0.47µF
GND
62
61
64
63
PUR
VSSU
PU.0/DP
PU.1/DM
70
69
66
65
VBUS
VUSB
71
68
67
V18
P7.0/CB8/A12
P5.7/TB0.1
U6
P7.1/CB9/A13
P7.2/CB10/A14
P5.6/TB0.0
MSP430F5529IPN
P4.7/PM_NONE
P7.3/CB11/A15
P4.6/PM_NONE
P5.0/A8/VREF+/VEREF+
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P5.1/A9/VREF-/VEREF-
P4.4/PM_UCA1TXD/PM_UCA1SIMO
AVCC1
DVCC2
P5.4/XIN
DVSS2
P5.5/XOUT
P4.3/PM_UCB1CLK/PM_UCA1STE
AVSS1
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P8.0
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P8.1
P4.0/PM_UCB1STE/PM_UCA1CLK
60
GPIO3/PWM2
59
R25
MSP_430_PDB
0
58
GPIO7/PWM0
57
R37
MSP_430_INTB
0
56
55
54
53
52
GPIO5/SPI(SOMI)/UART(RXD)
51
GPIO4/SPI(SIMO)/UART(TXD)
VDD33_UC
50
49
C105
0.1µF
48
C
47
46
GND
45
P8.2
DVCC1
P3.7/TB0OUTH/SVMOUT
DVSS1
P3.6/TB0.6
VCORE
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
AVSS2
PJ.0/TDO
P5.2/XT2IN
P5.3/XT2OUT
TEST/SBWTCK
75
72
73
76
77
78
79
74
PJ.2/TMS
PJ.3/TCK
P6.0/CB0/A0
P7.4/TB0.2
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
2
20
P7.5/TB0.3
P3.5/TB0.5
P3.4/UCA0RXD/UCA0SOMI
37
L13
P7.6/TB0.4
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
7
C104
0.1µF
P7.7/TB0CLK/MCLK
P6.7/CB7/A7
44
43
42
41
GPIO2/SPI(SCLK)
I2C LEVEL TRANSLATOR
U7
5
4
SCL
SDA
39
40
1
2
3
6
GPIO11/VEREF+
VDD33_UC
P6.6/CB6/A6
P3.1/UCB0SOMI/UCB0SCL
5
VDD33_UC_U17
P6.5/CB5/A5
38
J4
5-146278-3
P6.4/CB4/A4
P3.0/UCB0SIMO/UCB0SDA
4
PJ.1/TDI/TCLK
3
P6.1/CB1/A1
2
AIN_B_1
GPIO8/ADC3
P6.2/CB2/A2
1
AIN_B_0
GPIO9/ADC2
SH-J4
VDD33
P6.3/CB3/A3
ZZ12
Assembly Note
Place SH-J4 on pin 2 and 3
RST/NMI/SBWTDIO
80
GND
VDD33_UC
R184
VDD_I2C
10.0k
SCL_A
SDA_A
6
SCL_B
SDA_B
GPIO1/I2C(SCL)
GPIO0/I2C(SDA)
8
1
OE
3
7
VCCA
VCCB
GND
2
TCA9406DCUR
C110
0.1µF
VDD33_UC
R108
1.50k
J58
GPIO7/PWM0
D
1
2
GPIO7/PWM0
GPIO6/PWM1/SPI(CS)
C111
0.1µF
R109
1.50k
GND
D
5-146261-1
GPIO3/PWM2
GPIO3/PWM2
J59
1
2
MSP_430_INTB
5-146261-1
MSP_430_PDB
Number: SV601153
Rev: A
SVN Rev: Not in version control
Drawn By: Downs
Engineer: Tran Dam
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
1
38
EVM PCB Schematics
2
3
4
5
Designed for: Public Release
Mod. Date: 11/24/2014
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title: USB2ANY
Sheet: 1 of 10
Assembly Variant: 001
File: SV601153A_MSP430F5529.SchDoc
Size: C
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Appendix A
www.ti.com
1
2
3
4
VDD18
5
6
VDDL11
L4
1 kOhm
1
L3
120 ohm
C16
0.01µF
C17
0.01µF
C18
0.01µF
C22
1µF
C19
0.1µF
C25
10µF
12
C2
10µF
C1
10µF
C26
0.01µF
C27
0.01µF
C28
0.1µF
C30
1µF
2
C15
10µF
VDD1V8
VDD11
VDDR11
VDDIO
L5
A
L6
GND
1 kOhm
GND
A
120 ohm
C32
10µF
C3
10µF
C33
0.01µF
C34
0.01µF
C35
0.1µF
C37
1µF
C36
0.1µF
C38
1µF
C39
10µF
C4
10µF
C40
0.01µF
C41
0.01µF
C42
0.01µF
C44
0.1µF
C48
1µF
VDDT11
L8
GND
VDDA11
GND
120 ohm
C56
10µF
LAYOUT: PLACE 0.01uF ADJACENT (CLOSEST CAP) TO EACH POWER PIN
C6
10µF
C57
0.01µF
C58
0.01µF
C59
0.01µF
C60
0.1µF
C63
1µF
C67
0.01µF
C68
0.01µF
GND
VDD33
GND
IN_D0_N
R115
IN_D0_P
100
5-146261-1
Y2
J50
5-146261-1
1
2
1
2
E/D
VDD
GND
OUT
4
FXO-HC736R-96
96 MHz
2
6
5
3
1
2
1
5-146261-1
J28
DI1
NC
NC
NC
VCC
DO1+
DO1-
7
8
R26
0
DNP
R28
0
DNP
LAYOUT: To J10
GND
1
2
C
LAYOUT: PLACE R150, R151
near J10 connector as stub cutter
IN_D5_N
R125
IN_D5_P
100
R150
0
DNP
R151
0
DNP
C13
0.01µF
5-146261-1
IN_CLK_N
IN_CLK_P
IN_D4_N
R122
IN_D4_P
100
4
GND
X2
J51
2
1
2
1
5-146261-1
3
NC
VDD
E/D
OutputN
GND
OutputP
6
5
4
R33
R36
42
9
LAYOUT:
PLACE X1, X2, U1 and associated
components on backside of board
0
0
IN_D0_N
IN_D0_P
IN_D1_N
IN_D1_P
IN_D2_N
IN_D2_P
IN_CLK_N
IN_CLK_P
IN_D3_N
IN_D3_P
IN_D4_N
IN_D4_P
IN_D5_N
IN_D5_P
IN_D6_N
IN_D6_P
IN_D7_N
IN_D7_P
IN_D6_N
R128
IN_D6_P
100
IN_D7_N
R130
IN_D7_P
100
C80
IN_D0_N
IN_D0_P
IN_D1_N
IN_D1_P
IN_D2_N
IN_D2_P
IN_CLK_N
IN_CLK_P
IN_D3_N
IN_D3_P
IN_D4_N
IN_D4_P
IN_D5_N
IN_D5_P
IN_D6_N
IN_D6_P
IN_D7_N
IN_D7_P
0.01µF R20
0
LFOLDI
FXO-LC735R-170
170 MHz
SDIN/GPIO0
SWC/GPIO1
SCLK
MCLK
D
52
51
IN_D1_P
IN_D1_N
54
53
IN_D2_P
IN_D2_N
56
55
IN_D3_P
IN_D3_N
60
59
IN_D4_P
IN_D4_N
2
1
IN_D5_P
IN_D5_N
4
3
IN_D6_P
IN_D6_N
6
5
IN_D7_P
IN_D7_N
8
7
IN_CLK_P 58
IN_CLK_N 57
LFOLDI
R139 0
R140 0
R141 0
R142 0
DNP
SDIN/GPIO0_R
SWC/GPIO1_R
SCLK_R
MCLK_R
R143 0
R144 0
R145 0
R43
0
D_GPIO0/MOSI_R
D_GPIO1/MISO_R
D_GPIO2/SPLK_R
D_GPIO3/SS_R
R165
R166
R167
R168
R169
R170
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
I2S_WC/GPIO7_REG_R
I2S_CLK/GPIO8_REG_R
I2S_DA/GPIO6_REG_R
I2S_DB/GPIO5_REG_R
I2S_DC/GPIO2_R
I2S_DD/GPIO3_R
R44
R45
R46
R47
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
I2S_DA/GPIO6_REG
I2S_DB/GPIO5_REG
I2S_DC/GPIO2
I2S_DD/GPIO3
GND
0
0
0
0
0
0
R171
R172
R190
R191
GND
R131
R134
R135
R136
R137
R138
IN_D0_P
IN_D0_N
PDB_R
RES40
I2S_WC/GPIO7_REG_R
I2S_CLK/GPIO8_REG_R
I2S_DA/GPIO6_REG_R
I2S_DB/GPIO5_REG_R
I2S_DC/GPIO2_R
I2S_DD/GPIO3_R
63
31
40
34
35
36
37
38
39
VDDIO
VDDIO
VDDL11
VDDL11
D0+
D0-
VDDOA11
VDDOA11
VDDOP11
DOUT0+
DOUT0-
D1+
D1-
DOUT1+
DOUT1-
51
51
51
51
51
51
51
51
VDDA11
LF
D3+
D3IDx
D4+
D4-
MODE_SEL0
D5+
D5-
MODE_SEL1
D6+
D6-
D_GPIO0 / MOSI
D_GPIO1 / MISO
D_GPIO2 / SPLK
D_GPIO3 / SS
D7+
D7CLK+
CLK-
LFOLDI
PDB
RES2
I2S_WC / GPIO7_REG
I2S_CLK / GPIO8_REG
I2S_DA / GPIO6_REG
I2S_DB / GPIO5_REG
I2S_DC / GPIO2
I2S_DD / GPIO3
SDA
SCL
INTB
RES3
REM_INTB
I2CSEL
GPIO1
GPIO0
NC
RES1
RES0
PAD
GND
GND
21
28
25
12
17
27
26
DOUT0U2_P
DOUT0U2_N
23
22
DOUT1U2_P
DOUT1U2_N
C73
0.1µF
DOUT0_P
DOUT0_N
C74
0.1µF
20
LF
19
IDx
18
MODE_SEL0
32
MODE_SEL1
D_GPIO0/MOSI_R
D_GPIO1/MISO_R
D_GPIO2/SPLK_R
D_GPIO3/SS_R
48
47
49
41
10
SDA_R
SCL_R
INTB_R
RES41
GPO_INTB
13
15
14
11
SCLK_R
SWC/GPIO1_R
SDIN/GPIO0_R
MCLK_R
EXT_R
29
RES0_0
PAD
SH-J18
1
2
3
TSW-103-07-G-S
GND
IDx
MODE_SEL0
MODE_SEL1
ZZ18
Assembly Note
C
Place SH-J40 on pin 2 and 3
IDx
MODE_SEL0
MODE_SEL1
R18
R19
0
0
J40
1
2
3
SH-J40
VDDIO
TSW-103-07-G-S
PullDown
SDA_R
SCL_R
R21
R22
0
0
PDB_R
R34
0
R27
4.7k
SDA
SCL
R32
0
ZZ21
Assembly Note
Place SH-J19 on pin 2 and 3
R29
10.0k
INTB
PDB
VDDIO
R118
10.0k
GND
SH-J19
1
2
3
SCLK_R
30
VDDIO_PullUp
J18
C77
0.01µF
49.9
RES40
RES41
R24 ZZ19
10.0k Assembly Note
Place SH-J18 on pin 2 and 3
DOUT1_P
DOUT1_N
C76
0.1µF
R16
0
R17
LF
EXT_R
46
45
44
43
VDDIO
DOUT0_P
DOUT0_N
DOUT1_P
DOUT1_N
C78
0.1µF
D2+
D2-
C71
0.1µF
B
VDDT11
GND
VDDHS11
VDDHS11
VDDS11
VDDA11
VDDP11
C70
0.1µF
64
50
61
DNP
DNP
DNP
DNP
DNP
DNP DNP
DNP
DNP
DNP DNP
DNP
DNP
DNP
51
51
51
51
51
51
C69
0.1µF
VDDR11
VDD18
VDD18
VDDL11
IN_D3_N
R121
IN_D3_P
100
DNP
DS90LV017ATM
16
33
IN_CLK_N
R120
IN_CLK_P
100
U1
C12
0.1µF
U2
24
62
VDDIO
IN_D2_N
R119
IN_D2_P
100
GND
GND
J27
VDD18
IN_D1_N
R117
IN_D1_P
100
C11
0.01µF
3
MODE_SEL1
IDx
1
2
B
MODE_SEL0
L2
BLM15AX102SN1D
C10
4.7µF
J23
1
2
3
GPO_INTB
J19
TSW-103-07-G-S
J44
TSW-103-07-G-S
R208
RES0_0
PAD
R42
RES0_0
0
D
10.0k
DS90UH947RGCQ1
GND
GND
DNP These resistors
GND
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
2
3
4
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
5
Mod. Date: 11/26/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title:
Sheet: 4 of 10
Assembly Variant: 001
File: SV601153A_DS90Ux947.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
EVM PCB Schematics
39
Appendix A
www.ti.com
1
2
3
4
VDD1V8
DNP
R48
DNP
0
5
6
VDD1V8
R49
115k
R50
107k
R51
113k
R52
82.5k
R53
51.1k
R54
30.9k
R67
30.9k
R68
52.3k
R69
90.9k
R70
105k
R71
107k
R72
118k
R55
40.2k
DNP
R56
DNP
0
DNP
R57
DNP
0
R58
133k
R59
147k
R60
115k
R61
90.9k
R62
66.5k
R63
21.5k
R64
40.2k
DNP
R65
DNP
0
R76
35.7k
R77
71.5k
R78
90.9k
R79
115k
R80
137k
R81
80.6k
R82
0
DNP
R83
DNP
0
A
A
R66
40.2k
DNP
R73
0
GND
DNP
R74
DNP
0
GND
R75
40.2k
GND
GND
S2
219-8MST
S3
219-8MST
1
2
3
4
5
6
7
8
I2C Address Select (IDx)
1
2
3
4
5
6
7
8
Mode Select 0 (MODE_SEL0)
ZZ7
Assembly Note
S3: Connect 1 and 16
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
ZZ6
Assembly Note
S2: Connect 1 and 16
B
B
MODE_SEL0
IDx
J6
8'b
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
1
2
3
4
5
6
7
8
J5
C81
0.1µF
1
2
5-146261-1
C82
0.1µF
1
2
5-146261-1
GND
GND
VDD1V8
DNP
R84
DNP
0
R93
40.2k
R85
115k
R86
107k
R87
113k
R88
82.5k
R89
51.1k
R90
30.9k
R91
40.2k
R94
30.9k
R95
52.3k
R96
90.9k
R97
105k
R98
107k
R99
118k
DNP
R100
DNP
0
DNP
R92
DNP
0
VDDIO
DNP
R101
DNP
0
J7
R102 R103 R104 R105
DNP
1.0k 10.0k 10.0k
10.0k
1
2
C
GND
PDB
INTB
SCLK
0
0
R106
R107
KSR221GLFS
C83
10µF
8
7
6
5
GND
C
5-146261-1
S4
GND
S5
A6S-4104-H
ZZ9
Assembly Note
S6: Connect 1 and 16
16
15
14
13
12
11
10
9
1
2
3
4
GND
GND
1
2
3
4
5
6
7
8
PDB
INTB
I2CSEL
RES
Mode Switches
S6
219-8MST
Mode Select 1 (MODE_SEL1)
ZZ8
Assembly Note
S5: Connect 1 and 8, 2 and 7
MODE_SEL1
J8
1
2
3
4
5
6
7
8
D
C84
0.1µF
D
1
2
5-146261-1
GND
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
40
EVM PCB Schematics
2
3
4
5
Mod. Date: 11/24/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title:
Sheet: 6 of 10
Assembly Variant: 001
File: SV601153A_CONFIG.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Appendix A
www.ti.com
1
2
3
4
5
6
100ohm differential traces
J10
IN_D2_P
A
IN_CLK_P
IN_D3_P
IN_D2_P
IN_CLK_P
IN_D3_P
IN_D0_N
2
4
6
8
10
12
14
16
18
20
IN_D0_N
IN_D1_N
IN_D1_N
DOUT0_P
DOUT0_P
L10_P
LABEL "DOUT0+"
IN_D2_N
3
IN_D1_P
4
1
3
5
7
9
11
13
15
17
19
IN_D0_P
IN_D2_N
IN_CLK_N
IN_D3_N
LAYOUT NOTE:
Place P1 centered between J11 & J12
L10
100ohm differential trace
DLW21SN900HQ2L
6mil trace width
14mil trace gap
100ohm differential trace
IN_CLK_N
A
LABEL "DOUT0-"
IN_D3_N
DOUT0_N
DOUT0_N
TSW-110-07-G-D
2
IN_D1_P
1
IN_D0_P
L10_N
P1
EMITTER
0.5" spacing
center of pin to center of pin
SMA_D0N
SMA_D0P
1
3
SMA_D1N
SMA_D1P
2
4
PAIR A1
J43
IN_D6_P
IN_D5_P
IN_D6_P
TP2
IN_D7_P
PAIR A2
IN_D7_P
IN_D4_N
DOUT1_P
LABEL PINS "p1=0-, p2=1-"
L11
DLW21SN900HQ2L
IN_D6_N
LABEL "DOUT1-"
IN_D7_N
DOUT1_N
DOUT1_N
L11_N
TSW-110-07-G-D
GND
GND
LABEL PINS "p3=0+, p4=1+"
ON BACKSIDE OF BOARD
100ohm differential trace
TP1
TESTPOINT
IN_D7_N
D4S20D-40ML5-Z
3
LABEL "DOUT1+"
IN_D5_N
IN_D6_N
4
DOUT1_P
IN_D5_N
L11_P
2
IN_D5_P
IN_D4_N
2
4
6
8
10
12
14
16
18
20
1
IN_D4_P
1
3
5
7
9
11
13
15
17
19
IN_D4_P
100ohm differential trace
6mil trace width
14mil trace gap
GND
B
B
100ohm differential traces
Layout note:
J17
59S20X-400L5-Y
Overlay footprint for SMA and FAKRA
connector - signal pin 1 on both is the
Same pad
U15
1
IO1
IO2
DNP
DOUT0SMA0_P
0
DNP
50ohm single-ended trace
VDD_I2C
SCL
SDA
SCL
SDA
VDDIO
142-0701-851
C86
0.1µF
R123 R124
4.7k 4.7k
GND
0.625"
J20
1
2
3
4
GND
R126 0
R127 0
R113
C87
4.7pF
I2S_DC/GPIO2
I2S_DD/GPIO3
0
C88
4.7pF
I2S_DB/GPIO5_REG
I2S_DA/GPIO6_REG
I2S_WC/GPIO7_REG
I2S_CLK/GPIO8_REG
0022112042
DNL
142-0701-851
C
GND
0
i Place 0-ohm as close to trace as possible
Layout note:
1
2
INTB
Overlay footprint for SMA and FAKRA
connector - signal pin 1 on both is the
Same pad
LABEL "INTB"
LABEL "GND"
1.25"
J52
59S20X-400L5-Y
J15
SDIN/GPIO0
SWC/GPIO1
SCLK
MCLK
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
1
MH1
MH2
MH3
MH4
5-146261-1
GND
DOUT1_P
VDDIO
GND
R116
10.0k
J25
DAOUT
LRCK
BCK
SCKIN
1
GND
142-0701-851
0.625"
J14
1
2
3
RES0_0
J12
DNP
R14
0
DOUT0SMA1_P
DNP
50ohm single-ended trace
ZZ20
Assembly Note
Place SH-J14 on pin 2 and 3
0 0 0 0
1
2
3
4
J11
1
GND
R38
R39
R146
R147
TSW-116-07-G-D
R111
DOUT0_N R12
5
4
3
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
DNP
0
DOUT0SMA0_N
DNP
50ohm single-ended trace
R40
49.9
LABEL "VDD_I2C"
LABEL "SCL"
LABEL "SDA"
LABEL "GND"
J21
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
GND
1
4
GND
TPD2E001DRLR
C
J9
DOUT0_P R11
2
NC
DNP
VCC
5
4
3
2
3
5
5
4
3
2
SCL
SDA
SH-J14
DOUT1_N
TSW-104-07-G-S
DNP
R15
0
DOUT0SMA1_N
DNP
50ohm single-ended trace
R110
49.9
TSW-103-07-G-S
DNL
J13
1
5
4
3
2
VDD_I2C
MH1
MH2
MH3
MH4
1
142-0701-851
D
D
GND
GND
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
2
3
4
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
5
Mod. Date: 11/24/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title:
Sheet: 7 of 10
Assembly Variant: 001
File: SV601153A_CONNECTORS.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
EVM PCB Schematics
41
Appendix A
www.ti.com
1
2
3
4
5
6
A
A
H1
FID1
H2
H3
H9
H4
H10
1902C
NY PMS 440 0025 PH
1902C
1902C
NY PMS 440 0025 PH
NY PMS 440 0025 PH
PCB Number: SV601153
PCB Rev: A
H5
H6
H11
VDD5V
12V_IN_B4JUMP
H8
1902C
VBUS
VDD33
VDD5V
1902C
Texas Instruments
PCB
LOGO
R35
2.4k
PCB Label
Size: 0.65" x 0.20 "
R23
2.4k
R173
2.4k
2
D3
Orange
1
D10
Green
R30
470
R174
220
R31
180
R148
2.4k
R152
180
Q3
GND
ZZ1
Label Assembly Note
This Assembly Note is for PCB labels only
B
D1
Green
R149
220
Pb-Free Symbol
LBL1
D9
Green
3
PCB
LOGO
Board Silkscreen Label: "Not for EMI Testing"
D7
Green
1
D6
Green
1
2
FID3
1
FID2
2
NY PMS 440 0025 PH
2
NY PMS 440 0025 PH
B
1
NY PMS 440 0025 PH
VDD_EXT
H12
1902C
2
H7
1 BSS138
GND
2
PCB
LOGO
R41
100k
FCC disclaimer
GND
GND
GND
ZZ2
Assembly Note
These assemblies are ESD sensitive, ESD precautions shall be observed.
C
GND
INTB
C
ZZ3
Assembly Note
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
1
2
J65
5-146261-1
1
2
J67
5-146261-1
J66
5-146261-1
1
2
ZZ4
Assembly Note
These assemblies must comply with workmanship standards IPC-A-610 Class 2., unless otherwise specified.
VDD_I2C
VDD1V8
VDD11
GND
GND
GND
D
D
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
42
EVM PCB Schematics
2
3
4
5
Mod. Date: 11/24/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title:
Sheet: 8 of 10
Assembly Variant: 001
File: SV601153A_LED.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Appendix A
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1
2
3
4
5
6
VDD_EXT
C112
2
1
C54
0.1µF
C55
0.1µF
C61
1µF
10pF
J45
5-146261-1
GND
VDD5V
ZZ11
Assembly Note
Place SH-J33 on pin 1 and 2
J32
VBUS
1
2
5V_REG
J33
14
LABEL J32.1 "VDD5V"
LABEL J32.2 "GND"
13
5-146261-1
3
2
1
LABEL J33.3 "5V_VBUS"
LABEL J33.2 "VDD5V"
LABEL J33.1 "5V_REG"
C113
5V_SW
R189
12
L14
0.1µF
0
SH-J33
TSW-103-07-G-S
SH-J41
J41
5V_LDO
C114
100µF
5V_REG
C115
47µF
5V_SW
C116
10µF
11
7440650047
4.7µH
C117
0.1µF
10
9
8
R187
124k
22.1k
5V_LDO
GND
VCC
VIN
3
VREG5
SW2
4
SS
DNP
SW1
1
2
C118
3300pF
TPS54225PWP
TSW-103-07-G-S
ZZ10
Assembly Note
Place SH-J41 on pin 2 and 3
R114
DNP
3.24k
J16
100k
7
EN
U4
1
R193
6
PG
PGND1
R112
10.0k
5
GND
PGND2
VDD_EXT
2
VFB
VBST
LABEL J16.1 "5V_REG_EN"
LABEL J16.2 "GND"
C119
1µF
NC
5
IN
3
5-146261-1
COMM
OUT
4
TL750MXX-Q1
GND
R132
0.51
J46
5-146261-1
VDD_EXT
GND
EN
2
GND
SH-J16
C9
22µF
GND
R153
1.5k
1
U10_VIN2
J62
J63
U10_VBIAS
U10_VEN
U10_VEN1
3
B
SH-J48
1
2
VDD5V
J48
5-146261-1
6091
U10_VIN
C120
1µF
VDD_EXT
1
2
12V_IN_B4JUMP
C121
0.1µF
10.0k
R154
1
D8
1N5819HW-7-F
40V
3
2
C124
22µF
C125
2.2µF
C126
0.1µF
1
U10_VBIAS2
PJ-102A
GND
1v1_TPS R196
TP10 100k
R156
U10_VEN1
10.0k
3
R159
3.24k
2
3
4
U10_VEN
5
0
R198
C127
4.7µF
GND
TP7
U10
TPS74701DRC
1
TESTPOINT
U10_VBIAS
R157
3.24k
IN
OUT
C
GND
IN
OUT
PG
FB
BIAS
SS
EN
C129
0.1µF
GND
ZZ13
Assembly Note
Place SH-J49
R197
1.87k
C122
0.1µF
C123
10µF
1
2
3
J35
1
2
1V1_LM
TSW-103-07-G-S
GND
R199 GND
4.99k
C128
0.01µF
R158 0
VDD33
U12
R160 0
3
R192
DNP
0
GND
2
C51
10µF
1
VDD5V
TP12
R200
LABEL J24.1 "VDD5V"
LABEL J24.2 "GND"TP13
R163
100k
0
5-146261-1
7
C52
1µF
GND
IN
OUT
EN
ADJ
SS
TAB
BIAS
GND
GND
6
R161
C49
150pF 1.65k
5
GND
4
R162
1.37k
LP38851S-ADJ
C53
10pF
R164
DNP
3.24k
1
2
C130
4.7µF
GND
5-146261-1
C131
0.1µF
0
11
12
1IN
1IN
2IN
2IN
4
10
R206
GND
C134
4.7µF
C135
0.1µF
NC
NC
NC
NC
NC
NC
NC
J39
1
2
LABEL J39.1 "VDD1V8"
LABEL J39.2 "GND"
5-146261-1
TP17
GND
TESTPOINT
VDD33
16
19
20
21
25
26
27
C137
10µF
VDD1V8 VDD_I2C
1
2
J37 SH-J37
LABEL J42.1 "VDD33"
LABEL J42.2 "GND"
5-146261-1
1
2
3
LABEL J37.1 "VDD33"
LABEL J37.2 "VDD_I2C"
LABEL J37.3 "VDD1V8"
D
TSW-103-07-G-S
GND
GND
TPS767D318PWP
3
VDD33
J42
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
2
ZZ22
Assembly Note
Place SH-J37 on pin 2 and 3
R207
0
C136
0.1µF
NC
NC
NC
NC
NC
NC
NC
C133
10µF
100k
U11B
1
2
7
8
13
14
15
D
VDD1V8
R205
29
3
9
EP
1GND
2GND
1EN
2EN
C132
0.1µF
TP15
28
22
TPS767D318PWP
0
GND
GND
0
17
18
2OUT
2OUT
1RESET
2RESET
TP16
R204
23
24
1OUT
1OUT
C
GND
GND
TESTPOINT
U11A
5
6
C50
10µF
8
TP14
R203
VDD5V
ZZ17
Assembly Note
Place SH-J60 on pin 1 and 2
1
2
3
5-146261-1
6
VBIAS
1
2
LABEL J26.1 "1V1_LM"
LABEL J26.2 "VDD11"
LABEL J26.3 "1V1_TPS"
ZZ16
Assembly Note
Place SH-J26 on pin 1 and 2
J60 SH-J60
VBIAS
LABEL J35.1 "VDD11"
LABEL J35.2 "GND"
7
J49
1
B
TSW-103-07-G-S
0
9
8
J24
SH-J49
1V1_LM
1V1_TPS
GND
6092
VDD11
R195
10
J64
5-146278-3
J68
SH-J46
ZZ15
Assembly Note
Place SH-J46
5-146261-1
1V1_TPS
GND
J26 SH-J26
5-146261-1
J36
R133
3.24k
5-146278-3
LABEL J22.1 "TPS74701 IN"
LABEL J22.2 "GND"
GND
TP9
LABEL J36 "12V_EXT"
10.0k
LABEL J34.1 "5V_SW_EN"
LABEL J34.2 "GND"
J22
1
2
PWPD
J69
5-146278-3
R155
3.0k
1
2DNP
11
J47
5-146261-1
GND
J34
R194
1
2
3
A
1
VOUT
15
3
2
1
LABEL J41.3 "5V_LDO"
LABEL J41.2 "5V_REG"
LABEL J33.1 "5V_SW"
R188
U9
PWPD
A
2
1
TP5
4
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
5
Mod. Date: 11/24/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title:
Sheet: 9 of 10
Assembly Variant: 001
File: SV601153A_Power.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
EVM PCB Schematics
43
Appendix A
www.ti.com
1
2
3
4
5
6
A
A
GND
C20
0.01µF
R1
GND
C21
10µF
C23
0.1µF U3
1
VDD33 VDD5V
C5
10µF
L1
L7
C29
10µF
C7
0.1µF
C45
10µF
C46
0.1µF
2
GND
3
330 ohm
4
330 ohm
C43
10µF
B
5
GND
6
7
VREF
AGND
VINR
VINL
VCC
FMT
VDD
MD1
DGND
MD0
SCKI
LRCK
DOUT
BCK
14
100
13
R2
12
FMT
11
MD1
10
MD0
100
GND
C24
1µF
C8
1
3
2
J1
SJ-3523-SMT
1µF
C31
0.01µF
9
B
GND
8
PCM1808PW
GND
4
Y1
ECS-8FA3X-122.8-TR
R3
J2
0
2
1
C14
0.1µF
R8
10.0k
TRI-STATE
OUTPUT
DAOUT
VDD33
R7
3
0
BCK
R9
2
5-146261-1
1
VDD
GND
C47
10µF
0
LRCK
R4
R5
R6
10.0k 10.0k 10.0k
R10
0
SCKIN
3
2
1
GND
FMT
MD1
MD0
4
5
6
J3
TSW-103-07-G-S
C
3
2
1
ZZ5
Assembly Note
S1: Connect 1 and 6, 2 and 5, 3 and 4
S1A
S1B
S1C
219-3LPST
219-3LPST
219-3LPST
C
Label SW3: MDO
Label SW2: D1
Label SW1: FMT
GND
D
D
Number: SV601153
Rev: A
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Not in version control
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: Tran Dam
1
44
EVM PCB Schematics
2
3
4
5
Mod. Date: 11/24/2014
Designed for: Public Release
Project Title: DS90UB947-Q1EVM FPD-Link III Serializer Evaluation Board
Sheet Title:
Sheet: 10 of 10
Assembly Variant: 001
File: SV601153A_Audio_IF.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2014
6
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Appendix B
SNLU140A – November 2014 – Revised August 2015
Board Layout
SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
EVM PCB Schematics
45
Appendix B
46
Board Layout
www.ti.com
SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Appendix B
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SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Board Layout
47
Appendix B
48
Board Layout
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SNLU140A – November 2014 – Revised August 2015
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Appendix B
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SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Board Layout
49
Appendix B
50
Board Layout
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SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Appendix B
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SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Board Layout
51
Appendix B
52
Board Layout
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Copyright © 2014–2015, Texas Instruments Incorporated
Appendix B
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SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Board Layout
53
Revision History
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Revision History
Changes from Original (November 2014) to A Revision ................................................................................................ Page
•
•
•
Changed Title to DS90Ux947-Q1EVM User's Guide ................................................................................. 5
Changed DS90UB or DS90UH to DS90ux throughout document. ................................................................. 5
Changed rows in Table 2-1 ............................................................................................................. 29
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
54
Revision History
SNLU140A – November 2014 – Revised August 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
spacer
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Copyright © 2015, Texas Instruments Incorporated
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