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Texas Instruments DS125BR820EVM User guides
DS125BR820EVM Evaluation Board
User's Guide
Literature Number: SNLU166
August 2014
Contents
1
Overview ............................................................................................................................. 4
1.1
1.2
1.3
Features ....................................................................................................................... 4
Applications ................................................................................................................... 4
Ordering Information ........................................................................................................ 4
2
4-Level IO Control ................................................................................................................ 6
3
DS125BR820EVM Configuration Overview .............................................................................. 8
3.1
Quick Start Guide ............................................................................................................ 9
4
Bill of Materials .................................................................................................................. 12
5
Schematic
6
......................................................................................................................... 13
EVM Layout ....................................................................................................................... 14
2
Contents
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List of Figures
1-1.
DS125BR820EVM Front .................................................................................................... 5
1-2.
DS125BR820EVM Back .................................................................................................... 5
2-1.
Switch Orientation for User Configuration ................................................................................ 6
5-1.
Schematic
6-1.
Top Assembly Layer ....................................................................................................... 14
6-2.
Bottom Assembly Layer ................................................................................................... 15
..................................................................................................................
13
List of Tables
........................................................................................................
1-1.
Ordering Information
2-1.
Description of 4-Level Voltage Inputs ..................................................................................... 6
2-2.
Switch Configuration
3-1.
Description of Connections ................................................................................................. 8
3-2.
Description of Switch Configuration and Settings ....................................................................... 8
3-3.
SMA Channel Connections ............................................................................................... 10
3-4.
EQA and EQB Settings Available in Pin Mode ......................................................................... 10
3-5.
VOD Output Settings available in Pin Mode ............................................................................ 11
4-1.
Bill of Materials
........................................................................................................
.............................................................................................................
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List of Figures
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4
7
12
3
Chapter 1
SNLU166 – August 2014
Overview
The DS125BR820EVM – SMA evaluation kit provides a complete high bandwidth platform to evaluate the
40GbE, PCIe, and SAS/SATA signal conditioning features of the Texas Instruments DS125BR820
repeater/redriver. The DS125BR820EVM can be used for standard compliance testing, performance
evaluation, and initial system prototyping. The SMA edge launch connectors used for the
DS125BR820EVM will interface to multiple system connector types via commercially available breakout
cables, adaptors, and boards (not included). This flexible connectivity enables integrated system level
testing between TI repeaters and 3rd party ASIC/FPGA host boards. For a functional description of the
DS125BR820, refer to the DS125BR820 datasheet.
1.1
Features
•
•
•
•
•
•
•
•
•
•
1.2
Applications
•
•
1.3
8-Channel unidirectional repeater operating at rates up to 12.5 Gbps
Linear equalization to support link training protocols
EQ up to 10 dB at 6 GHz
Variable voltage range up to 1200 mVpp
Linear output driver
Programmable by pin selection (pin mode), EEPROM, or SMBus interface
Single supply operation: VIN = 3.3 V±10% or VDD = 2.5 V±5%
–40°C to +85°C operation
4 kV HBM ESD rating / 1 kV CDM ESD rating
High speed signal flow–thru pin-out package: 54-pin QFN (10 mm x 5.5 mm, 0.5 mm pitch)
FR-4 Backplane traces and high speed cable in serial Interfaces up to 12.5 Gbps
PCIe, SAS, SATA, 40G-KR4, 40G-CR4, 40G-SR4, 40G-LR4
Ordering Information
Table 1-1. Ordering Information
4
EVM ID
DEVICE ID
DEVICE PACKAGE
DS125BR820EVM
DS125BR820NJY
WQFN-54
Overview
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Figure 1-1. DS125BR820EVM Front
Figure 1-2. DS125BR820EVM Back
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Overview
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5
Chapter 2
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4-Level IO Control
The channel settings and controls are configurable in pin mode for the DS125BR820 via four logic levels
(0, R, F, 1). The four logic levels correspond to the following voltages in Table 2-1.
Table 2-1. Description of 4-Level Voltage Inputs
Level
Internal Pin Voltage (3.3 V
Mode)
Setting
Internal Pin Voltage (2.5 V
Mode)
0
Tie 1kΩ to GND
0.10 V
0.08 V
R
Tie 20kΩ to GND
1/3 x VIN
1/3 x VDD
F
Float (leave pin open)
2/3 x VIN
2/3 x VDD
1
Tie 1kΩ to VIN or VDD
VIN – 0.05 V
VDD – 0.04 V
Typical 4-level input thresholds:
• Internal threshold between 0 and R = 0.2 * VIN or VDD
• Internal threshold between R and F = 0.5 * VIN or VDD
• Internal threshold between F and 1 = 0.8 * VIN or VDD
To set these 4-level voltage inputs, each input is controlled by a group of three switches in accordance
with Figure 2-1. These switches are located on the back of the EVM. For switch modules that come in a
set of six (such as SW3), switches 6-5-4 control one setting, and switches 3-2-1 control another.
ON
1
2
3
4
5
6
{
{
OFF
VODA0
VODA1
Figure 2-1. Switch Orientation for User Configuration
NOTE: The switches on the back of the EVM physically display the switch numbers in ascending
order, as shown from the example in Figure 2-1. However, conventional notation of switch
settings are typically given in descending order. Therefore, switch configurations for the
EVM will appear in descending order for the rest of this User's Guide as a result of this
notation convention.
The following switches are used to set the input condition for 4-level inputs: SW1, SW2, SW3, SW5, SW6,
SW8, and SW9.
The switch configurations for each of the 4-level inputs are shown in Table 2-2. Note the notation in
descending order.
6
4-Level IO Control
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Table 2-2. Switch Configuration
4-Level Input
Setting
Switch Settings (3-2-1 or 6-5-4)
ON
0
Tie 1kΩ to GND
OFF
3
(6
2
5
1
4)
ON-OFF-OFF
ON
R
Tie 20kΩ to GND
OFF
3
(6
2
5
1
4)
OFF-ON-OFF
ON
F
Float (leave pin open)
OFF
3
(6
2
5
1
4)
OFF-OFF-OFF
ON
1
Tie 1kΩ to VIN or VDD
OFF
3
(6
2
5
1
4)
OFF-OFF-ON
NOTE: Since each 4-level input setting is controlled by a set of three adjacent switches, only one of
the three switches can be in the ON position at any time.
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Chapter 3
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DS125BR820EVM Configuration Overview
The following tables describe the various connectors and user-controllable settings available on the
DS125BR820EVM. Since the device can operate in one of three modes (pin mode, SMBus slave mode,
and SMBus master mode), note the switch description that matches the intended mode of operation. For
more information about specific EQ, VOD, and SD_TH values, see the DS125BR820 datasheet.
Table 3-1. Description of Connections
Component
Name
J1, J2
J3, J4
J5, J6
J7, J8
IN_B2+,
IN_B3+,
IN_A0+,
IN_A1+,
J9, J10
J11, J12
J13, J14
J15, J16
OUT_B2+,
OUT_B3+,
OUT_A0+,
OUT_A1+,
Function
IN_B2IN_B3IN_A0IN_A1-
High-speed differential input pairs
OUT_B2OUT_B3OUT_A0OUT_A1-
High-speed differential output pairs
J17
SDA, SCL
Optional SMBus access pins. See
datasheet for additional information on
SMBus.
J18
EEPROM
EEPROM slot for operation in master
mode (optional)
J19
PWR
VIN (3.3 V) or VDD (2.5 V) for DC power
VIH_SEL
Tie VIN (3.3 V) or VDD (2.5 V) to VIH power
(jumper required)
J20
Table 3-2. Description of Switch Configuration and Settings
Component
Switch No.
6-5-4
[Pin and SMBus modes] AD2: ADDR[2]
Note: In Pin mode, this must be tied to GND (6-5-4 = ON-OFF-OFF)
3-2-1
[Pin mode] EQB: 4-level EQ setting for B-Channels
[SMBus modes] AD3: ADDR[3]
3-2-1
ENSMB: Enable SMBus modes
3-2-1 = ON-OFF-OFF for pin mode
3-2-1 = OFF-OFF-ON for SMBus slave mode
3-2-1 = OFF-OFF-OFF for SMBus master mode (load configuration from
EEPROM)
6-5-4
[Pin mode] VODA1: VOD Control [1] for A-Channels
[SMBus modes] Set all switches to OFF. VOD is controlled individually via
registers.
3-2-1
[Pin mode] VODA0: VOD Control [0] for A-Channels
[SMBus modes] Set all switches to OFF. VOD is controlled individually via
registers.
SW1
SW2
SW3
8
Name and Description
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Table 3-2. Description of Switch Configuration and Settings (continued)
Component
Switch No.
2
SCL
ON for SMBus modes
OFF for Pin mode
1
SDA
ON for SMBus modes
OFF for Pin mode
SW4
6-5-4
[Pin mode] VODB1: VOD Control [1] for B-Channels
[SMBus modes] AD1: ADDR[1]
3-2-1
[Pin mode] VODB0: VOD Control [0] for B-Channels
[SMBus modes] AD0: ADDR[0]
6-5-4
[Pin and SMBus modes] LPBK-RES (RES1): Reserved
Note: Set all switches to OFF for normal operation.
3-2-1
[Pin and SMBus slave mode] SD_TH: Signal detect assert/de-assert
Threshold level for signal detect monitor
[SMBus master mode] READ_EN: See description of Read Enable button
on SW10.
SW5
SW6
2
RESET/PWDN
ON to enable device
OFF to disable device
1
VDD_SEL
ON for 3.3 V mode
OFF for 2.5 V mode
SW7
6-5-4
[Pin and SMBus modes] RES3: Reserved
Note: In Pin mode, this must be tied to GND (6-5-4 = ON-OFF-OFF)
3-2-1
[Pin mode] EQA: 4-level EQ settings for A-Channels
[SMBus modes] Set all switches to OFF. EQA is controlled individually via
registers.
6-5-4
[Pin and SMBus modes] RES2: Reserved
Note: Set all switches to OFF for normal operation.
3-2-1
[Pin and SMBus modes] RX_DET: Enable or disable the internal 50Ω to
VDD Input Termination. See datasheet for more information.
SW8
SW9
SW10
3.1
Name and Description
N/A
[SMBus master mode] READ_EN: Enable load from external EEPROM in
master mode
SW6: SD_TH (3-2-1) becomes the READ_EN pin.
To start the loading at power up, set SW6 pin 3 to ON (pull to GND).
To control the start manually, set SW6 pin 1 to ON (pull to VDD) and push
the SW10 button for the high-to-low transition to start the loading. When
loading is complete, the LED – D1 will turn off.
Quick Start Guide
1. Connect J19: VIN = 3.3 V or VDD = 2.5 V and GND.
• For VIN = 3.3 V: Set SW7 pin1 (VDD_SEL) to the ON position (enable internal LDO regulator) and
float VDD at J19.
• For VIN = 2.5 V: Set SW7 pin1 (VDD_SEL) to the OFF positions (disable internal LDO regulator)
and float VIN at J19.
2. Set Jumper J20 for VIH connection to VIN or VDD.
• For 3.3 V mode: VIH tied to VIN (see Figure 1-1)
• For 2.5 V mode: VIH tied to VDD (see Figure 1-1)
3. Set the control switches for normal operation:
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• SW6 – SD_TH = F (default signal detect threshold level): Set switches (3-2-1) = (OFF-OFF-OFF).
• SW6 – LPBK-RES = F (normal operation): Set switches (6-5-4) = (OFF-OFF-OFF).
• SW7 – RESET = 0 (enables the device): Set switch pin 2 to the ON position.
• SW9 – RX_DET = F (enables RX detection): Set switches (3-2-1) = (OFF-OFF-OFF).
• SW9 – RES2 = F (normal operation): Set switches (6-5-4) = (OFF-OFF-OFF).
4. Connect 50Ω SMA cables to the board depending on the desired input and output channels:
• The input signals J1 to J8 can be connected from a pattern generator.
• The output signals J9 to J16 can be connected to a scope.
Table 3-3. SMA Channel Connections
A/B Channels
B-Channels
A-Channels
5. Pin
•
•
•
•
Input Channel
Output Channel
J1: IN_B2+, J2: IN_B2-
J9: OUT_B2+, J10: OUT_B2-
J3: IN_B3+, J4: IN_B3-
J11: OUT_B3+, J12: OUT_B3-
J5: IN_A0+, J6: IN_A0-
J13: OUT_A0+, J14: OUT_A0-
J7: IN_A1+, J8: IN_A1-
J15: OUT_A1+, J16: OUT_A1-
Mode – Set the input equalization level:
Set ENSMB = 0 (1 kΩ to GND) by using SW2 (3-2-1) = (ON-OFF-OFF).
Set SW4 switches 1 and 2 to the OFF positions so the SMBus signals are disconnected.
Refer to Table 2-1 for information on 3-switch settings for the 4-level input.
[Example] Set EQA to Level 3: SW8 (3-2-1) = (OFF-OFF-OFF) = EQA = F
Table 3-4. EQA and EQB Settings Available in Pin Mode
EQUALIZATION BOOST RELATIVE TO DC
SW8 (3-2-1)
SW1 (3-2-1)
Level
EQA
EQB
dB at 1.5
GHz
dB at 2.5
GHz
dB at 4
GHz
dB at 5
GHz
dB at 6
GHz
3
2
1
1
0
ON
OFF
OFF
2.1
2.5
2.7
2.9
3.0
2
R
OFF
3
F
OFF
ON
OFF
4.0
5.1
6.4
6.8
7.4
OFF
OFF
5.5
7.0
8.3
8.6
4
1
OFF
OFF
8.9
ON
6.8
8.3
9.5
9.6
9.8
NOTE: For normal operation in pin mode, ensure that RES3 SW8 (6-5-4) = (ON-OFF-OFF) and
AD2 SW1 (6-5-4) = (ON-OFF-OFF).
6. Pin
•
•
•
•
10
mode: Set the output VOD level:
Set ENSMB = 0 (1 kΩ to GND) by using SW2 (3-2-1) = (ON-OFF-OFF).
Set SW4 switches 1 and 2 to the OFF positions so the SMBus signals are disconnected.
Refer to Table 2-1 for information on 3-switch settings for the 4-level input.
[Example] Set VODB[1:0] to Level 4: SW5 (6-5-4), (3-2-1) = (OFF-ON-OFF), (OFF-OFF-OFF) =
VODB[1:0] = R, F
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Table 3-5. VOD Output Settings available in Pin Mode
VOD GAIN RELATIVE TO VID = 1.2 VPP
SW3 (6-5-4), (3-2-1)
SW5 (6-5-4), (3-2-1)
Level
VODA[1:0]
VODB[1:0]
Input (VPP)
Output
(VPP)
6
5
4
3
2
1
1
0, 0
ON
OFF
OFF
ON
OFF
OFF
2
0, R
ON
OFF
OFF
OFF
ON
1.2
0.65
OFF
1.2
0.71
3
0, F
ON
OFF
OFF
OFF
OFF
ON
1.2
0.77
4
R, F
OFF
ON
OFF
OFF
OFF
OFF
1.2
0.83
5
F, R
OFF
OFF
OFF
OFF
ON
OFF
1.2
0.90
6
1, 0
OFF
OFF
ON
ON
OFF
OFF
1.2
1.00
NOTE: The DS125BR820 channels are designed to be linear, ideal for small to moderate levels
of input attenuation or when TX FIR transparency is critical to system operation. There
are two additional levels of VOD available in SMBus modes. Refer to the DS125BR820
datasheet for more information.
7. SMBus slave mode – Set the EQ, VOD, VOD_DB level:
• Set ENSMB = 1 (1 kΩ to VIH) by setting SW2 (3-2-1) = (OFF-OFF-ON).
• Set SW4 switches 1 and 2 to the ON position so the SMBUS signals are connected.
• Set SW3 switches 1 through 6 to the OFF position so they do not connect to the SDA and SCL
line.
• Set SW1 and SW5 to configure the AD[3:0] pins. AD[3:0]=0000 sets device slave address (+ write
bit) = 0xB0.
• Connect SDA, SCL and GND to J17.
• All EQ, VOD, and VOD_DB levels can be set via SMBus registers in accordance to the register
map in the DS125BR820 datasheet.
8. SMBus master mode – Set the EQ, VOD, VOD_DB level:
• Load a pre-programmed EEPROM in the J18 EEPROM slot. Note that the DS125BR820 can only
support EEPROM sizes ranging from 2K (256 Bytes) to 8K (1024 bytes). The EEPROM must also
be capable of an operating frequency up to 1 MHz.
• Set ENSMB = FLOAT by setting SW2 (3-2-1) = (OFF-OFF-OFF).
• Set SW4 switches 1 and 2 to the ON position so the SMBUS signals are connected.
• Set SW3 switches 1 through 6 to the OFF position so they do not connect to the SDA and SCL
line.
• Set SW1 and SW5 to configure the AD[3:0] pins. AD[3:0]=0000 sets device slave address (+ write
bit) = 0xB0.
• Set SW6 and SW10 in accordance to the desired EEPROM load behavior:
– To start loading EEPROM at power up, set SW6 pin 3 to ON (pull to GND).
– To control the start manually, set SW6 pin 1 to ON (pull to VDD) and push the SW10 button for
the high-to-low transition to start loading EEPROM.
• After a successful EEPROM load, the ALL_DONE pin on the DS125BR820 goes low and LED –
D1 turns off. Afterwards, the DS125BR820 releases control of the SDA/SCL line and all EQ, VOD,
and VOD_DB levels become controllable via SMBus slave registers in accordance to the SMBus
register map in the DS125BR820 datasheet.
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Chapter 4
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Bill of Materials
Table 4-1. Bill of Materials
Item
Qty
Reference
1
1
Manufacturer P/N
Description
PCB
SV601074
DS125BR820EVM PCB
CAP CER 10UF 6.3V 20% X5R 0603
2
1
C1
445-4112-6-ND
C1608X5R0J106M08
0AB
3
1
C2
445-8144-6-ND
CGJ3E2X7R0J105K0
80AA
CAP CER 1.0UF 6.3V X7R 10% 0603
4
5
C3, C4, C5, C6, C7
445-4711-1-ND
C0603X5R0J104M
CAP CER .10UF 6.3V X5R 0201
5
16
C11, C12, C13, C14,
C15, C16, C17, C18,
C19, C20, C21, C22,
C23, C24, C25, C26
587-2483-1-ND
LMK063BJ224MP-F
CAP CER .22UF 10V X5R 20% 0201
6
1
D1
511-1592-1-ND
SML-P12PTT86
LED GREEN 0.2MM 13MCD 0402 SMD
7
16
J1, J2, J3, J4, J5, J6,
J7, J8, J9, J10, J11,
J12, J13, J14, J15,
J16
J801-ND
142-0761-881
CONN JACK SMA 50 OHMS PC MOUNT
8
1
J17
WM6504-ND
22-28-4043
CONN HEADER 4POS .100 VERT GOLD
9
2
J19, J20
WM6503-ND
22-28-4033
CONN HEADER 3POS .100 VERT GOLD
10
1
J18
3M5473-ND
4808-3004-CP
SOCKET IC OPEN FRAME 8POS .3"
11
31
R1, R2, R3, R4, R8,
R11, R13, R14, R16,
R17, R19, R20, R22,
R23, R25, R26, R28,
R29, R31, R32, R34,
R35, R37, R38, R40,
R41, R43, R44, R46,
R47, R49
P1.00KLCT-ND
ERJ-2RKF1001X
RES 1.00K OHM 1/10W 1% 0402 SMD
12
1
R7
P220LCT-ND
ERJ-2RKF2200X
RES 220 OHM 1/10W 1% 0402 SMD
13
13
R12, R15, R18, R21,
R24, R27, R30, R33,
R36, R39, R42, R45,
R48
P20.0KLCT-ND
ERJ-2RKF2002X
RES 20.0K OHM 1/10W 1% 0402 SMD
14
2
R5, R6
P4.70KLCT-ND
ERJ-2RKF4701X
RES 4.70K OHM 1/10W 1% 0402 SMD
15
6
SW1, SW3, SW5,
SW6, SW8, SW9
CT2196MST-ND
219-6MST
SWITCH TAPE SEAL 6 POS SMD
16
1
SW2
CT2193MST-ND
219-3MST
SWITCH TAPE SEAL 3 POS SMD
17
2
SW4, SW7
CT2192MST-ND
219-2MST
SWITCH TAPE SEAL 2 POS SMD
18
1
SW10
P12225STB-ND
EVQ-21505R
SWITCH LT 6MM 160GF 5MM HEIGHT
19
1
U1
20
12
Digikey P/N
1
N/A
S9001-ND
DS125BR820NJY
BUFFER - REPEATER
SPC02SYAN
CONN JUMPER SHORTING GOLD
FLASH
Bill of Materials
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Chapter 5
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Schematic
Figure 5-1. Schematic
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Schematic
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Chapter 6
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EVM Layout
Figure 6-1 and Figure 6-2 show the DS125BR820EVM layout. The evaluation board uses switches to
control signal integrity settings. The DS125BR820EVM allows access to the inner four buffer repeater
channels while remaining both very compact and low power. The WQFN package offers an exposed
thermal pad to enhance electrical and thermal performance. This must be soldered to the copper landing
on the PWB.
Figure 6-1. Top Assembly Layer
14
EVM Layout
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Figure 6-2. Bottom Assembly Layer
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EVM Layout
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STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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