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Texas Instruments TLK10xL EVM User guides
User's Guide
SLLU200 – July 2014
TLK10xL EVM
This user guide details the characteristics, operation, and use of the Industrial Ethernet TLK10xLEVM
(EVM). The EVM enables Texas Instruments customers to quickly design and market systems using the
TLK105L, TLK106L, TLK105, and TLK106 devices. This document also includes schematic diagrams, a
printed-circuit board (PCB) layout, board assembly and board marking drawings, and a bill of materials
(BOM).
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Contents
Features .......................................................................................................................
Applications ...................................................................................................................
Description ....................................................................................................................
System Description ..........................................................................................................
Design Features .............................................................................................................
General Block Diagram .....................................................................................................
6.1
Power Supply Options .............................................................................................
6.2
Serial Management and MAC Interfaces ........................................................................
6.3
MDI modes ..........................................................................................................
6.4
LED Options .........................................................................................................
6.5
Bootstrap Options/Jumpers........................................................................................
6.6
Clock Options .......................................................................................................
Power Supply Modes ........................................................................................................
7.1
Default Configuration ...............................................................................................
Serial Management and MII/RMII Interfaces .............................................................................
8.1
Serial Management for Standalone TLK10xLEVM .............................................................
8.2
MII Interface .........................................................................................................
8.3
RMII Interface .......................................................................................................
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MDI Modes ................................................................................................................... 9
9.1
Default Configuration – Separate Magnetic and RJ45 Connector ........................................... 9
9.2
Fiber Transceiver Operation ..................................................................................... 10
9.3
Integrated Magnetic with RJ45 Connector ..................................................................... 11
Clock Options ............................................................................................................... 13
10.1 Default Configuration ............................................................................................. 13
10.2 25M OSC Configuration .......................................................................................... 14
10.3 External Clock Supplied to TLK10xL ........................................................................... 14
Schematic ................................................................................................................... 15
Layout ........................................................................................................................ 20
Board Assembly ............................................................................................................ 22
Board Marking (Silk) ....................................................................................................... 23
Bill of Materials ............................................................................................................. 24
List of Figures
1
General Block Diagram ..................................................................................................... 5
2
MDIO/MDC Interface Block Diagram ...................................................................................... 7
3
MII Interface Block Diagram ................................................................................................ 8
4
RMII Interface Block Diagram .............................................................................................. 9
5
Separate Magnetic with RJ45 Block Diagram .......................................................................... 10
6
Optic Transceiver Block Diagram ........................................................................................ 11
7
Integrated Magnetic with RJ45 Block Diagram ......................................................................... 12
8
Transformer-Less Operation Block Diagram
13
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25M OSC Modifications
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...........................................................................
...................................................................................................
TLK10xL EVM Schematics (1 of 5) .....................................................................................
TLK10xL EVM Schematics (2 of 5) ......................................................................................
TLK10xL EVM Schematics (3 of 5) ......................................................................................
TLK10xL EVM Schematics (4 of 5) ......................................................................................
TLK10xL EVM Schematics (5 of 5) ......................................................................................
Layer 1 - Signal .............................................................................................................
Layer 2 - GND ..............................................................................................................
Layer 3 - Power.............................................................................................................
Layer 4 - Signal .............................................................................................................
Layer 1 – Components Side Assembly..................................................................................
Layer 4 – Print Side Assembly ...........................................................................................
Layer 1 – Components Side Silk .........................................................................................
Layer 4 – Print Side Silk ...................................................................................................
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List of Tables
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............................................................................................................. 24
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Design Features
2
Bill of Materials
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Features
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Features
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Applications
•
•
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TLK10xL reference design supporting TLK105L, TLK106L, TLK105, and TLK106
Low power consumption:
– Single supply < 275 mV
– Dual supply < 200 mW
Programmable power back off, reducing PHY power up to 20% in systems with shorter cables
Error-Free 100Base-T operation up to 150 meters under typical conditions
Error-free 10Base-T operation up to 300 meters under typical conditions
Variable I/O voltage range: 1.8 V to 3.3 V
Industrial networks and factory automation
Motor and motion control
Description
The Industrial Ethernet TLK10xLEVM enables TI customers to quickly design and market systems using
the TLK105L, TLK106L, TLK105, and TLK106 devices. Use a design similar to the EVM circuit to expedite
product development. TLK10xLEVM can be operated using only a single voltage (5-V DC jack, J82). On
default configurations, all other voltages are regulated on-board and internally produced.
The EVM kit contains:
• TLK10xLEVM unit
• Printed copy of this user's guide
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System Description
Effective and simple Ethernet design has made it the most popular networking solution at the physical and
data link levels. With high-speed options and a variety of media types to choose from, Ethernet is efficient
and flexible. These factors and the low cost of Ethernet hardware have made Ethernet an attractive option
for industrial networking applications. Also, the opportunity to use open protocols such as TCP/IP-overEthernet networks offers the possibility of a level of standardization and interoperability. The result has
been an ongoing shift toward the use of Ethernet for industrial control and automation applications.
Ethernet is increasingly replacing proprietary communications.
The TLK10xLEVM reference design enables TI customers to quickly design and release to market
systems using TI industrial Ethernet PHY transceiver devices. The TLK10xLEVM has been designed in a
small (2.6 in x 3.7 in) form factor which makes it easy to fit into any of the present products. The reference
design platform demonstrates the advanced performance of the TLK10xL Ethernet PHY transceiver
devices.
The design supports 10/100 Base-T and is compliant with the IEEE 802.3 standard. The reference design
operates from a single power supply (5 V with on-board regulator) or from a dual power supply (1.55 V
supplied from external source). On the single supply option, only the 5-V jack (J82) is connected (default
mode of operation), while all other voltages required for the Ethernet PHY transceiver are on-board
regulated and internally generated within the device.
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Design Features
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Design Features
Table 1 lists the design features of the EVM.
Table 1. Design Features
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Feature
Description
Ethernet PHY
The TLK10xL Ethernet PHY features:
• Industrial temperature rating: –40°C to +85°C (TLK106L and TLK106 support up to 105°C)
• Configurable PHY Addresses: jumper and resistor strapping options, supporting address space
00-31h (5 bits, default address 0x1)
• MII or RMII – jumper strapping option
Power consumption
Single Supply < 275 mW
Dual Supply < 200 mW
Power supply
The device is designed for power-supply flexibility and can operate with a single 3.3-V power
supply.
The following are the possible power input options:
• 5 V from external DC jack connector and on-board regulator to generate 3.3 V
• 3.3-V DC input through the serial connectors (J11/J13) and internally regulate the 1.55-V supply
• Both 3.3-V DC and 1.55-V DC supplied, through the serial connectors (J11/J13)
MAC - Controller interface
• 40-pin header allowing customers to plug their own MAC to the TLK10xLEVM using DC wires,
and using these as a MAC interface
• 2x 50 pin serial connectors to accommodate all MII/RMII interface signals
Clock
• 25-MHz crystal with internal oscillator (default)
• Operation with 25-MHz OSC
• External clock supported through pin 37 of J12 header
Status LEDs
Two LEDs (configured as PU or PD )
AFE supported
• Default operation, separate magnetic, Pulse HX1198FNL
• Integrated magnetic, Pulse J3011G21DNLT
• Transformer-less operation
• Fiber operation, Avago HFBR-58036AQZ
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General Block Diagram
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6
General Block Diagram
Figure 1 shows the general block diagram of the EVM.
Sled
5-V
Jack
3.3-V
Regulator
MII/
R
(som MII BU
S
e op
tions
)
3.3 V
INT
VOLTAGE
LEDs
1.55 V
MLED
1.55 V
LED LINK
25/50-MHz crystal or oscillator
TLK10xL
DUT
Boot Resistors/
Jumpers
RESET
Magnetics Pulse HX1198
RJ45
Figure 1. General Block Diagram
6.1
Power Supply Options
The TLK10xLEVM has several power supply options. The default option is feeding 5 V to the DC jack.
This option uses an on-board 3.3-V regulator and the TLK in single-supply mode. Another option is
feeding the TLK10xLEVM’s voltages through the serial connectors (J11/J13). In this mode, all voltages
can be supplied separately.
6.2
Serial Management and MAC Interfaces
The TLK10xLEVM supports a few options for serial management (MDIO/MDC) and for MII/RMII as MAC
Interfaces. The easiest option is to connect the MDIO/MDC pins (35/33 pins) on the 40-pin header (J12)
and one GND pin to an Ethernet MAC. This option allows read/write registers, activating force
transmission, and configuring loops to the TLK. Another option is to connect the entire MII interface to an
Ethernet MAC, allowing full testing of the TLK with a working system.
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General Block Diagram
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RMII interface to the MAC is also possible in the same way, but needs to share the 50M clock with the
MAC. Sharing a 50M clock is done by connecting the Ext 25/50M pin (pin 37) of the 40-pin header (J12)
to the same clock source of the MAC. Some modifications to the TLK10xLEVM are required in order to
share the 50M clock.
6.3
MDI modes
The TLK10xLEVM supports the following MDI options:
1. Default RJ45 with standalone magnetic (Pulse HX1198FNL)
2. RJ45 with integrated magnetic (Pulse J3011G21DNLT, not mounted)
3. Fiber transceiver operation (Avago HFBR-5803, not mounted)
4. Transformer-less operation
All modes are configured by connecting the required resistors and components to the TLK10xLEVM.
6.4
LED Options
The TLK10xL supports two LEDs, one of the LEDs as a configurable multi-LED. Operation of MLED (COL
pin) is configured using register writings. The TLK LEDs can operate as current source (when connected
to pull-down) or current sink (when connected to pull-up).
6.5
Bootstrap Options/Jumpers
Some TLK10xL configurations are made through bootstrap options; using selection with jumpers or using
resistors population.
The TLK10xLEVM can support the following jumper configurations:
• PHY_ID0
• PHY_ID1
• PHY_ID2
• AMDIX Disable
• MII/RMII Mode
• AN_0
The TLK10xLEVM can support the following resistor configurations:
• PHY_ID3
• PHY_ID4
• LED Mode
6.6
Clock Options
The TLK10xLEVM supports the following clock options:
• 25 MHz from crystal is the default configuration
• 25 MHz from OSC can be configured by board modifications
• External clock can be supplied by the 40-pin header (J12)
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Power Supply Modes
7.1
Default Configuration
When using default configuration, only 5 V should be connected to the TLK10xLEVM, allowing the onboard regulator to supply the required 3.3-V supplies to the TLK which is using its internal LDO to supply
1.55 V.
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Serial Management and MII/RMII Interfaces
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Serial Management and MII/RMII Interfaces
8.1
Serial Management for Standalone TLK10xLEVM
Minimal operation with the TLK10xLEVM would be to just connect MDIO/MDC and GND pins to a MAC
with MDIO/MDC capabilities. This allows the user to read/write registers and configure the TLK10xL to the
different loopback modes and activate the TLK10xL for basic testing.
This mode doesn’t allow full MII interface – transferring packets between the MAC and TLK10xL. For such
operation, connect all MII signals (see Section 8.2.1).
8.1.1
Serial Management – Block Diagram
For using the MDIO/MDC interface on the TLK10xLEVM, no changes are required. Simply connect pins
31 and 33 of J12 (40-pin header) to the MAC and one GND pin.
NOTE: For stable registers reading more than one GND connection should be shared between the
boards.
Sled
5-V
Jack
3.3-V
Regulator
MDIO
/MD
(3 w C and
G
ires
only ND
)
3.3 V
INT
VOLTAGE
LEDs
1.55 V
MLED
1.55 V
LED LINK
25/50-MHz crystal or oscillator
TLK10xL
DUT
Boot Resistors/
Jumpers
RESET
Magnetics Pulse HX1198
RJ45
Figure 2. MDIO/MDC Interface Block Diagram
8.2
8.2.1
MII Interface
MII Interface Connection for Standalone TLK10xLEVM
The TLK10xLEVM can be connected to any MAC system, by routing the MII signals to the 40-pin header
(J12). In this mode full system testing can be done with transferring packets between the MAC and the
TLK10xL.
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Serial Management and MII/RMII Interfaces
8.2.2
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MII Interface – Block Diagram
No changes are required to use the MII interface on the TLK10xLEVM with any MAC system. Simply
connect the relevant pins of J12 (40-pin header) to the MAC and GND pins.
NOTE: For operation, more than one GND connection should be shared between the boards.
&XVWRPHU¶V0$&
MII/RMII
BUS
M
II/RM
Sled
II
5-V
Jack
40-Pin Header
3.3-V
Regulator
BUS
MII/R
MII
3.3 V
INT
VOLTAGE
LEDs
1.55 V
MLED
1.55 V
LED LINK
25-MHz crystal or oscillator
TLK10xL
DUT
Boot Resistors/
Jumpers
RESET
Magnetics Pulse HX1198
RJ45
Figure 3. MII Interface Block Diagram
8.3
8.3.1
RMII Interface
RMII Interface Connection for Standalone TLK10xLEVM
The TLK10xLEVM can be connected to any MAC system, by routing the RMII signals to the 40-pin header
(J12). In this mode full system testing can be done, with transferring packets between the MAC and the
TLK10xL.
8.3.2
RMII Interface – Block Diagram
To use the RMII interface on the TLK10xLEVM with any MAC system, a few changes are required to route
shared clock to the TLK10xL:
• Connect 0R to R78
8
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MDI Modes
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•
•
Disconnect R71 and R72
Connect the shared 50M clock to the Ext 25/50M pin (pin 37) of the 40-pin header (J12) and to the
MAC.
Beside the previous changes, simply connect the relevant pins of J12 (40-pin header) to the MAC and
GND pins.
NOTE:
For operation, more than one GND connection should be shared between the boards.
Please also refer to the TLK105L, TLK106L datasheet (SLLSEE3) for RMII working mode
and requirements on the shared clock (50 MHz) and strap pin (RX_DV).
50-MHz oscillator
&XVWRPHU¶V0$&
MII/RMII
BUS
MII/R
Sled
MII
5-V
Jack
40-Pin Header
3.3-V
Regulator
BUS
MII/R
MII
3.3 V
INT
VOLTAGE
LEDs
1.55 V
MLED
1.55 V
Boot Resistors/
Jumpers
TLK10xL
DUT
LED LINK
RESET
Magnetics Pulse HX1198
RJ45
Figure 4. RMII Interface Block Diagram
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MDI Modes
9.1
Default Configuration – Separate Magnetic and RJ45 Connector
The TLK10xLEVM supports few MDI options. The default configuration is for the TLK10xL to use RJ45
with standalone magnetic (Pulse HX1198FNL).
For this working mode no changes are required to the TLK10xLEVM (default configuration).
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MDI Modes
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Sled
5-V
Jack
3.3-V
Regulator
MII/
R
(som MII BU
S
e op
tions
)
3.3 V
INT
VOLTAGE
LEDs
1.55 V
1.55 V
MLED
LED LINK
25/50-MHz crystal or oscillator
TLK10xL
DUT
Boot Resistors/
Jumpers
RESET
Magnetics Pulse HX1198
RJ45
Figure 5. Separate Magnetic with RJ45 Block Diagram
9.2
Fiber Transceiver Operation
The TLK10xL family of devices support Fiber mode. Please follow datasheet recommendations on how to
configure the TLK10xL for fiber mode. Please note that TTLK10x version (non-L) do not support fiber
mode.
Working with Fiber transceiver (Avago HFBR-5803, not mounted) is possible on the TLK10xLEVM.
The footprint for the Fiber transceiver option is found on the bottom of the TLK10xLEVM.
In order to work with integrated magnetic, the following modifications are required to the TLK10xLEVM:
• Connect 0R to the following resistors:
– R323, R324, R321, R322
• Connect 130R to the following resistors:
– R337, R339, R394, R396
• Connect 82R to the following resistors:
– R338, R340, R395, R397
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MDI Modes
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•
•
•
•
•
•
•
Connect 100 nF to the following capacitors:
– C17, C18, C251, C253, C254
Connect 10 nF to C231
Mount L14 and L15 with Ferrite-Bead 120R, 800 mA, 0805
Disconnect the following resistors:
– R112, R113, R114, R115 (0R)
– R11, R12 (49.9R)
Disconnect the following capacitors:
– C23, C24
U24 should be connected – Avago HFBR-5803 Fiber transceiver
Remove T1 (separate magnetic)
Sled
5-V
Jack
MII/R
(som MII BU
S
e op
tions
)
3.3-V
Regulator
3.3 V
INT
VOLTAGE
LEDs
1.55 V
MLED
1.55 V
TLK10xL
DUT
LED LINK
25/50 MHz crystal or oscillator
Boot Resistors/
Jumpers
RESET
Optic Transceiver
Figure 6. Optic Transceiver Block Diagram
9.3
Integrated Magnetic with RJ45 Connector
The TLK10xLEVM can operate using RJ45 with integrated magnetic (Pulse J3011G21DNLT, not
mounted). The footprint for the integrated magnetic option is found on the bottom of the TLK10xLEVM.
In order to work with integrated magnetic, the following modifications are required to the TLK10xLEVM:
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MDI Modes
•
•
•
•
•
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Connect 0R to the following resistors:
– R104, R81, R94, R95
– R107, R108, R109, R110
Connect 100 nF to the following capacitors:
– C11, C12
Disconnect the following resistors:
– R112, R113, R114, R115
– R101, R103, R34, R69
Connect J1 - Pulse J3011G21DNLT integrated magnetic
U2 (RJ45 connector) must be removed before trying to solder J1
Sled
5-V
Jack
3.3-V
Regulator
MII/R
(som MII BU
S
e op
tions
)
3.3 V
INT
VOLTAGE
LEDs
1.55 V
MLED
1.55 V
LED LINK
25/50-MHz crystal or oscillator
TLK10xL
DUT
Boot Resistors/
Jumpers
RESET
RJ45
With Integrated
Magnetic
Figure 7. Integrated Magnetic with RJ45 Block Diagram
9.3.1
Transformer-Less Operation
The TLK10xLEVM can support Transformer-Less operation, with no magnetic on the MDI path, but
capacitors instead. For more details on the Transformer-Less operation, please refer to the relevant
application note on the TLK10xL web-site (SLLA327).
In order to work in Transformer-Less mode, the following modifications are required to the TLK10xLEVM:
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Clock Options
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•
•
•
Connect 0R to the following resistors:
– R107, R108, R109, R110
Disconnect the following resistors:
– R112, R113, R114, R115
– R101, R103, R34, R69
Connect 33 nF to the following capacitors:
– C20, C21, C22, C27
Sled
5-V
Jack
3.3-V
Regulator
MII/
R
(som MII BU
S
e op
tions
)
3.3 V
INT
VOLTAGE
LEDs
1.55 V
1.55 V
MLED
LED LINK
25/50-MHz crystal or oscillator
TLK10xL
DUT
Boot Resistors/
Jumpers
RESET
RJ45
Figure 8. Transformer-Less Operation Block Diagram
10
Clock Options
10.1 Default Configuration
The TLK10xLEVM supports several clock options, with default configuration of 25 MHz from crystal. In this
mode an external crystal resonator connected across pins XI and XO.
The crystal must be 25-MHz ±50 ppm-tolerance crystal reference.
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Clock Options
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10.2 25M OSC Configuration
The TLK10xL can also operate with 25M external CMOS-level oscillator source connected to pin XI only.
Please refer to the datasheet for OSC requirement specifications.
In
•
•
•
order to operate with 25M OSC, the following modifications are required:
U5 OSC should be mounted – Epson, SG-211SCE (d) 25MHZ (footprint SMT 2 X 2.5)
0R should be mounted to R1 resistor location
Disconnect the following resistors: R71, R72
Figure 9. 25M OSC Modifications
10.3 External Clock Supplied to TLK10xL
External clock can be supplied to the TLK10xL by using the 40-pin header (J12). The external clock must
meet the TLK10xL datasheet requirements and to be within 25 MHz ±50ppm-tolerance.
The following changes are required to route the external clock to the TLK10xL:
• Connect 0R to R78
• Disconnect the following resistors: R71, R72
• External clock (25M/50M) should be connected to Ext 25/50M pin (pin 37) of the 40-pin header (J12)
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Schematic
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11
Schematic
Figure 10 through Figure 14 illustrate the TLK10xL schematics.
7
8
6
5
4
3
2
1
TOP
TLK CONFIGURATION
F
TLK10XL DUT
POWER SUPPLY
3V3
AVDD_3V3
IOVDD
RESET_N
3V3
POWER_SUPPLY
AVDD_3V3
IOVDD
3_3V_PS
COL
AVDD33
CRS
VDDIO
LED_LINK
RESET_N
25_50M_EXT
EMB_1V5_1
EMB_1V5_2
EXT_PWRDWN_CONTROL
MDC
MDIO
25M_50M_EXT
RDM_B
EMB_1V5_1
RDP_B
EMB_1V5_2
RXD0
EXT_PWRDWN
RXD1
RXD2
RXD3
TLK10XL_DUT
RX_CLK
E
RX_DV
RX_ER
ROOM=TLK111_DUT
TDM_A
TDP_A
TXD0
TXD1
TXD2
TXD3
TX_CLK
TX_EN
COL
CRS
LED_LINK
MDC
MDIO
RDM_B
RDP_B
RXD0
RXD1
RXD2
RXD3
RX_CLK
RX_DV
RX_ER
TDM_A
TDP_A
TXD0
TXD1
TXD2
TXD3
TX_CLK
TX_EN
COL
CRS
COL
LED_LINK
LED_LINK
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_ER
3V3
RXD0
F
CRS
TLK_CONFIGURATION_PINS
RXD1
RXD2
RXD3
RX_DV
RX_ER
ROOM=CONFIGURATIONS
3V3_PS
E
MAGNETICS
COL
LED_LINK
RDM_B
RDP_B
TDM_A
TDP_A
3V3
COL
LED_LINK
RDM_B
MAGNETICS_AFE
RDP_B
TDM_A
ROOM=MAG_DUT
TDP_A
3V3_CT_INPUT
D
D
ERM8-025-05.0-S-DV-TR
ERM8-025-05.0-S-DV-TR
IGNORE
IGNORE
1
2
RX_ER
RX_DV
CRS
COL
RXD0
RXD1
RXD2
RXD3
2
1
1
R24
33
1
R20
233
1
R27
2
33
R181
2
33
1
R25
332
1
R29
1
R31
1
R21
R281
2
0
233
C
RX_CLK
R22
EMB_MDIO
EMB_MDC
EMB_RESET_N
2
R73
A14
A16
A18
A20
A22
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
IOVDD_EMB
0
EMB_RX_CLK
233
EMB_RX_ERR
EMB_RX_DV
EMB_CRS
EMB_COL
EMB_RXD0
EMB_RXD1
EMB_RXD2
EMB_RXD3
233
2
33
233
AVDD_3V3
R23
1
0
IGNORE
2
3V3_AVDD_EMB
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
J11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
A23
1
A27
A07
A09
A11
A13
A15
A17
A19
A21
LED_LINK
R120 1
0 2
R102 IGNORE
R31
R171
R301
1
3V3_EMB
B08
B10
B12
B14
B16
B18
B20
B22
B24
25_50M_EXT
2
0
EMB_TXD3
EMB_TXD2
EMB_TXD1
EMB_TXD0
EMB_TX_EN
EMB_TX_CLK
R33
0
R21
233
1
R15
233
1
R26
2
33
EXT_PWRDWN_CONTROL
TXD3
TXD2
2 TXD1
33
TXD0
2 TX_EN
33
TX_CLK
2
33
1
3V3
ERM8-025-DV
3V3
P1
P3
P5
B
1
R78 0
F1
VIA
VIA
VIA
1
1
M203
VIA
M202
1
M201
1
M200
A
IGNORE
1
IGNORE
1
FID
FID
F3
IGNORE
1
FID
FID
FID
7
3V3_EMB
2
IGNORE
25_50M_H
33
35
37
39
P8
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
J12P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
FID
6
5
IOVDD
B07
B09
B11
B13
B15
B17
B19
B21
B23
1
B41
1
C
B27
B29
B31
B33
B35
B37
2 B39
R105 0 IGNORE 25_50M_EXT
R58
2
3V3_AVDD_EMB
0
AVDD_3V3
IGNORE
GND
TP30MIL19
TP30MIL
1
1
TP30MIL21
TP30MIL
1
1
34
36
38
40
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
IS EXPRESSLY FORBIDDEN.
COPYRIGHT (C) TI 2006
IGNORE
2
0
B
F6
1
R57
CONNECTOR_B
TEXAS
INSTRUMENTS
IGNORE
1
IOVDD_EMB
P6
P10
IGNORE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
ERM8-025-DV
DATE:
8
2
0
J13
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P4
P9
F5
1
R56
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
P2
P7
F4
1
F2
IGNORE
Header_2x20
CONNECTOR_A
25_50M_EXT
B28
B30
B32
B34
B36
B38
B40
B42
2
IGNORE
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
EMB_1V5_1
EMB_1V5_2
EMB_1V5_1
EMB_1V5_2
\1\
33
2
R191
1
\1\
R16
R90 0
MDIO
1
MDC
RESET_N
IOVDD
4
Wed May 21 19:13:34 2014
3
ASSY NAME:
TLK105LEVM
EDGE NUMBER: SV601037-001
ENGINEER:
PART NO:
REV: 1
PCB-53001
DRW PAGE:
DESIGN PAGE:
2
A
SADAN NOAM
1
OF 1
1
OF 5
1
Figure 10. TLK10xL EVM Schematics (1 of 5)
SLLU200 – July 2014
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5
C2
3 PF
1
1
2
IGNORE
1
IN
R94
12
11
3
5
4
7
6
8
12
9
10
2
IN
R95
2
11
0
C3
1
2
IN
2
R89
2
TDP_A
IN
1
2
1
C24
1 UF
2
1
R10
2
49.9
OPTIONAL
6
TDM_A
IN
RDP_B
IN
RDM_B
IN
8
2
1
IGNORE
9
10
C34
3 PF
2
IGNORE
1
L3
2
E
OPTIONAL
1
1
2
C25
100 NF
33 NH
OPTIONAL
IGNORE
IGNORE
1
RDP_BOT
C35
3 PF
OPTIONAL
1
TDM_BOT
R13
2
IGNORE
7
2
49.9
0
1
IGNORE
CT_INPUT
RDM_BOT
C23
100 NF
33 NH
5
4
R9
1
2
L2
OPTIONAL 3 PF
3
R81
330
IGNORE
E
2
IGNORE
1
J1
12
1
2
IGNORE
1
LED_LINK
1
2
IGNORE
1
C12
100 NF
C11
100 NF
0
OPTIONAL
1
IGNORE
1313
1414
COL
L1
1
2
33 NH
OPTIONAL
RJ45_INTEGRATED
CONNECTOR
J3011G21DNLT
IGNORE
1
3V3_CT_INPUT
F
CT_INPUT
R104
330
2
1
FOR INTEGRATED MAGNETIC OPERATION,
POPULATE ALL NON-OPTIONAL ITEMS ON THIS SECTION AND REMOVE U2 (RJ45)
CT_INPUT
3
MAGNETICS
INTEGRATED MAGNETIC
F
4
0
6
CT_INPUT
7
8
1
2
33 NH
TDP_BOT
1
IGNORE
IGNORE
2
2
R14
2
1
0
L4
2
R11
49.9
C26
1 UF
2
1
R12
2
49.9
OPTIONAL
TRANSFORMER-LESS
D
1
R107
IGNORE
0
1
R108
D
FOR TRANSFORMER-LESS OPERATION,
POPULATE R107-R110 AND C20-C22 AND C27, AND REMOVE R112-R115 AND R34, R69, R101, R103
2
IGNORE
2
0
1
0
R110
IGNORE
2
FIBER
2
FOR FIBER OPERATION, PLEASE REFER TO THE USER GUIDE
FOR COPPER OPERATION, DO NOT POPULATE ALL ITEMS ON THIS SECTION
0
T1
TDP_A_MAG
TX_P2
CHA
TX_P3
TDM_A_MAG
RDP_B_MAG
CHB
RDM_B_MAG
2
2
R396
130
130
R394
IGNORE
1
IGNORE
2
130
R339
1
1
\1\
1
VCC_PIN_6
IGNORE
2
FERRITE
VCC_PIN_5
BEAD
2
SD_PIN_4
RX_VEE_PIN_9
B
2
1
IGNORE
1
IGNORE
IGNORE
C254
100 NF
C253
100 NF
2
10 UF
IGNORE
1
2
C231
+
2
RD_PIN_2
TX_VEE_PIN_1
NRD_PIN_3
IGNORE
IGNORE
R111
1 M
1
C19
4700PF
C16
4700PF
2
2
1
TEXAS
INSTRUMENTS
1
IGNORE
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
IS EXPRESSLY FORBIDDEN.
COPYRIGHT (C) TI 2006
DATE:
7
L15
IGNORE
2
C8
10 NF
IGNORE
2
1
2
0
1
1
C15
1 UF
2
1
C14
100 NF
2
C10
1 UF
1
2
R322
IGNORE
8
BEAD
PLACE CAPACITORS,
INDUCTORS AND RESISTORS
CLOSE TO TRNACEIVER
2
2
A
NTD_PIN_7
2
FERRITE
L14
FXRD_M
FXRD_P
2 IGNORE
0
1
2
R8 75
2
R7 75
1
1
R321
2
1
2
R6 75
R5 75
1
C9
100 NF
RDM_B
1
1
\1\ 1
R32
0
MAGNETICS
C7
10 NF
FXTD_M
IGNORE1
RDP_B
B
100 NF
C18
1
RX_P8
HX1198FNL
IGNORE
IGNORE
1
RX_P9
0
C251
100 NF
RX_P7
RX_P10
R324
hfbr-5803
AFBR-5803AQZ
7
2
RX_P6
U24
TD_PIN_8
1
2
NC_P5
2
2
NC_P4
NC_P12
IGNORE
2
IGNORE
NC_P13
0
1
FIBER TRANSCEIVER
FXTD_P
1
IGNORE
TX_P14
RX_P11
R323
2
1
TX_P1
TX_P15
TDM_A
C17
100 NF
2 IGNORE
1
1
TX_P16
R69 0
TDP_A
C
R397 82
HX1198FNLT
1
2
2
1
1
0
R395 82
0
2
2
R101
2
R34
1
IGNORE
2
1
GND_PIN10
R103
1
2
3
4
5
6
7
8
R340 82
I/0_PIN1
I/0_PIN2
I/0_PIN3
I/0_PIN4
I/0_PIN5
I/0_PIN6
I/0_PIN7
I/0_PIN8
IGNORE
10
1-406541-1
GND_PIN9
R338 82
U2
9
2
2
RJ45_CONNECTOR
1
R335
49.9
R337
IGNORE
R328
49.9
IGNORE
1
IGNORE
130
CT_INPUT
CT_INPUT
1
2
2
0
0
1
R115
1
R114
2
0
R113
2
0
1
1
C
R112
IGNORE
1
IGNORE
0
2
2
C22
33 NF
IGNORE
2
C21
33 NF
1
1
IGNORE
C20
33 NF
C27
33 NF
1
IGNORE
2
1
R109
6
5
Tue May 27 14:19:04 2014
4
3
ASSY NAME:
TLK105LEVM
EDGE NUMBER: SV601037-001
ENGINEER:
PART NO:
DRW PAGE:
DESIGN PAGE:
2
A
SADAN NOAM
REV: 1
PCB-53001
1
OF 1
2
OF 5
1
Figure 11. TLK10xL EVM Schematics (2 of 5)
16
TLK10xL EVM
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7
8
6
5
4
3
2
1
CONFIGURATION PINS
F
F
1
3V3_PS
IN
R40
2.2 K
IGNORE
1
2
CFG_PHY_ID [4]
RXD3
IN
R41
2.2 K
IGNORE
\1\
2
CFG_PHY_ID [3]
RXD2
IN
J5
JUMPER
CFG_PHY_ID [2]
R37
RXD1
1
2
IN
\1\
2.2 K
J6
CFG_PHY_ID [1]
R38
1
2
RXD0
IN
JUMPER
E
E
2.2 K
1
R35
2
\1\
CFG_CROSSOVR
RX_ER
IN
2.2 K
\1\
J8
JUMPER
R36
J10
1
JUMPER
MII/RMII
RX_DV
IN
2
2.2 K
D
D
LED_MODE_CONFIGURATION
CRS
1
IN
R51
2.2 K
2
IGNORE
C
C
3V3_PS
3V3_PS
R44
1
2
COL
2
K
IN3
A
R45
1
LD2
2
3xjumper
CFG_ANEG_SPD_0
LED_LINK
IN
470
IN1
IN1
2.2 K
J3
J4
K
IN3
A
R49
1
LD4
2
470
IN2
IN
3xjumper
R48
1
2.2 K
CFG_PHY_ID [0]
MLED
1
R42
B
2
470
R43
1
IN2
B
A
K
1
LD3
R46
2
470
R47
2
1
2.2 K
A
K
LD5
2
2.2 K
TEXAS
INSTRUMENTS
A
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
IS EXPRESSLY FORBIDDEN.
COPYRIGHT (C) TI 2006
DATE:
8
7
6
5
Wed May 21 19:13:33 2014
4
3
TLK105LEVM
ASSY NAME:
EDGE NUMBER: SV601037-001
ENGINEER:
PART NO:
DRW PAGE:
DESIGN PAGE:
2
A
SADAN NOAM
REV: 1
PCB-53001
1
OF 1
3
OF 5
1
Figure 12. TLK10xL EVM Schematics (3 of 5)
SLLU200 – July 2014
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8
7
6
5
4
3
2
1
POWER SUPPLY
F
F
5V INPUT
5V_SUPPLY
DC_JACK 5V
E
E
J82
POWER_JACK_RAPC712X
5V_SUPPLY
+
1
R91
750
K
K
A
LD18
A
2
2
2
2
C183
220 UF
1
1
C182
100 PF
2
C90
1 NF
1
C89
10 NF
1
C82
10 UF
2
GND2
GND
1
VIN
D
D
3.3V_PS
3V3
LP3964_LDO
2
VIN
U4
VOUT
3
1
C
3V3
2
OUT
4
R4
2
402
1
R62
2
IOVDD
A
2
SENSE
OUT
0
K
C4
33 UF
SD
5
1
1
0
1
1
2
1
C1
68 UF
0
R88
LD1
2
GND
R59
2
1
10 K
5V_SUPPLY
R60
C
1
R63
2
AVDD_3V3
OUT
0
B
B
TEXAS
INSTRUMENTS
A
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
IS EXPRESSLY FORBIDDEN.
COPYRIGHT (C) TI 2006
DATE:
8
7
6
5
Wed May 21 19:13:33 2014
4
3
ASSY NAME:
TLK105LEVM
EDGE NUMBER: SV601037-001
ENGINEER:
PART NO:
DRW PAGE:
DESIGN PAGE:
2
A
SADAN NOAM
REV: 1
PCB-53001
1
OF 1
4
OF 5
1
Figure 13. TLK10xL EVM Schematics (4 of 5)
18
TLK10xL EVM
SLLU200 – July 2014
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4
3
2
TLK105L DUT
1
EMB_1V5_2
EMB_1V5_1
2
R80
2
0
R77
IN
IN
F
1
2
0
R106
1
PFBOUT
C13
3 PF
1
2
F
2
C55
100 NF
2
0
1
1
1
CLOSE TO PIN 18
PFBIN1
2
1
IN
R79
C54
100 NF
CLOSE TO PIN 37
PFBIN2
IGNORE
5
0
6
IGNORE
7
8
PFBOUT
EMB_1V5_1
EMB_1V5_2
IGNORE
2
1
C60
100 PF
2
1
2
C59
1 NF
1
2
1
C33
100 PF
2
2
C32
1 NF
1
C31
10 NF
1
OUT
OUT
OUT
OUT
OUT
OUT
LED_LINK
TDM_A
RDP_B
RD_N_BIDIR_P9
RDM_B
1
2
RXD_2/PHYAD3_OUTPUT_P32
TD_N_BIDIR_P11
RD_P_BIDIR_P10
RESET_N
RXD2
TDP_A
1
RXD_1/PHYAD2_OUTPUT_P31
TD_P_BIDIR_P12
C56
CLOSE TO PIN 24
IGNORE
R82
2.2 K
1
2
RXD_0/PHYAD1_OUTPUT_P30
RXD1
PFBIN1
JUMPER
J14
1
2
RXD0
TLK105L
AVDD33
VDD_PFBIN1_POWER_P13
TP30MIL
RBIAS
CLOSE TO PIN 15
1
COL/PHYAD0_OUTPUT_P29
AVDD33/AFE_TEST_POWER_P14
\1\
TP30MIL2
2
C53
100 NF
COL
PFBOUT
4.87 K
1
RX_ER/MDIX_EN_OUTPUT_P28
VDD_PFBOUT_POWER_P15
1
C52
CRS/CRS_DV/LED_CFC_OUTPUT_P27
RX_ER
R96
RBIAS
10 UF
CRS
RESETN_INPUT_P18
MIRX_DV/MII_MODE_OUTPUT_P26
XI_INPUT_P23
RX_DV
TLK105LRHB
RBIAS_POWER_P16
2
OUT
D
RX_CLK_OUTPUT_P25
VDDS_3P3V_POWER_P21
OUT
RX_CLK
XO_OUTPUT_P22
OUT
VDD_PFBIN2_POWER_P24
33 PF
MLED/AN_EN_OUTPUT_P17
17
RESET_N
MDC
MDIO
MDC_INPUT_P20
MDIO_BIDIR_P19
XTAL1 I261
XTAL
ATS250BSM-1E
1
C51
2
1
TLK105L
2
E
P2
PFBIN2
U1
C48
I273
P1
2
0
2
1 M
33 PF
10 UF
2
R72
1
R70
2
0
1
10 UF
1
VDDIO
2
1
R71
1
C58
10 NF
C57
C30
E
100 NF
D
OUT
OUT
POWER_PAD_POWER_P33
OUT
OUT
3_3V_PS
1
0
INTN_INPUT_P8
IGNORE
TXD_3_INPUT_P7
R68
4.7 K
OUT
2
TXD_2_INPUT_P6
ST_1
1
TXD_0_INPUT_P4
GND_2
R1
25M_REF
1
OUTPUT_3
TXD_1_INPUT_P5
U5
VDD_4
TXEN_INPUT_P3
25MHZ OSCILATOR
RXD_3/PHYAD4_OUTPUT_P1
OUT
TXCLK_OUTPUT_P2
3_3V_PS
SG-211SCE (D) 25MHZ-X1G0036210159XX
2
0
OUT
OUT
2
OUT
OUT
1
2
C41
100 PF
2
C40
1 NF
1
1
C39
10 NF
IGNORE
OUT
2
TX_CLK
3_3V_PS
TX_EN
C
TXD0
R75
2.2 K
TXD1
TXD2
TXD3
1
OUT
MDIO
RXD3
1
1
IN
2
OUT
2
0
C
R67
25M_50M_EXT
1
R66
R74
2.2 K
2
IGNORE
1
R117
0
R76
2.2 K
EXT_PWRDWN
2
IN
IGNORE
2
IGNORE
3_3V_PS
3_3V_PS
I241
2
I242
2
1
1
C29
100 PF
C28
1 NF
I240
2
C6
10 NF
1
1
I239
2
C5
10 UF
IN
TLK105L EVM - VERSION 001
TLK106L EVM - VERSION 002
B
VDDIO
VDDIO
I236
2
I237
2
1
1
C50
100 PF
C47
1 NF
I234
2
C45
10 NF
1
1
I233
2
C43
10 UF
IN
AVDD33
AVDD33
I231
2
I230
2
TEXAS
INSTRUMENTS
1
1
C49
100 PF
C46
1 NF
1
C44
10 NF
I229
2
1
I228
2
C42
10 UF
IN
A
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
IS EXPRESSLY FORBIDDEN.
COPYRIGHT (C) TI 2006
DATE:
8
B
7
6
5
Wed May 21 19:13:34 2014
4
3
ASSY NAME:
TLK105LEVM
EDGE NUMBER: SV601037-001
ENGINEER:
PART NO:
DRW PAGE:
DESIGN PAGE:
2
A
SADAN NOAM
REV: 1
PCB-53001
1
OF 1
5
OF 5
1
Figure 14. TLK10xL EVM Schematics (5 of 5)
SLLU200 – July 2014
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TLK10xL EVM
Copyright © 2014, Texas Instruments Incorporated
19
Layout
12
www.ti.com
Layout
Figure 15 through Figure 18 show the PCB layout drawings.
Figure 15. Layer 1 - Signal
Figure 16. Layer 2 - GND
20
TLK10xL EVM
SLLU200 – July 2014
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Copyright © 2014, Texas Instruments Incorporated
Layout
www.ti.com
Figure 17. Layer 3 - Power
Figure 18. Layer 4 - Signal
SLLU200 – July 2014
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TLK10xL EVM
Copyright © 2014, Texas Instruments Incorporated
21
Board Assembly
13
www.ti.com
Board Assembly
Figure 19 and Figure 20 show the board assembly drawings for this EVM.
F3
9
1
2
40
J12
P1
M203
2
10
1
M200
39
R31
R65
R64
R61
R55
C90
A
J82
C182
R18
C89
R21
U1
K
R29
R59
R79
C30
C183
R1
XTAL1
R60
C1
R78
R70
R105R102
R19
+
C31
C51
TP30MIL2
R16
R73
R5
R74
C57 C52
C13
C7
A K
C32
R90
R89
C47
C56
R77
R71
C45
R72
R96
C58
R6
LD1
R24
C33
C53
C59
LD18
R4
R51
C54
C60
C10
R13
R27
37
36
2425
R91
U4
C55
R107
C9
R99
R80
R106
R112R323
C23
1
C24
R103
C82
C2
R20
C20
C16
R28
R25
48
R9
R101
12
13
C27
16
2
L1
R40
R41
R108
R113R324
C43
C3
R10
R34
T1
C50
C34
L2
R11 R12
R69
L3
R109
C21
U2
1
R114R321
C22
8
7
C35
R32
R30
R17
R26
R2
R22
C49
L4
F1
R23
R110
R115R322
R120
R33
R3
R85
R87
R86
R83
C46
R84
C14
C25
C26
C44
R15
C42
R121
R117 R76
R75
TP30MIL21
C15
PCB EDGE
R14
R8
R98
R97
R7
C8
R119
C19
C4
C48
R63
C6
R50
R88
U5
1
R68
C40
R62
C41
C28
R54
C5
ALD7 K
R58
C29
ALD6 K
R52
R53
C39
R57
R67
R56
R37
R38
J14
R39
1
1
R35
R42
1
A
LD3 K
R36
R45
1
ALD2 K
R43
F2
R44
R66
J5
1
J7
1
J6
J8
1
1
J10
1
J4
M201
2
2
2
TP30MIL19
J15
R46
J3
A
LD5 K
1
R49
J9
A
LD4 K
R47
R48
R82
M202
Figure 19. Layer 1 – Components Side Assembly
F6
R111
R81
1
2
J11
49
50
J1
C12
F5
R95
F4
C231
R340
R339
1
R337
J13
R399
L15
49
50
C251
1
2
R398
R116
R338
C254
U24
L14
AREA
PLUG
PROCESS
R104
C11
C253
R397
R94
R396
R335 C18
R328 C17
9
R394
R395
Figure 20. Layer 4 – Print Side Assembly
22
TLK10xL EVM
SLLU200 – July 2014
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Copyright © 2014, Texas Instruments Incorporated
Board Marking (Silk)
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14
Board Marking (Silk)
Figure 21 and Figure 22 show the board markings (silk) for this EVM.
Figure 21. Layer 1 – Components Side Silk
Figure 22. Layer 4 – Print Side Silk
SLLU200 – July 2014
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TLK10xL EVM
Copyright © 2014, Texas Instruments Incorporated
23
Bill of Materials
15
www.ti.com
Bill of Materials
Table 2 lists the BOM for this EVM.
Table 2. Bill of Materials
S. #
Ref Des
Qty
1
!PCB
1
2
U5
1
SMT2X2_5
EPSON
SG-211SCE (d) 25MHZX1G0036210159xx
?
3
J3,J4
2
JUMPERX3
Samtec
TSW-103-07-G-S
?
CONN HEADER 3POS .100" T/H GOLD
SAM1029-03-ND
4
C52
1
C1210
Samsung
CL32A106KPINNNE
10 UF
CAP CER 10UF 10V 10% X5R 1210
1276-3311-2-ND
5
C2,C3,C13,C34,C35
5
C0603
Samsung
CL10C030BB8NNNC
3 PF
IGNORE
CAP CER 3PF 50V NPO 0603
1276-2125-2-ND
6
C20-C22,C27
4
C0603
KEMET
C0603C333J3RACTU
33 NF
IGNORE
CAP CER 33NF 25V 5% X7R 0603
399-9068-2-ND
7
C4
1
C1206
Nichicon
F930G336KAA
33 UF
CAP TANT 33UF 4V 10% 1206
489-8141-2-ND
8
C251,C253,C254
3
C0603
SAMSUNG
CL10B104KO8NNNC
100 NF
CAP CER 100NF 16V 10% X7R 0603
1276-1005-2-ND
9
C53-C55
3
C0603
SAMSUNG
CL10B104KO8NNNC
100 NF
CAP CER 100NF 16V 10% X7R 0603
1276-1005-2-ND
10
C5,C30,C42,C43,C57,C8
2
6
C1206
TDK
C3216X7R1V106M160AC
10 UF
CAP CER 10UF 35V 20% X7R 1206
4458034-2-ND
11
C90
1
C0603
SAMSUNG
CL10C102JB8NNNC
1 NF
CAP CER 1NF 50V 5% NPO 0603
1276-1091-2-ND
12
C89
1
C0603
SAMSUNG
CL10B103KB8NCNC
10 NF
CAP CER 10NF 50V 10% X7R 0603
1276-1921-2-ND
13
C1
1
C1206
Nichicon
F930J686KAA
68 UF
CAP TANT 68UF 6.3V 10% 1206
493-6546-2-ND
14
C16
1
C1812
AVX
1812GC472KAT1A
4700PF
CAP CER 4700PF 2KV 10% X7R 1812
478-3003-2-ND
15
C19
1
C1812
AVX
1812GC472KAT1A
4700PF
CAP CER 4700PF 2KV 10% X7R 1812
478-3003-2-ND
16
C48,C51
2
C0603
SAMSUNG
CL10C330FB8NNNC
33 PF
CAP CER 33PF 50V 1% NPO 0603
1276-2262-2-ND
17
C29,C33,C41,C49,C50,C
60,C182
7
C0402
Yageo
CC0402JRNPO9BN101
100 PF
CAP CER 100PF 50V 5% NPO 0402
311-1024-2-ND
18
C10,C15,C24,C26
4
C0603
Samsung
CL10B105KQ8NNNC
1 UF
CAP CER 1UF 6V3 10% X7R 0603
1276-1024-2-ND
19
C11,C12,C17,C18
4
C0402
SAMSUNG
CL05B104KP5NNNC
100 NF
CAP CER 0.1UF 10V 0.1% X7R 0402
1276-1002-2-ND
20
C9,C14,C23,C25
4
C0402
SAMSUNG
CL05B104KP5NNNC
100 NF
CAP CER 0.1UF 10V 0.1% X7R 0402
1276-1002-2-ND
21
C28,C32,C40,C46,C47,C
59
6
C0402
Kemet
C0402C102J3RACTU
1 NF
CAP CER 1NF 25V 5% X7R 0402
399-7752-2-ND
22
C6C8,C31,C39,C44,C45,C5
8
8
C0402
Kemet
C0402C103J5RACTU
10 NF
CAP CER 10NF 50V 5% X7R 0402
399-7758-2-ND
23
J1
1
CON_RJ45_J3011
Pulse
J3011G21DNL
?
IGNORE
RJ45 CAT5 8 POS RA Female with integrated
magnetic
553-1763-2-ND
24
L14,L15
2
L0805
Samsung
CIM21J121NE
120 OHM
IGNORE
FERRITE CHIP 120OHM 800MA 0805
1276-6333-2-ND
25
XTAL1
1
HC49SM_I
CTS
ATS250BSM-1E
?
CRYSTAL 25.0MHZ 18PF SMD
CTX1213CT-ND
26
J12
1
CON_SAMTEC_XXC020DFDNRC
?
TSW-120-07-G-D
?
20PINS DOUBLE ROW .100
SAM1028-20-ND
27
U24
1
CON_AGILENT_HFBR-5803-SC
Avago
HFBR-5803AQZ
?
Fast Ethernet Optical Transceiver
516-2346-ND
28
T1
1
SM16
PULSE
HX1198FNLT
?
10/100 BASE-T MAGNETICS
553-2209-2-ND
29
L1-L4
4
L0603
Bourns Inc.
CI160808-33NJ
33 NH
INDUCTOR MULTI LAYER CHIP 33NH
CI160808-33NJTR-ND
30
J5,J6,J8,J10,J14
5
JMP02
SAMTEC
TSW-102-07-G-S
?
CONN HEADER 2POS 0.100" SGL GOLD
SAM1029-02-ND
31
LD1-LD5,LD18
6
LED0805
Everlight
QTLP630C4TR
?
LED GREEN WATER CLR 08050 SMD T/R
1080-1411-2-ND
32
U4
1
SOT-223-5
TI
LP3964EMP-3.3/NOPBTR-ND
?
IC REG LDO 3.3 0.8A SOT223-5
LP3964EMP-3.3/NOPBTR-ND
24
JEDEC Type
Vendor
Vendor Part Number
Value
BOM Ignore
SV601037-001
DESCRIPTION
Digi-key Number
TLK10xLEVM
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
TLK10xL EVM
3.3V CMOS SMD OSCILLATOR WITH
STANDBY, 25MHz, 20ppm -40-+85
SLLU200 – July 2014
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Copyright © 2014, Texas Instruments Incorporated
Bill of Materials
www.ti.com
Table 2. Bill of Materials (continued)
S. #
Ref Des
Qty
JEDEC Type
Vendor
Vendor Part Number
Value
BOM Ignore
DESCRIPTION
Digi-key Number
33
C231
1
C6032
VISHAY SPRAGUE
293D106X9025C2TE3
10 UF
IGNORE
CAP TANT 10UF 25V 10% 2312
718-1050-2-ND
34
C183
1
7343
Kemet
T491D227K006AT
220 UF
CAP TANT 220UF 6V3 10% 2917
399-8378-2-ND
35
J82
1
CON3
SWITCHCRAFT
RAPC712X
?
CONN POWERJACK MINI R/A PCMT
SC237-ND
36
R60
1
R0603
Samsung ElectroMechanics America,
Inc
RC1608J103CS
10 K
RES 10K OHM 1/10W 5% 0603
1276-5086-2-ND
37
R117
1
R0402
YAGEO
RC0402JR-070R
0
RES 0.0 OHM 1/16W JUMP 0402 SMD
311-0.0JRTR-ND
38
R73,R90,R120
3
R0402
YAGEO
RC0402JR-070R
0
RES 0.0 OHM 1/16W JUMP 0402 SMD
311-0.0JRTR-ND
39
R1,R22,R23,R32,R33,R5
6R58,R67,R77,R78,R80,R
94,R95,R102,R105,R107R110,R321-R324
24
R0603
Yageo
RC0603JR-070RL
0
RES 0.0 OHM 1/10W JUMP 0603 SMD
311-0.0GRTR-ND
40
R13,R14,R34,R59,R62,R
63,R66,R69,R71,R72,R7
9,R88,R89,R101,R103,R
106,R112-R115
20
R0603
Yageo
RC0603JR-070RL
0
RES 0.0 OHM 1/10W JUMP 0603 SMD
311-0.0GRTR-ND
41
R2,R3,R15-R21,R24-R31
17
R0402
YAGEO
RC0402FR-0733RL
33
RES 33.0 OHM 1/16W 1% 0402 SMD
311-33.0LRTR-ND
42
R5-R8
4
R0603
YAGEO
RC0603FR-0775RL
75
RES 75.0 OHM 1/10W 1% 0603 SMD
311-75.0HRTR-ND
43
R338,R340,R395,R397
4
R0603
YAGEO
RC0603FR-0782RL
82
IGNORE
RES 82.0 OHM 1/10W 1% 0603 SMD
311-82.0HRTR-ND
44
R337,R339,R394,R396
4
R0603
YAGEO
RC0603FR-07130RL
130
IGNORE
RES 130 OHM 1/10W 1% 0603 SMD
311-7130HRTR-ND
45
R4
1
R0603
YAGEO
RC0603FR-07402RL
402
RES 402 OHM 1/10W 1% 0603 SMD
311-402HRTR-ND
46
R42,R45,R46,R49
4
R0603
YAGEO
RC0603FR-07470RL
470
RES 470 OHM 1/10W 1% 0603 SMD
311-470HRTR-ND
47
R91
1
R0603
YAGEO
RC0603FR-07750RL
750
RES 750 OHM 1/10W 1% 0603 SMD
311-750HRTR-ND
48
R9-R12
4
R0402
YAGEO
RC0402FR-0749R9L
49.9
RES 49.9 OHM 1/16W 1% 0402 SMD
311-49.9LRTR-ND
49
R328,R335
2
R0402
YAGEO
RC0402FR-0749R9L
49.9
IGNORE
RES 49.9 OHM 1/16W 1% 0402 SMD
311-49.9LRTR-ND
50
R81,R104
2
R0603
Samsung ElectroMechanics America,
Inc.
RC1608J331CS
330
IGNORE
RES 330 OHM 1/10W 5% 0603
1276-5050-2-ND
51
R35R38,R43,R44,R47,R48,R
74,R75,R82
11
R0402
YAGEO
RC0402FR-072K2L
2.2 K
RES 2.20K OHM 1/16W 1% 0402 SMD
311-2.20KLRTR-ND
52
R40,R41,R51,R76
4
R0402
YAGEO
RC0402FR-072K2L
2.2 K
RES 2.20K OHM 1/16W 1% 0402 SMD
311-2.20KLRTR-ND
53
R96
1
R0603
Yageo
RC0603FR-074K87L
4.87 K
RES 4.87K OHM 1/10W 1% 0603 SMD
311-4.87KHRTR-ND
54
R68
1
R0603
BOURNS
CR0603-JW-472GLF
4.7 K
RES 4.7K OHM 1/10W 5% 0603 SMD
CR0603-JW-472GLFTR-ND
55
R111
1
R0402
YAGEO
RC0402FR-071ML
1M
RES 1.00M OHM 1/16W 1% 0402 SMD
311-1.0MLRTR-ND
56
R70
1
R0402
YAGEO
RC0402FR-071ML
1M
RES 1.00M OHM 1/16W 1% 0402 SMD
311-1.0MLRTR-ND
57
U2
1
CON_RJ45_TE_1-406541-1
TE Connectivity
1-406541-1
?
CONN MOD JACK R/A 8P8C SHIELDED
A97716-ND
58
J11,J13
2
CON_SAMTEC_ERM8-05-S-DVTR
Samtec
ERM8-025-05.0-S-DV-TR
?
Connector, 2x50 way Plug 0.8mm board to board
socket strip, Male
59
U1
1
QFN50P500X500X100-33
TI
TLK105LRHB
?
IC TXRX IND ETHERNET PHY 32QFN
60
TP30MIL19,TP30MIL21
2
TH
SAMTEC
HMTSW-101-07-TM-S-240
?
61
TP30MIL2
1
TH
SAMTEC
HMTSW-101-07-TM-S-240
?
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
SLLU200 – July 2014
Submit Documentation Feedback
TESTPOINT_TH_0.9mm_pad_1.7MM
HMTSW-101-07-TM-S-240-ND
TESTPOINT_TH_0.9mm_pad_1.7MM
HMTSW-101-07-TM-S-240-ND
TLK10xL EVM
Copyright © 2014, Texas Instruments Incorporated
25
ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR
EVALUATION MODULES
Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user
expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following:
1.
User agrees and acknowledges that EVMs are intended to be handled and used for feasibility evaluation only in laboratory and/or
development environments. Notwithstanding the foregoing, in certain instances, TI makes certain EVMs available to users that do not
handle and use EVMs solely for feasibility evaluation only in laboratory and/or development environments, but may use EVMs in a
hobbyist environment. All EVMs made available to hobbyist users are FCC certified, as applicable. Hobbyist users acknowledge, agree,
and shall comply with all applicable terms, conditions, warnings, and restrictions in this document and are subject to the disclaimer and
indemnity provisions included in this document.
2. Unless otherwise indicated, EVMs are not finished products and not intended for consumer use. EVMs are intended solely for use by
technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical
mechanical components, systems, and subsystems.
3. User agrees that EVMs shall not be used as, or incorporated into, all or any part of a finished product.
4. User agrees and acknowledges that certain EVMs may not be designed or manufactured by TI.
5. User must read the user's guide and all other documentation accompanying EVMs, including without limitation any warning or
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contact TI.
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General Statement for EVMs Not Including a Radio
For EVMs not including a radio and not subject to the U.S. Federal Communications Commission (FCC) or Industry Canada (IC)
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General Statement for EVMs including a radio
User Power/Frequency Use Obligations: For EVMs including a radio, the radio included in such EVMs is intended for development and/or
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For EVMs Annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
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environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at its own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
Industry Canada Compliance (English)
For EVMs Annotated as IC – INDUSTRY CANADA Compliant:
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs Including Radio Transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs Including Detachable Antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Canada Industry Canada Compliance (French)
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
spacer
Important Notice for Users of EVMs Considered “Radio Frequency Products” in Japan
EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan.
If user uses EVMs in Japan, user is required by Radio Law of Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use EVMs only after user obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or
Use of EVMs only after user obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect
to EVMs. Also, do not transfer EVMs, unless user gives the same notice above to the transferee. Please note that if user does not
follow the instructions above, user will be subject to penalties of Radio Law of Japan.
http://www.tij.co.jp
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品の
ご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
http://www.tij.co.jp
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
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www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
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www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
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