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Texas Instruments DS90Ux940-EVM User guides
DS90UH940-Q1EVM User's Guide
User's Guide
Literature Number: SNLU162
October 2014
Contents
1
DS90UH940-Q1EVM User's Guide
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
.......................................................................................... 5
General Description ......................................................................................................... 5
Features ....................................................................................................................... 5
System Requirements ....................................................................................................... 6
Contents of the Demo Evaluation Kit ..................................................................................... 6
Applications Diagram ........................................................................................................ 6
Typical Configuration ........................................................................................................ 7
Quick Start Guide ............................................................................................................ 8
Demo Board Connections .................................................................................................. 9
ALP Software Setup ....................................................................................................... 12
1.9.1 System Requirements ............................................................................................ 12
1.9.2 Download Contents ............................................................................................... 12
1.9.3 Installation of the ALP Software ................................................................................. 12
1.9.4 Installation of the Device Profiles ............................................................................... 12
1.9.5 Startup - Software Description ................................................................................... 12
1.9.6 Information Tab .................................................................................................... 14
1.9.7 Pattern Generator Tab ............................................................................................ 14
1.9.8 Registers Tab ...................................................................................................... 15
1.9.9 Registers Tab - Address 0x00 selected ........................................................................ 16
1.9.10 Registers Tab - Address 0x00 expanded ..................................................................... 16
1.9.11 Scripting Tab ...................................................................................................... 18
Troubleshooting ALP Software ........................................................................................... 19
1.10.1 ALP Loads the Incorrect Profile ................................................................................ 19
1.10.2 ALP does not detect the EVM .................................................................................. 21
Typical Connection and Test Equipment ................................................................................ 23
Termination Device ........................................................................................................ 23
Equipment References .................................................................................................... 24
Cable References .......................................................................................................... 24
2
Bill of Materials .................................................................................................................. 25
A
EVM PCB Schematics ......................................................................................................... 29
B
Board Layout ..................................................................................................................... 36
2
Contents
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List of Figures
1-1.
Applications Diagram ........................................................................................................ 6
1-2.
Typical Configuration ........................................................................................................ 7
1-3.
Interfacing to the EVM
1-4.
Launching ALP
1-5.
1-6.
1-7.
1-8.
1-9.
1-10.
1-11.
1-12.
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
1-19.
1-20.
1-21.
1-22.
1
2
3
4
5
6
...................................................................................................... 8
............................................................................................................. 13
Initial ALP Screen .......................................................................................................... 13
Follow-up Screen ........................................................................................................... 14
ALP Information Tab ....................................................................................................... 14
ALP Pattern Generator Tab ............................................................................................... 15
ALP Registers Tab ......................................................................................................... 15
ALP Device ID Selected ................................................................................................... 16
ALP Device ID Expanded ................................................................................................. 17
ALP Scripting Tab .......................................................................................................... 18
USB2ANY Setup ........................................................................................................... 19
Remove Incorrect Profile .................................................................................................. 19
Add Correct Profile ......................................................................................................... 20
Finish Setup ................................................................................................................. 20
ALP No Devices Error ..................................................................................................... 21
Windows 7, ALP USB Driver ............................................................................................. 21
ALP in Demo Mode ........................................................................................................ 22
ALP Preferences Menu .................................................................................................... 22
Typical Test Setup for Video Application ................................................................................ 23
Typical Test Setup for Evaluation ........................................................................................ 23
Top Layer.................................................................................................................... 36
Ground Layer ............................................................................................................... 36
Power Layer................................................................................................................. 36
Bottom Layer ................................................................................................................ 36
Top Silkscreen .............................................................................................................. 37
Bottom Silkscreen .......................................................................................................... 37
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List of Figures
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3
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List of Tables
1-1.
Power Supply................................................................................................................. 9
1-2.
MIPI CSI-2 Output Signals J15 and J16 .................................................................................. 9
1-3.
FPD-Link III Input Signals
1-4.
USB2ANY Connector ...................................................................................................... 10
1-5.
I2C/CCI Interface Header J13 ............................................................................................ 10
1-6.
GPIO/Audio Interface Header J17 ....................................................................................... 10
1-7.
SPI/D_GPIO Interface Header J14
1-8.
1-9.
1-10.
4
..................................................................................................
......................................................................................
CMLOUT Output Signals ..................................................................................................
Mode_Sel0 SW-DIP8 - S1 ...............................................................................................
Mode_Sel1 SW-DIP8 - S2 ...............................................................................................
List of Tables
9
10
10
10
11
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Chapter 1
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DS90UH940-Q1EVM User's Guide
1.1
General Description
The Texas Instruments DS90Ux940-Q1EVM evaluation module (EVM) converts FPD-Link III to MIPI CSI2. This kit will demonstrate the functionality and operation of the DS90UH940-Q1/DS90UB940-Q1. The
DS90UH940-Q1 supports HDCP content protection but otherwise is the same as DS90UB940-Q1. The
information provided in this document can be applied to both devices. The DS90Ux940-Q1 is a FPD-Link
III Deserializer which, in conjunction with the DS90Ux949/929/947-Q1 Serializers, it recovers the data
from one or two FPD-Link III serial streams and converts into a Camera Serial Interface (CSI-2) format
compatible with Mobile Industry Processor Interface (MIPI) specifications. It supports video resolutions up
to WUXGA and 1080p60 with 24-bit color depth.
The recovered data is packetized and serialized over four CSI-2 data lanes strobed by a half-rate serial
clock compliant with the MIPI DPHY / CSI-2 specifications, each lane running up to 1.3 Gbps. The CSI-2
output serial bus greatly reduces the interconnect and signal count to a graphic processing unit (GPU) and
eases system designs for video streams from multiple automotive driver assist cameras.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including
GPIOs, I2C and SPI communication, over the same differential link. In backward compatible mode, the
device supports up to WXGA and 720p60 resolutions with 24-bit color depth over a single differential link.
The device supports up to 7.1 audio channels. Audio data received from the FPD-Link III stream is
decrypted and regenerated up to 8-channel I2S interface with maximum bit rate of 192 kHz.
NOTE: The demo board is not intended for EMI testing. The demo board was designed for easy
accessibility to device pins with tap points for monitoring or applying signals, additional pads
for termination, and multiple connector options.
1.2
Features
•
•
•
•
•
•
•
•
•
•
•
Supports Pixel Clock Frequency up to 170 MHz for WUXGA (1920x1200) and 1080p60 resolutions
with 24-bit Color Depth
2 lane FPD-Link III interface with De-skew capability
Support MIPI DPHY
– Support MIPI DPHY
– Support up to 4 data lanes per CSI-2 port, each lane up to 1.3Gbps
Capable to recover data up to 15 meters 50Ω Coaxial or Differential Shielded Twisted-Pair (STP) cable
Backwards Compatible to DS90Ux925Q/925AQ and DS90Ux927Q FPD-Link III Serializers
Adaptive equalization
@Speed BIST and reporting pin
Supports 7.1 multiple I2S (4 data) channels
Single +12V power supply for EVM
1.8V or 3.3V compatible LVCMOS I/O interface
Automotive grade product: AEC-Q100 Grade 2 qualified
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System Requirements
1.3
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System Requirements
In order to demonstrate, the following is required:
1. FPD-Link III compatible Serializer
(a) DS90Ux949-Q1, DS90Ux947-Q1 up to 1080p60
(b) DS90Ux929-Q1, DS90Ux925Q/925AQ, DS90Ux927Q up to 720p60
2. Video source
3. Optional I2C controller
4. Power supply for 12V @ 1A (required)
1.4
Contents of the Demo Evaluation Kit
1. One EVM board with the DS90Ux940-Q1
1.5
Applications Diagram
HDMI
or
DP++
VDDIO
(1.8V)
1.8V
1.1V
3.3V
1.2V
VDDIO
(3.3V / 1.8V)
FPD-Link III
2 Lane
MIPI
CSI-2
D0+/-
IN_CLK-/+
Mobile
Device
or
Graphics
Processor
IN_D0-/+
DOUT0+
RIN0+
DOUT0-
RIN0-
DOUT1+
RIN1+
DOUT1-
RIN1-
D1+/D2+/-
IN_D1-/+
IN_D2-/+
CEC
DDC
HPD
DS90Ux949-Q1
Serializer
I2C
IDx
D_GPIO
(SPI)
D3+/CLK+/-
DS90Ux940-Q1
Deserializer
Application
Processor
I2C
IDx
D_GPIO
(SPI)
Figure 1-1. Applications Diagram
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Typical Configuration
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1.6
Typical Configuration
Video Processor Board
(Video Data + Ctrl + PCLK)
FPD-Link III
Serializer
Video
Processor
(I2C)
Dual FPD-LINK III
Cluster, Head Unit
(MIPI CSI-2)
DS90Ux940
Application
Processor
Display
(I2C)
Figure 1-2. Typical Configuration
Figure 1-1 and Figure 1-2 illustrate the use of the chipset in a display application.
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Quick Start Guide
1.7
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Quick Start Guide
1.
2.
3.
4.
5.
Connect mini USB J10 to USB port for register programming (optional)
Configure switches S1, S2, S3 and S4 to set device’s operating modes
Connect J1 (RIN0+/- and RIN1+/-) to 1 lane or 2 lane FPD-Link III serial bit stream
Connect MIPI CSI-2 output signals (J16 or J15) to application processor
Provide power to board on J18 (12V)
(a) Optional +1.2VDC power supply on JP8, +1.8VDC power supply on JP9 and +3.3VDC power
supply on JP10
6. For details of pin-names and pin-functions, please refer to the DS90Ux940-Q1 datasheet.
JP8-10 f
(Optional)
J18 f
12V
+5%
J10 j
1.2V
+5%
c FPD-LINK III INPUTS
d LVCMOS I/O
e FUNCTION CONTROLS
f POWER SUPPLY
1.8V
+5%
3.3V
+5%
g MIPI CSI-2 OUTPUTS
hJ13
h I2C/CCI BUS
i CMLOUT OUTPUTS
j USB CONNECTOR
J3, J4c
(Optional)
J1c
g J15, J16
J8, J9 c
(Optional)
dJ14 J17
J5, J6 i
eS1, S2, S3, S4
Figure 1-3. Interfacing to the EVM
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Demo Board Connections
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1.8
Demo Board Connections
Table 1-1. Power Supply
Reference
Signal
Description
J18
+12V
12V ±5% Main Power
Single +12V power connector that supplies power to the entire board.
JP8 (Optional)
+1.2V
1.2V ±5%
Alternative to Main Power
JP9 (Optional)
+1.8V
1.8V ±5%
Alternative to Main Power
JP10 (Optional)
+3.3V
3.3V ±5%
Alternative to Main Power
Table 1-2. MIPI CSI-2 Output Signals J15 and J16
Reference
Port
Signal
J15.2
CSI1_D3+
J15.3
CSI1_D3-
J15.6
CSI1_D2+
J15.7
CSI1_D2-
J15.10
CSI1_D1+
CSI-2 Port 1
J15.11
CSI1_D1-
J15.14
CSI1_D0+
J15.15
CSI1_D0-
J15.18
CSI1_CLK+
J15.19
CSI1_CLK-
J16.2
CSI0_D3+
J16.3
CSI0_D3-
J16.6
CSI0_D2+
J16.7
CSI0_D2-
J16.10
CSI0_D1+
CSI-2 Port 0
J16.11
CSI0_D1-
J16.14
CSI0_D0+
J16.15
CSI0_D0-
J16.18
CSI0_CLK+
J16.19
CSI0_CLK-
NOTE: The CSI-2 signals are labeled on the back side silkscreen text of PCB board.
Table 1-3. FPD-Link III Input Signals
Reference
Signal
Description
J1
RIN0+/RIN1+/-
HSD connector
J3 (Optional)
RIN0+
SMA connector
J4 (Optional)
RIN0-
SMA connector
J8 (Optional)
RIN1+
SMA connector
J9 (Optional)
RIN1-
SMA connector
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Demo Board Connections
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Table 1-4. USB2ANY Connector
Reference
Description
J10
mini USB 5 pin
Table 1-5. I2C/CCI Interface Header J13
Reference
Signal
J13.1
VDDI2C
J13.2
SCL
J13.3
SDA
J13.4
GND
Table 1-6. GPIO/Audio Interface Header J17
Reference
Signal
J17.2
SDOUT/GPIO0
Description
Aux I2S Data Output / Remote or Local I/O
J17.4
SWC/GPIO1
J17.6
I2S_DC/GPIO2
Aux I2S Word Clock Output / Remote or Local I/O
I2S Data Output / Remote or Local I/O
J17.8
I2S_DD/GPIO3
I2S Data Output / Remote or Local I/O
J17.10
VDDIO
GPIO Voltage Level 1.8V or 3.3V
J17.12
I2S_DB/GPIO5
I2S Data Output / Local only I/O
J17.14
I2S_DA/GPIO6
I2S Data Output / Local only I/O
J17.16
I2S_WC/GPIO7
I2S Word Clock Output/ Local only I/O
J17.18
I2S_CLK_GPIO8
I2S Clock Output / Local only I/O
J17.20
MCLK
I2S System Clock Output
Table 1-7. SPI/D_GPIO Interface Header J14
Reference
Signal
Description
J14.2
BISTEN
J14.4
BISTC
BIST Clock Select (Shared with S3)
J14.6
VDDIO
GPIO Voltage Level 1.8V or 3.3V
BIST Enable Pin (Shared with S3)
J14.8
D_GPIO3/SS
I/O in 2 lane FPD-Link III mode / Slave Select
J14.10
D_GPIO2/SCLK
I/O in 2 lane FPD-Link III mode / Serial Clock
J14.12
D_GPIO1/MISO
I/O in 2 lane FPD-Link III mode / Master In, Slave Out
J14.14
D_GPIO0/MOSI
I/O in 2 lane FPD-Link III mode / Master Out, Slave In
Table 1-8. CMLOUT Output Signals
Reference
Signal
Description
J5
CMLOUT+
SMA connector
J6
CMLOUT-
SMA connector
Table 1-9. Mode_Sel0 SW-DIP8 - S1 (1)
Reference
(1)
10
Mode
CSI LANE
REPLICATE
Output Mode
S1.1 (Default)
1
0
0
4 data lanes, 1 CSI port active
(determined by MODE_SEL1 CSI_SEL bit)
S1.2
2
0
1
4 data lanes, both CSI ports active
(overrides MODE_SEL1 CSI_SEL bit)
Only set one ON.
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Table 1-9. Mode_Sel0 SW-DIP8 - S1 (1) (continued)
Reference
Mode
CSI LANE
REPLICATE
Output Mode
S1.3
3
1
0
2 data lanes, 1 CSI port active
(determined by MODE_SEL1 CSI_SEL bit)
S1.4
4
1
1
2 data lanes, both CSI port active
(overrides MODE_SEL1)
S1.5
N/A
N/A
N/A
RESERVED
S1.6
N/A
N/A
N/A
RESERVED
S1.7
N/A
N/A
N/A
RESERVED
S1.8
N/A
N/A
N/A
RESERVED
Table 1-10. Mode_Sel1 SW-DIP8 - S2 (1)
Reference
CSI_SEL
MODE
High Speed Back
Channel
Input Mode
S1.1
(Default)
0
00
5 Mbps
STP
S1.2
0
01
5 Mbps
Coax
S1.3
0
10
20 Mbps
STP
S1.4
0
11
20 Mbps
Coax
S1.5
1
00
5 Mbps
STP
S1.6
1
01
5 Mbps
Coax
S1.7
1
10
20 Mbps
STP
S1.8
1
11
20 Mbps
Coax
(1)
Only set one ON.
IDx SW-DIP8 - S4 (1)
(1)
Reference
7-bit Address
S1.1 (Default)
0x2C
8-bit Address
0x58
S1.2
0x2E
0x5C
S1.3
0x30
0x60
S1.4
0x32
0x64
S1.5
0x34
0x68
S1.6
0x36
0x6C
S1.7
0x38
0x70
S1.8
0x3C
0x78
Only set one ON.
BISTEN/PDN Setting SW-DIP3 - S3
Reference
(1)
Signal
(1)
Input = L
Input = H
Description
Normal operating mode. BIST
is disabled. (Default)
BIST Mode is enabled.
BIST Enable Input
S3.1
BISTEN
S3.2
BISTC
External Pixel Clock (Default)
Internal Pixel Clock (~50MHz)
BIST Clock Select
S3.3
PDB
Power Down (DIsabled)
Operational (Default)
Power Down Mode Input
Before BIST can be enabled, the 940 D_GPIO[0] has to be strapped high and D_GPIO[3:1] strapped low on J14.
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ALP Software Setup
1.9
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ALP Software Setup
1.9.1 System Requirements
Operating System:
USB:
USB2ANY Firmware Version:
Windows 7 64-bit
USB2ANY
2.5.2.0
1.9.2 Download Contents
TI Analog LaunchPAD can be downloaded from: http://www.ti.com/tool/alp.
Download and extract the “snlc048.zip” file to a temporary location that can be deleted later.
Make sure J10 on the DS90Ux940-Q1 is connected to a PC USB port with USB cable and power is
applied to the DS90Ux940-Q1 EVM.
The following installation instructions are for the Windows 7 64-bit Operating System.
1.9.3 Installation of the ALP Software
Execute the ALP Setup Wizard program called “ALPF_setup_v_x_x_x.exe” that was extracted to a
temporary location on the local drive of your PC.
There are 7 steps to the installation once the setup wizard is started:
1. Select the "Next" button.
2. Select “I accept the agreement” and then select the “Next” button.
3. Select the location to install the ALP software and then select the “Next” button.
4. Select the location for the start menu shortcut and then select the “Next” button.
5. There will then be a screen that allows the creation of a desktop icon. After selecting the desired
choices select the “Next” button.
6. Select the “Install” button, and the software will then be installed to the selected location.
7. Uncheck “Launch Analog LaunchPAD” and select the “Finish” button. The ALP software will start if
“Launch Analog LaunchPAD” is checked, but it will not be useful until the USB driver is installed and
board is attached.
Connect J10 USB jack of the DS90Ux940-Q1 EVM board to a PC/laptop USB port using a Type A
1
2
3
4
A to mini-B
1 2 3
4
MINI
USB cable. Power the DS90Ux940-Q1 EVM board with a 12 VDC
power supply. The “Found New Hardware Wizard” will open on the PC/laptop.
1.9.4 Installation of the Device Profiles
There are 2 steps to add the DS90Ux940 profile:
1. Contact TI for the DS90Ux940-Q1 profile
2. Extract the “DS90Ux940.zip” to ALP’s profile folder. The profile folder can be found at: C:\Program
Files (x64)\Texas Instruments\Analog LaunchPAD vx.x.x\Profiles\
1.9.5 Startup - Software Description
Make sure all the software has been installed and the hardware is powered on and connected to the PC.
Execute “Analog LaunchPAD” shortcut from the start menu. The default start menu location is under All
Programs > Texas Instruments > Analog LaunchPAD vx.x.x > Analog LaunchPAD to start MainGUI.exe.
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ALP Software Setup
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Figure 1-4. Launching ALP
The application should come up in the state shown in the figure below. If it does not, see Section 1.10,
“Troubleshooting ALP Software”.
Under the Devices tab click on “DS90Ux940_ENG” to select the device and open up the device profile and
its associated tabs.
Figure 1-5. Initial ALP Screen
After selecting the DS90Ux940, the following screen should appear.
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ALP Software Setup
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Figure 1-6. Follow-up Screen
1.9.6 Information Tab
The Information tab is shown below. Please note the device revision could be different.
Figure 1-7. ALP Information Tab
1.9.7 Pattern Generator Tab
The DES Pattern Generator tab is shown below.
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Figure 1-8. ALP Pattern Generator Tab
1.9.8 Registers Tab
The Register tab is shown below.
Figure 1-9. ALP Registers Tab
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ALP Software Setup
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1.9.9 Registers Tab - Address 0x00 selected
Address 0x00 selected as shown below. Note that the “Value:” box,
value of that register.
, will now show the hex
Figure 1-10. ALP Device ID Selected
1.9.10 Registers Tab - Address 0x00 expanded
By double clicking on the Address bar
or a single click on
can be expanded.
16
. Address 0x00 expanded reveals contents by bits. Any register address displayed
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Figure 1-11. ALP Device ID Expanded
Any RW Type register,
, can be written into by writing the hex value into the “Value:” box,
or putting the pointer into the individual register bit(s) box by a left mouse click to put a check mark
(indicating a “1”) or unchecking to remove the check mark (indicating a “0”). Click the “Apply” button to
write to the register, and “refresh” to see the new value of the selected (highlighted) register.
The box toggles on every mouse click.
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ALP Software Setup
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1.9.11 Scripting Tab
The Scripting tab is shown below.
Figure 1-12. ALP Scripting Tab
The script window provides a full Python scripting environment which can be for running scripts and
interacting with the device in an interactive or automated fashion.
WARNING
Directly interacting with devices either through register
modifications or calling device support library functions can effect
the performance and/or functionality of the user interface and may
even crash the ALP Framework application.
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1.10 Troubleshooting ALP Software
1.10.1 ALP Loads the Incorrect Profile
If ALP opens with the incorrect profile loaded the correct profile can be loaded from the
USB2ANY/Aardvark Setup found under the tools menu.
Figure 1-13. USB2ANY Setup
Highlight the incorrect profile in the Defined ALP Devices list and press the remove button.
Figure 1-14. Remove Incorrect Profile
Find the correct profile under the Select a Daughter Board list, highlight the profile and press Add.
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Troubleshooting ALP Software
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Figure 1-15. Add Correct Profile
Select Ok and the correct profile should now be loaded.
Figure 1-16. Finish Setup
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1.10.2 ALP does not detect the EVM
If the following window opens after starting the ALP software, double check the hardware setup.
Figure 1-17. ALP No Devices Error
It may also be that the USB driver is not installed. Check the device manager. There should be a “HIDcompliant device” under the “Human Interface Devices” as shown below.
Figure 1-18. Windows 7, ALP USB Driver
The software should start with only “DS90UH940_ENG” in the “Devices” pull down menu. If there are
more devices then the software is most likely in demo mode. When the ALP is operating in demo mode
there is a “(Demo Mode)” indication in the lower left of the application status bar as shown below.
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DS90UH940-Q1EVM User's Guide
Copyright © 2014, Texas Instruments Incorporated
21
Troubleshooting ALP Software
www.ti.com
Figure 1-19. ALP in Demo Mode
Disable the demo mode by selecting the “Preferences” pull down menu and un-checking “Enable Demo
Mode”.
Figure 1-20. ALP Preferences Menu
After demo mode is disabled, the ALP software will poll the ALP hardware. The ALP software will update
and have only “DS90UH940_ENG” under the “Devices” pull down menu.
CMLOUT Outputs for Eye Monitor
Connector J5 connects to CMLOUT+ and J6 connects to CMLOUT-, which are present on the bottom right
side of DS90Ux940Q Evaluation board. CMLOUT+/- must be enabled by register, 0x56[3] = 1 with 0x57
and 0x52, to be able to monitor the recovered FPD-Link III serial stream (see datasheet for details).
• Reg 0x57[2:1] : 10 for channel 1, 01 for channel 0
• Reg 0x52[7] : 1 for channel 1 ; 0 for channel 0
22
DS90UH940-Q1EVM User's Guide
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Typical Connection and Test Equipment
www.ti.com
1.11 Typical Connection and Test Equipment
The following is a list of typical test equipment that may be used to generate signals for the Serializer
inputs:
1. Digital Video Source – for generation of specific display timing such as Digital Video Processor or
Graphics Controller (GPU) with HDMI or OpenLDI output.
2. Any other signal generator / video source - This video generator may be used for video signal sources
for DVI or DP++
3. Any other signal / video generator that provides the correct input levels as specified in the datasheet.
The following is a list of typical test equipment that may be used to monitor the MIPI CSI-2 signals from
the DS90Ux940-Q1:
1. Logic Analyzer
2. Any SCOPE with a bandwidth of at least 4 GHz for observing differential signals.
3. UNH-IOL MIPI D-PHY Reference Termination Board (RTB)
4. UNH-IOL MIPI D-PHY/CSI/DSI Probing Board
5. UNH-IOL CSIGUI Tool
1.12 Termination Device
A termination device is required in order to properly monitor and measure the transmission of the CSI-2
signals. The termination device should support the change of signals as it switches between LP and HS
modes. This can be provided by either a CSI-2 receiver or a dedicated dynamic termination board. The
recommended termination board is the UNH-IOL MIPI D-PHY Reference Termination Board (RTB).
Serializer
Board
DS90Ux940
EVM Board
MIPI CSI-2
HDMI/DP++
or
OpenLDI
Generator
Applications
Processor
Display
FPD-Link II
Contents of Demo Kit
Graphics Controller /
Video Processor Board
Figure 1-21. Typical Test Setup for Video Application
The picture below shows a typical test set up using a video generator and logic analyzer.
Serializer
Board
DIGITAL
VIDEO
GENERATOR
DIGITAL VIDEO GENERATOR
HDMI/DP++
or
OpenLDI
DS90Ux940
EVM Board
MIPI CSI-2
FPD-Link II
Digital Video Source
Contents of Demo Kit
Logic Analyzer / Oscilloscope
Figure 1-22. Typical Test Setup for Evaluation
SNLU162 – October 2014
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23
Equipment References
www.ti.com
1.13 Equipment References
NOTE: Please note that the following references are supplied only as a courtesy to our valued
customers. It is not intended to be an endorsement of any particular equipment or supplier.
Digital Video Pattern Generator:
Astrodesign
www.astro-americas.com
Logic Analyzer:
Agilent Technologies Inc
www.agilent.com
MIPI Test Fixtures:
University of New Hampshire InterOperability Laboratory (UNH-IOL)
www.iol.unh.edu/services/testing/mipi/fixtures.php
Corelis CAS-1000-I2C/E I2C Bus Analyzer and Exerciser Products:
www.corelis.com/products/I2C-Analyzer.htm
Aardvark I2C/SPI Host Adapter Part Number: TP240141
www.totalphase.com/products/aardvark_i2cspi
1.14 Cable References
For optimal performance, we recommend Shielded Twisted Pair (STP) 100ohm differential impedance and
24 AWG (or larger diameter) cable for high-speed data applications.
Leoni Dacar 538 series cable:
www.leoni-automotive-cables.com
Rosenberger HSD connector:
www.rosenberger.de/en/Products/35_Automotive_HSD.php
24
DS90UH940-Q1EVM User's Guide
SNLU162 – October 2014
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Copyright © 2014, Texas Instruments Incorporated
Chapter 2
SNLU162 – October 2014
Bill of Materials
Item
Qty
References
Value
Part Number
Mfr
Description
1
35
C1, C2, C5, C8, C9,
C10, C11, C17, C23,
C24, C25, C26, C27,
C30, C31, C32, C35,
C48, C50, C53, C56,
C61, C65, C69, C73,
C77, C79, C83, C90,
C93, C99, C100, C102,
C103, C104
0.1uF
CGA2B3X7R1H104K05
0BB
TDK Corporation
CAP CER 0.1UF 50V
10% X7R 0402
2
4
C3, C4, C6, C7
0.033uF
CGA2B3X7R1H333K05
0BB
TDK Corporation
CAP CER 0.033UF 50V
10% X7R 0402
3
3
C12, C66, C80
10uF
C3216X7R1C106K
TDK
CAP CER 10UF 16V
X7R 10% 1206
4
2
C13, C89
2.2uF
T491B225K020AT
KEMET
CAP TANT 2.2UF 20V
10% 1411
5
10
C14, C47, C55, C60,
C64, C68, C72,
C76,C82, C92
1uF
CGA3E1X7R1E105K08
0AC
TDK Corporation
CAP CER 1UF 25V
10% X7R 0603
6
15
C15, C44, C51, C57,
C58, C62, C70,
C74,C78, C84, C85,
C86,C87, C94, C95
0.01uF
GCM155R71H103KA55
D
Murata Electronics
CAP CER 10000PF
50V 10% X7R 0402
7
2
C16, C88
22uF
F931E226MNC
nichicon
CAP TANT 22UF 25V
20% 2917
8
2
C18, C21
220PF
C1608X7R1H221K
TDK
CAP CER 220PF 50V
10% X7R 0603
9
2
C19, C20
30pF
C1608C0G1H300J
TDK
CAP CER 30PF 50V
5% NP0 0603
10
1
C22
2200PF
C1608X7R1H222K
TDK
CAP CER 2200PF 50V
10% X7R 0603
11
5
C28, C46, C49, C52,
C63
4.7uF
GRM21BR71C475KA7
3L
Murata Electronics
CAP CER 4.7UF 16V
10% X7R 0805
12
1
C29
470nF
C1608X7R1H474K080
AC
TDK
CAP CER 0.47UF 50V
10% X7R 0603
13
2
C33,C34
4.7pF
ECD-G0E4R7C
Panasonic
CAP CER 4.7PF 25V
NP0 0402
14
1
C36
0.022uF
C0805C223K5RACTU
Kemet
CAP CER 0.022UF 50V
10% X7R 0805
15
1
C37
10uF
C3225X7R1E106M250
AC
TDK Corporation
CAP CER 10UF 25V
X7R 20% 1210
16
1
C38
100uF
EEF-UD0K101R
Panasonic
CAP ALUM 100UF 8V
20% SMD
17
1
C39
270uF
APXA100ARA271MHC
0G
United Chemi-Con
CAP ALUM 270UF 10V
20% SMD
18
2
C40, C41
100uF
JMK325BJ107MM-T
Taiyo Yuden
CAP CER 100UF 6.3V
20% X5R 1210
19
1
C42
180pF
CC0805JRNP09BN181
Yageo
CAP CER 180PF 50V
5% NPO 0805
20
1
C43
150pF
08055A151JAT2A
AVX Corporation
CAP CER 150PF 50V
5% NP0 0805
21
1
C45
560pF
CC0805KRX7R9BB561
Yageo
CAP 560PF 50V
CERAMIC X7R 0805
22
7
C54, C59, C67, C71,
C75, C81, C91
10uF
JMK212AB7106KGHT
Taiyo Yuden
CAP CER 10UF 6.3V
10% X7R 0805
SNLU162 – October 2014
Submit Documentation Feedback
Bill of Materials
Copyright © 2014, Texas Instruments Incorporated
25
www.ti.com
Item
26
Qty
References
Value
Part Number
Mfr
Description
TDK Corporation
CAP CER 2200PF 50V
10% X7R 0402
23
1
C101
2.2nF
CGA2B2X7R1H222K05
0BA
24
1
D1
1SMB5922
1SMB5922B-13
Diodes Inc
DIODE ZENER 7.5V
3W SMB
25
1
D3
DIODE
B340A-13-F
Diodes Inc
DIODE SCHOTTKY 3A
40V SMA
26
1
F1
FUSE
1206L050/15YR
Littelfuse Inc
PTC RESET 15V .500A
SMD 1206
27
2
JP1, JP2
2-Pin Header_open
87220-2_open
AMP/Tyco
CONN HEADER VERT
.100 2POS 30AU. DO
NOT PURCHASE, DO
NOT MOUNT.
28
1
JP3
2-Pin Header_open
87220-2_open
AMP/Tyco
CONN HEADER VERT
.100 2POS 30AU. DO
NOT PURCHASE. DO
NOT POPULATE.
29
7
JP4, JP6, JP7, JP8,
JP9, JP10, JP11
2-Pin Header
87220-2
AMP/Tyco
CONN HEADER VERT
.100 2POS 30AU
30
2
JP5, JP12
3-Pin Header
87224-3
Tyco
CONN HEADER VERT
.100 3POS 15AU
31
1
J1
HSD_2X2
D4S20D-40ML5-Y
Rosenberger
Automotive HSD
Connector - Right Angle
Plug for PCB.
32
2
J2, J7
FAKRA
59S20X-40ML5-Y_open
Rosenberger
FAKRA-HF PCB RIGHT
ANGLE PLUG
33
6
J3, J4, J5, J6, J8, J9
SMA
142-0701-851
Emerson
CONN SMA JACK 50
OHM EDGE MNT
34
1
J10
mini USB 5pin
UX60-MB-5ST
Hirose
CONN RECEPT MINI
USB2.0 5POS.
35
1
J11
HEADER 7X2_open
PBC07DFAN_open
Sullins
CONN HEADER .100
DUAL STR 14POS. DO
NOT PURCHASE. DO
NOT POPULATE.
36
1
J12
HEADER 5X2
PBC05DFAN
Sullins
CONN HEADER .100
DUAL STR 10POS
37
1
J13
IDC1X4
22-11-2042
Molex/Waldom
Electronics Corp
CONN HEADER 4POS
.100 VERT GOLD
38
1
J14
HEADER 7X2
PBC07DFAN
Sullins
CONN HEADER .100
DUAL STR 14POS
39
2
J15, J16
2X10-Pin Header
N2520-6002RB
3M
CONN HEADER 20
POS STRGHT GOLD.
40
1
J17
2X10-Pin Header
67997-220HLF
FCI
CONN HEADER
20POS .100 STR 15AU
41
1
J18
CONN JACK PWR
PJ-002A
CUI Inc
CONN POWER JACK
2.1MM
42
1
J19
DIP20 SOCKET MSP430G2403IN20
4820-3004-CP
3M
SOCKET IC OPEN
FRAME 20POS .3"
43
1
J20
JTAG-14
AWHW14G-0202-T-R
Assmann
CONN HEADER LOWPRO 14POS GOLD
44
1
J21
2X2-Pin Header
87227-2
TEC
CONN HEADER VERT
.100 4POS 15AU
45
3
LED1, LED4
0603_green_LED
LTST-C191KGKT
LITE-ON INC
LED GREEN CLEAR
THIN 0603 SMD
46
1
LED2
0603_orange_LED
LTST-S270KFKT
Lite-On Inc
LED ORANGE CLR RT
ANG SMD
47
1
LED3
0603_red_LED
LTST-C190KRKT
LITE-ON INC
LED SUPER RED
CLEAR 0603 SMD
48
2
L1, L2
Z = 90 ohm
DLW21SN900HQ2L
Murata
CHOKE COIL
COMMON MODE
280MA SMD. DO NOT
PURCHASE. DO NOT
POPULATE.
49
1
L3
BK1608HS600-T
BK1608HS600-T
Taiyo Yuden
FERRITE BEAD 60
OHM 0603
50
1
L4
15uH
SDR1806-150ML
Bourns Inc.
INDUCTOR POWER
15UH SMD
Bill of Materials
SNLU162 – October 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
www.ti.com
Item
Qty
References
Value
Part Number
Mfr
Description
51
2
L5, L11
FB 1K@100MHz,0603
MPZ1608S102A
TDK Corporation
FERRITE CHIP BEAD
1000 OHM 0603
52
5
L6, L7, L8, L9, L10
FB 120@100MHz,0603
BLM18SG121TN1D
Murata Electronics
FILTER CHIP 120 OHM
3A 0603
53
1
Q1
BSS138
BSS138
Fairchild
MOSFET N-CH 50V
220MA SOT-23
54
4
R1, R2, R75, R98
220 Ohm,0402
ERJ-2GEJ221X
Panasonic
RES 220 OHM 1/10W
5% 0402 SMD
55
13
R12, R20, R37, R38,
R47, R63, R64,R73,
R74, R87, R91, R109,
R120
0 Ohm,0402_open
ERJ-2GEJ0R00X_open
Panasonic
RES ZERO OHM
1/16W 5% 0402 SMD.
DO NOT PURCHASE,
DO NOT LOAD.
56
2
R3, R4
57
4
R97, R107, R115, R116
0 Ohm,0402
ERJ-2GEJ0R00X
Panasonic
RES 0.0 OHM 1/10W
JUMP 0402 SMD
58
3
R5, R13, R40
45.3K Ohm,0402
ERJ-2RKF4532X
Panasonic
RES 45.3k OHM 1/10W
1% 0402 SMD
59
3
R6, R14, R41
90.9K Ohm,0402
ERJ-2RKF9092X
Panasonic
RES 90.9K OHM
1/10W 1% 0402 SMD
60
4
R7, R15, R18, R42
107K Ohm,0402
ERJ-2RKF1073X
Panasonic
RES 107K OHM 1/10W
1% 0402 SMD
61
9
R8,R9,R16,R17,R22,
R30,R43,R44,R53
113K Ohm,0402
ERJ-2RKF1133X
Panasonic
RES 113K OHM 1/10W
1% 0402 SMD
62
2
R10,R45
107K Ohm,0402
ERJ-2RKF1073X
Panasonic
RES 107K OHM 1/10W
1% 0402 SMD
63
3
R11,R19,R46
232K Ohm,0402
ERJ-2RKF2323X
Panasonic
RES 232K OHM 1/10W
1% 0402 SMD
64
3
R21,R29,R52
182K Ohm,0402
ERJ-2RKF1823X
Panasonic
RES 182K OHM 1/10W
1% 0402 SMD
65
3
R23,R31,R54
93.1K Ohm,0402
ERJ-2RKF9312X
Panasonic
RES 93.1K OHM
1/10W 1% 0402 SMD
66
3
R24,R32,R55
68.1K Ohm,0402
ERJ-2RKF6812X
Panasonic
RES 68.1K OHM
1/10W 1% 0402 SMD
67
6
R25,R27,R33,R35,R56,
R58
47.5K Ohm,0402
ERJ-2RKF4752X
Panasonic
RES 47.5K OHM
1/10W 1% 0402 SMD
68
3
R26,R34,R57
31.6K Ohm,0402
ERJ-2RKF3162X
Panasonic
RES 31.6K OHM
1/10W 1% 0402 SMD
69
3
R28,R36,R59
40.2K Ohm,0402
ERJ-2RKF4022X
Panasonic
RES 40.2K OHM
1/10W 1% 0402 SMD
70
4
R48, R49, R50, R65
49.9ohm,0402_open
ERJ-2RKF49R9X_open
Panasonic
RES 49.9 OHM 1/10W
1% 0402 SMD. DO
NOT PURCHASE. DO
NOT POPULATE.
71
5
R60, R61, R62, R76,
R77
10K
ERJ-3EKF1002V
Panasonic
RES 10.0K OHM
1/10W 1% 0603 SMD
72
2
R66, R67
33 ohm
ERJ-3GEYJ330V
Panasonic
RES 33 OHM 1/10W
5% 0603 SMD
73
5
R68, R99, R103, R113,
R117
0 Ohm, 0603
ERJ-3GEY0R00V
Panasonic
RES 0.0 OHM 1/10W
JUMP 0603 SMD
74
3
R69, R78, R79
1.5K
ERJ-3GEYJ152V
Panasonic
RES 1.5K OHM 1/10W
5% 0603 SMD
75
2
R70, R72
33K ohm
ERJ-3GEYJ333V
Panasonic
RES 33K OHM 1/10W
5% 0603 SMD
76
1
R71
1.2M ohm
ERJ-3GEYJ125V
Panasonic
RES 1.2M OHM 1/10W
5% 0603 SMD
77
10
R80, R86, R88,
R89,R90, R92, R93,
R94,R95, R96
100_open
ERJ-2GEJ101X_open
Panasonic
RES 100 OHM 1/10W
5% 0402 SMD. DO
NOT PURCHASE. DO
NOT POPULATE.
78
2
R81, R82
4.7K
ERJ-3GEYJ472V
Panasonic
RES 4.7K OHM 1/10W
5% 0603 SMD
79
3
R83, R84, R85
0 Ohm
ERJ-2GEJ0R00X
Panasonic
RES 0.0 OHM 1/10W
JUMP 0402 SMD
80
1
R100
52.3Kohm
ERJ-6ENF5232V
Panasonic
RES 52.3K OHM 1/8W
1% 0805 SMD
RES 0.0 OHM 1/10W
JUMP 0402 SMD
SNLU162 – October 2014
Submit Documentation Feedback
Bill of Materials
Copyright © 2014, Texas Instruments Incorporated
27
www.ti.com
Item
Qty
Value
Part Number
Mfr
Description
81
1
R101
9.53Kohm
RG2012P-9531-B-T5
Panasonic
RES 9.53K OHM 1/8W
.1% 0805 SMD
82
1
R102
3.09Kohm
ERJ-6ENF3091V
Panasonic
RES 3.09K OHM 1/8W
1% 0805 SMD
83
1
R104
2.49K
ERJ-3EKF2491V
Panasonic
RES 2.49K OHM
1/10W 1% 0603 SMD
84
3
R105, R111, R114
100K
ERJ-3EKF1003V
Panasonic
RES 100K OHM 1/10W
1% 0603 SMD
85
1
R106
1K
ERJ-3EKF1001V
Panasonic
RES 1.0K OHM 1/10W
1% 0603 SMD
86
1
R108
4.99K
ERJ-3EKF4991V
Panasonic
RES 4.99K OHM
1/10W 1% 0603 SMD
87
1
R110
23.2K
ERJ-2RKF2322X
Panasonic
RES 23.2K OHM
1/10W 1% 0402 SMD
88
1
R112
12.1K
ERJ-2RKF1212X
Panasonic
RES 12.1K OHM
1/10W 1% 0402 SMD
89
1
R118
330ohm
ERJ-2RKF3300X
Panasonic
RES 330 OHM 1/10W
1% 0402 SMD
90
1
R119
47Kohm
ERA-3AEB473V
Panasonic
RES 47K OHM 1/16W
.1% 0603 SMD
91
3
SW1, SW2, SW3
SPST
ADTSM31NV
APEM Components
SWITCH TACTILE
SPST-NO 0.05A 12V
92
4
S1, S2, S4, S5
SW SMD-8
219-8MST
CTS
Electrocomponents
SWITCH TAPE SEAL 8
POS SMD 50V
93
1
S3
SW DIP-3
78B03ST
Grayhill
SWITCH DIP
EXTENDED SEALED
3POS
94
12
TP1, TP2, TP3,
TP4,TP5, TP6,
TP7,TP8, TP9, TP10,
TP11, TP12
TEST POINT
95
1
U1
DS90UH940-Q1
DS90UB940-Q1
DS90UH940-Q1
DS90UB940-Q1
TI
DS90UH940-Q1
DS90UB940-Q1
96
1
U2
TPS73533DRB
TPS73533DRBT
TI
IC REG LDO 3.3V 0.5A
8SON
97
1
U3
TPD4E004DRY
TPD4E004DRYR
TI
IC 4CH ESD-PROT
ARRAY 6-SON
98
1
U4
MSP430F5529IPN
MSP430F5529IPN
TI
IC MCU 16BIT 128K
FLASH 80LQFP
99
1
U5
TXB0106IPWR
TXB0106PWR
TI
IC 6BIT NON-INV
TRANSLTR 16TSSOP
100
1
U6
TCA9406DCUR
TCA9406DCUR
TI
IC V-LEVEL XLATR
I2C/SMBUS US8
101
1
U7
LM25576MH/NOPB
LM25576MH/NOPB
TI
IC REG BUCK ADJ 3A
20TSSOP
102
1
U8
TPS74801DRC
TPS74801DRCT
TI
IC REG LDO ADJ 1.5A
10SON
103
1
U9
TPS767D318PWP
TPS767D318PWP
TI
IC REG LDO 1.8V/3.3V
1A 28HTSSOP
104
1
Y1
Crystal, SMT Quart
Crystal
ECS-240-20-5PX-TR
ECS
CRYSTAL 24.000MHZ
20PF SMD
SV601029
TI
DS90UH940-Q1EVM
105
28
References
DS90UX948_940Q1EVM Rev1E Brd
PCB
TEST POINT. NOT A
COMPONENT
Bill of Materials
SNLU162 – October 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
SNLU162 – October 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
1
2
3
4
A
A
C
C
Date:
Size
A
Title
Tuesday, September 16, 2014
D
E
Sheet
1
E
of
Prepreg Material
Document Number
DS90UBUH948_940-Q1EVM
Board Stackup
4.5 MIL
Secondary component side, 1.58 MIL (layer 4)
4
Core Material
Power plane, 1.4 MIL (layer 3)
3
B
4.5 MIL
Ground plane, 1.4 MIL (layer 2)
2
44.2 MIL Core
Primary component side, 1.58 MIL (layer 1)
D
1
LAYOUT NOTES:
1) 4 layer board.
2) Use standard FR-406 or FR-370HR.
3) 5% impedance tolerance.
4) Minimum 4 standoffs on each corner of board. (0.156 X 4).
B
8
Rev
1E
1
2
3
4
Appendix A
SNLU162 – October 2014
EVM PCB Schematics
EVM PCB Schematics
29
30
EVM PCB Schematics
Copyright © 2014, Texas Instruments Incorporated
A
B
C
D
Supply
Connector
VSS
+5V
Aux
5
SDA
I2C
Connector SCL
FPD3 Input
HSD
SMA
SMA /
FAKRA
HSD
SMA
SMA /
FAKRA
+12V
Barrel
VDD33
VDD12
VDD18
Power
USB
USB2ANY
FPDL3-
FPDL3+
FPDL3-
FPDL3+
GPIO0
GPIO1
I2S_DA
I2S_DB
I2S_DC
I2S_DD
I2S_CLK
I2S_WC
MCLK
I2S Bank
D_GPIO
4
MODE_SEL[1:0]
LOCK
3
IDx
FPD (LVDS) Output
LVDSx-
LVDSx+
LVDSx-
LVDSx+
3
PASS
Status LEDs
CAD
D_GPIO0
D_GPIO1
D_GPIO2
D_GPIO3
DS90UH948Q
DS90UH940Q
PDB
BISTC
BISTEN
INTB
Options
Board Block Diagram
4
20-pin IDC
20-pin IDC
5
Date:
Size
A
Title
J9
J7/J8
J4
J2/J3
J10
J18
U4
U2
U7
2
S1
S4
J14
U1
S5
J19
U8
Tuesday, September 16, 2014
Document Number
DS90UBUH948_940-Q1EVM
S2
J17
Block Diagram
J6
J5
J1
1
Sheet
U9
2
of
J16
S3
1
8
J13
J15
Approximate layout of major components/connectors
2
Rev
1E
A
B
C
D
Appendix A
www.ti.com
SNLU162 – October 2014
Submit Documentation Feedback
1
2
3
5
4
3
2
1
5
4
3
2
1
VSS
5
4
3
2
1
VSS
5
4
3
2
1
Layout note: overlay
footprint for SMA and
FAKRA connector - signal
pin 1 on both is the same
pad
FAKRA
J7
Layout note: overlay
footprint for SMA and
FAKRA connector - signal
pin 1 on both is the same
pad
5
4
3
2
1
SMA
J4
SMA
5
4
3
2
1
5
4
3
2
1
VSS
5
4
3
2
1
VSS
5
4
3
2
1
SMA
J9
5
4
3
2
1
VSS
5
4
3
2
1
VSS
A
R65
49.9ohm,0402_open
VSS
0.625"
5
4
3
2
1
SMA
J8
1
2
VSS
R50
49.9ohm,0402_open
0.625"
J3
J1
HSD_2X2
I2C_SDA
I2C_SCL
VDD12_LVDS
VDDP12_LVDS
VDDL12c
VSS
FAKRA
J2
I2C_SDA
I2C_SCL
VDD12_LVDS
{4,5,7}
{4,5,7}
VDDP12_LVDS
VDDL12c
{6}
{6}
VDDP12_0
VDDP12_1
{6}
{6}
{6}
4
RINA-
RINB-
RINA+
RINB+
50 ohm
single ended
impedance
traces
50 ohm
single ended
impedance
traces
RINB+
RINB-
RINA+
RINA-
0.625"
RINB-
RINB+
RINA-
RINA+
Z = 90 ohm
Z = 90 ohm
VSS
B
CMLOUT+
5
5 4
4 3
3 2
2 1
J5 1
VSS 50 ohm
CMLOUTsingle
ended
5
5 4
impedance
traces
4 3
3 2
2 1
1
J6
L2
L1
LAYOUT NOTE: L short pin 1 to
pin 2, short pin 3 and pin 4. Cut
traces to populate common
mode filter.
VSS
C21
/
+
C11 0.1uF
1
2
C9 0.1uF
1
2
VSS
S3
VSS
65
VSS
PDB
JP3
INTB_IN
C
2
0.1uF
VSS
SPST
SW1
1
C10
DAP
CAP_PLL0
MODE_SEL1
VDDP12_CH0
VDDR12_CH0
RIN0+
RIN0CMF
VDD33_A
VDDR12_CH1
RIN+
RINVDDP12_CH1
MODE_SEL0
CMLOUTP
CMLOUTM
CAP_PLL1
50 ohm single ended
impedance traces
3'%
BISTC
BISTEN
Silkscreen
namings
VDDIO
VSS
1 R48
2
49.9ohm,0402_open
1 R49
2
49.9ohm,0402_open
VSS
2
0.1uF
49
MODE_SEL1 50
51
VDDP12_0
52
VDDR12_0
53
C4 0.033uF100 ohm differential impedance +/-5%. 54
1
2
2
55
VSS C51
0.1uF
C6 0.033uF
VDD33c 56
{3,6} VDD33c
1
2
57
VDDR12_1
58
C7 0.033uF100 ohm differential impedance +/-5%. 59
1
2
60
VDDP12_1
MODE_SEL0 61
DOUT+ 62
100 ohm differential impedance +/-5%. DOUT- 63
64
2
VSS C81
0.1uF
VSS
U1
Connect to VSS
VSS
0603_orange_LED LED2
2
1 2
1
R2
220 Ohm,0402
C3 0.033uF
1
2
GPIO0
Connect to VSS
GPIO0
{4,7}
'68+04
10uF
C12
948
940
R3
open
populated
VDDP12_LVDS
VDD33_B
D4D4+
D5D5+
D6D6+
CLK2CLK2+
D7D7+
VDD12_LVDS
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D
VDDP12_LVDS
VDD33c
D4D4- {5}
D4+
D4+ {5}
D5D5- {5}
D5+
D5+ {5}
D6D6- {5}
D6+
D6+ {5}
CLK2CLK2- {5}
CLK2+
CLK2+ {5}
D7D7- {5}
D7+
D7+ {5}
VDD12_LVDS
D_GPIO0
D_GPIO0 VSS
{5}
D_GPIO1
D_GPIO1 {5}
D_GPIO2
D_GPIO2 {5}
VSS
{6}
VDD33c
VDD12_Pin33
R4
populated
open
2 R3
1 VDD12_Pin33
0 Ohm,0402_open
1 R4
2 0.1uF
2
C11
0 Ohm,0402
D0D0+
D1{5}
D1+
{5}
D2{5}
D2+
{5}
CLK1{5}
CLK1+
{5}
D3D3+
{5}
{5}
{5}
{5}
PDB
IDx
I2C_SDA
I2C_SCL
VDDL12c
D0D0+
D1D1+
D2D2+
CLK1CLK1+
D3D3+
LED1
1
{3,5}
1
2
Date:
Size
B
Title
MODE_SEL0
2
0603_green_LED
2
1
2
R1
220 Ohm,0402
R5
45.3K Ohm,0402
182K Ohm,0402
LOCK
1
2
2
D
R6
90.9K Ohm,0402
113K Ohm,0402
C
1
2
2
Layout note: For all differential pairs(CSI-2 and LVDS) in this design follow the guidelines decribed below:
Route together with controlled differential 100ohm impedance and controlled single ended 50ohm
impedance. Keep away from other high speed signals. Keep lengths within 5mil of each other. Keep
traces on layers adjacent to the ground plane. Keep the number of VIAS to minimum. If VIAS are used,
make it symetrical through all signals. Keep diff pairs separated at least by x3 of the trace width.
NO STUBS on the signal path, components should be placed such that the signals can routed in
pass-through manner.
R7
107K Ohm,0402
93.1K Ohm,0402
2
1
2
2
JP2
1
2
2
1
R8
113K Ohm,0402
68.1K Ohm,0402
B
R9
113K Ohm,0402
47.5K Ohm,0402
2
R10
107K Ohm,0402
31.6K Ohm,0402
JP1
1
2
VDD33c
VSS
0.1uF
IDX
Tuesday, September 16, 2014
Document Number
DS90UBUH948_940-Q1EVM
DS90UBUH
DS90UBUH9
DS90UBUH940
SW SMD-8
MODE_SEL0
S1
MODE_SEL1
C102
/
+
2
VDDP12_0
VDDP12_1
5
6
5
6
8
7
1
2
4
3
4
3
R13
45.3K Ohm,0402
VDDR12_0
VDDR12_1
R37 2
8
7
1
R38 2
1
1
2
1
SMA
R11
232K Ohm,0402
47.5K Ohm,0402
VDDR12_0
VDDR12_1
0 Ohm,0402_open
0 Ohm,0402_open
4
1
2
2
{6}
{6}
0 Ohm,0402_open
0 Ohm,0402_open
SMA
3
1
2
2
15
13
11
9
7
5
3
1
16
14
12
10
8
6
4
2
2
8
7
6
5
4
3
2
1
1
1
R12
0 Ohm,0402_open
40.2K Ohm,0402
1
2
1
2
1
2
2
2
4
R14
90.9K Ohm,0402
113K Ohm,0402
R41
182K Ohm,0402
R40
45.3K Ohm,0402
R52
182K Ohm,0402
E
R42
3
R15
107K Ohm,0402
93.1K Ohm,0402
1
1
1
2
2
R43
2
1
2
1
2
90.9K Ohm,0402
R53
113K Ohm,0402
2
1
2
2
1
2
1
2
2
1
2
107K Ohm,0402
R54
93.1K Ohm,0402
R44
A
SW DIP-3
R18
107K Ohm,0402
R45
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R16
113K Ohm,0402
68.1K Ohm,0402
1
2
1
1
R63 2
1
R64 2
1
2
R602
R612
R62
1
1 10K
1 10K
10K
3
2
1
4
5
6
2
1
2
2
1
1
2
E
Sheet
3
/
+
VSS
0.1uF
C103
VSS
8
VSS
Rev
1E
0.1uF
C104
SW SMD-8
IDX
of
/
VSS
SW SMD-8
MODE_SEL1
S2
S4
+
2
PDB
IDX
I2C_SDA
I2C_SCL
VDDL12_1
D0D0+
D1D1+
D2D2+
CLK1CLK1+
D3D3+
VDD25_CAP
BISTC
BISTEN
1
2
2
2
113K Ohm,0402
R55
68.1K Ohm,0402
LOCK
CAP_I2S
VDDIO
BISTC/INTB
BISTEN/TESTEN
VDDL12_0
SDOUT/GPIO0/PASS
SWC/GPIO1
I2S_DD/GPIO3
I2S_DC/GPIO2
I2S_DB/GPIO5_REG
I2S_DA/GPIO6_REG
I2S_CLK/GPIO8_REG
I2S_WC/GPIO7_REG
MCLK
D_GPIO3/SS
R17
113K Ohm,0402
47.5K Ohm,0402
1
2
1
2
113K Ohm,0402
R56
47.5K Ohm,0402
15
13
11
9
7
5
3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
2
15
13
11
9
7
5
3
1
16
14
12
10
8
6
4
2
16
14
12
10
8
6
4
2
1
R46
31.6K Ohm,0402
1
2
1
LOCK
CAPI2S
VDDIOc
BISTC
BISTEN
VDDL12c
GPIO0
GPIO1
I2S_DD
I2S_DC
I2S_DB
I2S_DA
I2S_CLK
I2S_WC
MCLK
D_GPIO3
GPIO0
{5}
GPIO1
I2S_DD
{5}
I2S_DC
{3,5}
I2S_DB
{5}
I2S_DA
I2S_CLK
{5}
I2S_WC
{5}
MCLK
{5}
D_GPIO3
{5}
1
2
2
2
2
40.2K Ohm,0402
R47
8
7
6
5
4
3
2
1
78
70
6C
68
64
60
5C
58
1 2 3
O
N
VSS
VDD33
VDD33c
VDDIO
VDDIOc
{5}
R19
232K Ohm,0402
47.5K Ohm,0402
1
2
1
2
232K Ohm,0402
R58
47.5K Ohm,0402
0 Ohm,0402_open
R59
40.2K Ohm,0402
107K Ohm,0402
R57
31.6K Ohm,0402
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
{5}
{5}
R20
0 Ohm,0402_open
1
R21
1
R22
1
R23
1
R24
1
R25
1
R26
1
R27
1
R28
1
R29
1
R30
1
R31
1
R32
1
R33
1
R34
1
R35
1
R36
O
N
O
N
Copyright © 2014, Texas Instruments Incorporated
2
1 2 3 4 5 6 7 8
SNLU162 – October 2014
Submit Documentation Feedback
1
O
N
{4,5,6,7}
VSS
{5,6,7}
VDD33
{3,6} VDD33c
{4,5,6}
VDDIO
{6} VDDIOc
1
2
3
4
www.ti.com
Appendix A
EVM PCB Schematics
31
1
2
3
4
{5}
I2C_SCL
{3,5,7}
0603_green_LED
LED4
Q1
BSS138
9
9
VSS
8
8
7
VDD33_UC
A
VSS
C27
0.1uF
C29
470nF
C22
2200PF
P5.1/A9/VREF-/VeREF-
VUSB
VBUS
PUR
DM
DP
VSS
VSS
VBUS
VUSB
DP
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
P4.0/PM_UCB1STE/PM_UCA1CLK
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.3/PM_UCB1CLK/PM_UCA1STE
DVSS2
DVCC2
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.6/PM_NONE
P4.7/PM_NONE
P5.6/TB0.0
P5.7/TB0.1
P7.4/TB0.2
P7.5/TB0.3
P7.6/TB0.4
GPIO3/PWM2
NOTE: Float p2.3, p2.5, and p2.6 on MSP430 for USB2ANY detection
C
R78
1.5K
R79
1.5K
VDD33_UC
1
2
3
4
VSS
8
7
6
5
GPIO5/SPI(SOMI)/UART(RXD)
GPIO2/SPI(SCLK)
GPIO0/I2C(SDA)
GPIO1/I2C(SCL)
0.1uF
C24
VDD33_UC
VSS
1uF
C14
L3
1
2
BK1608HS600-T
GPIO4/SPI(SIMO)/UART(TXD)
IN
NC3
NC2
EN
TPS73533DRB
OUT
NC1
NR/FB
GND
U2
SDABRD
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
0.01uF
C15
{4}
{4}
{4}
60
PUR
DM
2.2uF
C13 +
P7.7/TB0CLK/MCLK
JP4
1 R68
2
0 Ohm, 0603
3V3@0.5A UC POWER SUPPLY
SCLBRD
B
U4
MSP430F5529IPN
220PF VSS
C21
30pF
XTAL 24 MHz C19
Crystal, SMT Quart Crystal
Y1
30pF
C20
{4}
{4}
{4}
VDD33_UC
GPIO7/PWM0
VCORE
DVSS1
DVCC1
P8.2
P8.1
P8.0
AVSS1
P5.5/XOUT
P5.4/XIN
AVCC1
VSS
C18
220PF
J11
HEADER 7X2_open
JTAG
R72
33K ohm
P5.0/A8/VREF+/VeREF+
P7.3/CB11/A15
P7.2/CB10/A14
P7.1/CB9/A13
P7.0/CB8/A12
P6.7/CB7/A7
P6.6/CB6/A6
P6.5/CB5/A5
VSS
SPST
SW2
R71
1.2M ohm
VSS
VDD33_UC
R69
1.5K
P6.4/CB4/A4
33 ohm
33 ohm
F1
FUSE
C
GPIO6/PWM1/SPI(CS)
20
4.7uF
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C17
0.1uF
19
VSS
U3
R66
R67
C28
GPIO10/VEREF-
VSS
VSS
C23
0.1uF
GPIO8/ADC3
GPIO9/ADC2
AIN_B_1
AIN_B_0
VSS
R70
33K ohm
GPIO11/VEREF+
I2C_SCL
I2C_SDA
VSS
VDDIO
VDD_I2C
7
6
6
VDD33_UC
I2C_SDA
VSS
VDDIO
VDD_I2C
{3,5,7}
{3,5,6,7}
{3,5,6}
J10
2
2
R75 11
220 Ohm,0402
1
2
3
2
1
6
5
4
VCC
IO4
IO3
IO1
IO2
GND
1
2
3
4
5
TPD4E004DRY
1
2
mini USB 5pin
2
1
66
1
2
3
4
5
21
1
2
80
P6.3/CB3/A3
79
P6.2/CB2/A2
P1.0/TA0CLK/ACLK
22
2
~RST
P1.1/TA0.0
78
P6.1/CB1/A1
23
1
TCK
P1.2/TA0.1
77
P6.0/CB0/A0
75
PJ.3/TCK
~RST/NMI/SBWTDIO
76
2
4
6
8
10
12
14
P1.6/TA1CLK/CBOUT
27
P1.7/TA1.0
28
65
1
3
5
7
9
11
13
74
PJ.2/TMS
TDI
73
PJ.1/TDI/TCLK
TDO
72
PJ.0/TDO
P2.0/TA1.1
29
64
PU.1/DM
TEST1
71
TEST/SBWTCK
P2.1/TA1.2
30
P1.3/TA0.2
70
P5.3/XT2OUT
P2.2/TA2CLK/SMCLK
31
P1.4/TA0.3
24
69
P5.2/XT2IN
P2.3/TA2.0
32
P1.5/TA0.4
25
68
AVSS2
P2.4/TA2.1
33
62
1
2
1
2
PWPD
9
D1
1SMB5922
VBUS
22uF
C16 +
1
2
1
2
61
VSSU
TDO
TDI
TMS
TCK
VSS
~RST
26
67
V18
P2.5/TA2.2
34
VUSB
P2.6/RTCCLK/DMAE0
35
VBUS
P2.7/UCB0STE/UCA0CLK
36
P3.0/UCB0SIMO/UCB0SDA
37
63
PUR
38
P3.1/UCB0SOMI/UCB0SCL
1
2
PU.0/DP
P3.2/UCB0CLK/UCA0STE
39
P3.3/UCA0TXD/UCA0SIMO
40
D
D
{3,7}
PDB
2
1
B
VDD_I2C
I2C_SDA
GPIO0/I2C(SDA)
B1
VCCB
B2
B3
B4
B5
B6
GND
TXB0106IPWR
A1
VCCA
A2
A3
A4
A5
A6
OE
16
15
14
13
12
11
10
9
Date:
Size
C
Title
C30
0.1uF
1
2
3
4
SCL_B
VCCB
OE
SCL_A
8
7
6
5
VSS
E
Tuesday, September 16, 2014
C31
0.1uF
Sheet
2R77
10K 1
I2C_SCL
GPIO1/I2C(SCL)
Document Number
DS90UBUH948_940-Q1EVM
USB Controller
TCA9406DCUR
SDA_B
GND
VDDA
SDA_A
U6
4
VDD33_UC
50 ohm single ended
impedance traces
INTB_CTRL
GPIO6/PWM1/SPI(CS)
GPIO2/SPI(SCLK)
GPIO4/SPI(SIMO)/UART(TXD)
GPIO5/SPI(SOMI)/UART(RXD)
PDB_CTRL
I2C LEVEL TRANSLATOR
1
2
3
4
5
6
7
8
U5
50 ohm single ended
impedance traces
1 R74
2
0 Ohm,0402_open
VOLTAGE LEVEL TRANSLATOR
PDB_CTRL
INTB_CTRL
1 R73
2
0 Ohm,0402_open
GPIO5/SPI(SOMI)/UART(RXD)
GPIO7/PWM0
GPIO1/I2C(SCL)
GPIO3/PWM2
50 ohm single ended
impedance traces
GPIO7/PWM0
HEADER 5X2
2
4
6
8
10
E
GPIO3/PWM2
1 R120
2
0 Ohm,0402_open
INTB
{7} INTB
SS
{7} SS
C25
{7} SPLK
SPLK
MISO
{7} MISO
0.1uF
{7} MOSI
MOSI
2R76
10K 1
PDB
VDDIO
VSS
1
3
5
7
9
J12
USB2ANY CONNECTOR
GPIO4/SPI(SIMO)/UART(TXD)
GPIO6/PWM1/SPI(CS)
GPIO0/I2C(SDA)
GPIO2/SPI(SCLK)
2
1
Copyright © 2014, Texas Instruments Incorporated
2
EVM PCB Schematics
1
of
VSS
8
C26
0.1uF
VDD33_UC
2
32
1
A
Rev
1E
1
2
3
4
Appendix A
www.ti.com
SNLU162 – October 2014
Submit Documentation Feedback
1
2
3
4
{3} D4{3} D4+
{3} D5{3} D5+
{3} D6{3} D6+
{3} CLK2{3} CLK2+
{3} D7{3} D7+
{3} D0{3} D0+
{3} D1{3} D1+
{3} D2{3} D2+
{3} CLK1{3} CLK1+
{3} D3{3} D3+
D4D4+
D5D5+
D6D6+
CLK2CLK2+
D7D7+
D0D0+
D1D1+
D2D2+
CLK1CLK1+
D3D3+
1
A
R96
100_open
R95
100_open
R94
100_open
R93
100_open
R92
100_open
100 ohm diff pair. +/-5%.
Resistors have to be placed close to U1.
+/- 1 mil for all inter/intra pairs.
R90
100_open
R89
100_open
R88
100_open
R86
100_open
R80
100_open
100 ohm diff pair. +/-5%.
Resistors have to be placed close to U1.
+/- 1 mil for all inter/intra pairs.
D7+/CSI0_C-
C2+/CSI0_D0-
D5+/CSI0_D1-
D5+/CSI0_D2-
D4+/CSI0_D3-
D3+/CSI1_C-
C1+/CSI1_D0-
D2+/CSI1_D1-
D1+/CSI1_D2-
D0+/CSI1_D3-
J15 TX OUT
2
4
6
8
10
12
14
16
18
20
J16 TX OUT
2
4
6
8
10
12
14
16
18
20
B
VSS
2X10-Pin Header
1
3
5
7
9
11
13
15
17
19
VSS
2X10-Pin Header
1
3
5
7
9
11
13
15
17
19
D7-/CSI0_C+
C2-/CSI0_D0+
D6-/CSI0_D1+
D5-/CSI0_D2+
D4-/CSI0_D3+
D3-/CSI1_C+
C1-/CSI1_D0+
D2-/CSI1_D1+
D1-/CSI1_D2+
D0-/CSI1_D3+
0.5"
VSS
VSS
TP3
TEST POINT
1
1
1
TP12
TEST POINT
TP11
TEST POINT
TP10
TEST POINT
TP9
TEST POINT
1
1
TP7
TEST POINT
TP8
TEST POINT
TP6
TEST POINT
TP5
TEST POINT
1
1
1
1
TP4
TEST POINT
TP2
TEST POINT
1
1
TP1
TEST POINT
1
C
C
TP
Dn
Dp
TP
1.12mm
0402 pad
1.12mm
1
2
3
VDDIO
VDD33
VDD_I2C
VDD18
50 ohm single ended
impedance traces
50 ohm single ended
impedance traces
VSS
VSS
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
HEADER 7X2
J14
D
VDD_I2C
R81
4.7K
0603
VSS
2
1
R84
2 0 Ohm R85
1
0 Ohm
C33 C34
VDD_I2C
4.7pF 4.7pF
VSS
Date:
Size
B
Title
DB
I2S_DB {3}
DA
I2S_DA {3}
I2S_WC WC
{3}
I2S_CLK CLK
{3}
MCLK
MCLK {3}
SDOUT
GPIO0 {3}
SWC
GPIO1 {3}
DC
I2S_DC {3}
DD
I2S_DD {3}
E
E
Sheet
{3,4,7}
{3,4,7}
5
{3,4,6,7}
VSS
{6,7} VDD33
{6} VDD18
{3,4,6}
VDDIO
I2C_SDA
I2C_SCL
Tuesday, September 16, 2014
Document Number
DS90UBUH948_940-Q1EVM
Output and Termination
GPIO0
GPIO1
I2S_DC
I2S_DD
VDDIO
I2S_DB
I2S_DA
I2S_WC
I2S_CLK
MCLK
I2C_SDA
I2C_SCL
R82
4.7K
0603
TESTEN
BISTEN
BISTEN {3}
BISTC
BISTC {3} INT_B
1R87
0 Ohm,0402_open
2
VDDIO
SS
D_GPIO3 D_GPIO3 {3}
SPLK
D_GPIO2 D_GPIO2 {3}
MISO
D_GPIO1 D_GPIO1 {3}
MOSI
D_GPIO0 D_GPIO0 {3}
VSS
2
4
6
8
10 1 R91
2
12 0 Ohm,0402_open
14
16
18
20
2X10-Pin Header
J17
1
3
5
7
9
11
13
{4}
J13
0 Ohm R83
2
1
C32
0.1uF
JP6
External I2C connection
JP5
D
Place at the board edge
1
2
B
1
2
1 2
1 2
1 2
1 2
2
1
1 2
1 2
1 2
Copyright © 2014, Texas Instruments Incorporated
1 2
SNLU162 – October 2014
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2
1
2
1
2
3
4
1
2
1
1
2
2
A
of
8
Rev
1E
VSS
VDD33
VDD18
VDDIO
1
2
3
4
www.ti.com
Appendix A
EVM PCB Schematics
33
1
2
3
4
VDD12
VDD12
VDD12
VDD12
VDD12
VDD33
L5
1
VSS
10uF
C37
L7
VSS
L9
A
VSS
FB 120@100MHz,0603
L10
VSS
FB 120@100MHz,0603
VSS
FB 120@100MHz,0603
L8
FB 120@100MHz,0603
VSS
FB 120@100MHz,0603
L6
VSS
FB 1K@100MHz,0603
MAIN
12V INPUT
POWER
CONNECTOR
2
1
10uF
C81
10uF
C75
10uF
C71
10uF
C67
10uF
C59
10uF
C54
1uF
C82
1uF
C76
1uF
C72
1uF
C68
1uF
C60
1uF
C55
C35
0.1uF
VCC
SD
VIN
VIN
SYNC
COMP
FB
RT
RAMP
AGND
BST
PRE
SW
SW
IS_1
IS_2
PGND
PGND
OUT
SS
20
19
18
17
16
15
14
13
12
11
0.1uF
C83
0.1uF
C77
0.1uF
C73
0.1uF
C69
0.1uF
C61
0.1uF
C56
0.01uF
C84
0.01uF
C78
0.01uF
C74
0.01uF
C70
0.01uF
C62
0.01uF
C85
{3}
{3}
VDDP12_1
VDDR12_1
{3}
{3}
VDDL12c
{3}
B
Place near pin of U1
VDD12_LVDS
VDDP12_LVDS
Place near pin of U1
VDD12_LVDS
VDDP12_LVDS
0.01uF
C95
VDDP12_0
VDDR12_0
Place near pin of U1
VDDL12c
0.01uF
C87
{3}
Place near pin of U1
VDDP12_1
VDDR12_1
0.01uF
{3}
Place near pin of U1
VDD12_Pin33
VDDP12_0
VDDR12_0
C86
0.01uF
C44
R102
15uH
2
{3}
{3}
3.09Kohm
DIODE
D3
0.022uF
2
L4
1
VSS
VDD33c
C36
1
Place near pin of U1
VDD33c
0.01uF
C58
VDD12_Pin33
0.01uF
C57
MAIN POWER
1
2
3
4
5
6
7
8
9
10
U7
21
DAP
VDD_12.0V_EXTERNAL
1
2
1
2
3
CONN JACK PWR
+5V
+
1
C41
100uF 100uF
C40
0603_red_LED
LED3
C
JP7
JP11
2
VSS
4.7uF
C63
VSS
1uF
C64
1 R99
2
0 Ohm, 0603
1
VSS
C
2.2uF
22uF
{3,4,5}
C89 +
C88 +
VDDIO External input
+5V
Layout note: mount
C38, C39 on top side of
board.
270uF
+ C39
100uF
C38
2
R98 1 2
220 Ohm,0402
1
2
1R97
2
0 Ohm,0402
1
2
1
B
1
2
1
2
1K R106
1
2
1
2
2
2
VDDIO
0.1uF
VSS
C90
+5V
U9
VDD18
VDDIO
VDD33
VSS
1
4.7uF
C52
L11
VSS
1
2
3
VDDIO=VDD33
VDDIO=VDD18
JP12
VSS
10uF
1uF
C92
1RESET
NC13
NC12
1FB/NC
1OUT
1OUT
2RESET
TPS767D318PWP NC11
NC10
NC9
2OUT
2OUT
NC8
NC7
D
0.1uF
C93
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2 R114
100K
0.01uF
C94
6
7
8
9
10
Date:
Size
Title
10uF
0.1uF
10uF
0.1uF
VSS
C80
C79
VSS
C66
VSS
VSS
C65
1
23.2K
1
12.1K
0.01uF
C51
E
Sheet
6
JP10
VDD33
JP9
VDD18
VSS
of
8
JP8
VDD18
VDD33
1 R103
2 VDD12
0 Ohm, 0603
0.1uF
C50
VDD18
{5}
VSS
VDD33
{5,7}
1 R117
2
0 Ohm, 0603
Tuesday, September 16, 2014
E
{3,4,5,7}
1 R113
2
0 Ohm, 0603
VSS
4.7uF
C49
Document Number
DS90UBUH948_940-Q1EVM
Power and Decoupling
Place near pin of U1
{3}
2
R110
2
R112
VDDIOc
VSS
1
VDDIOc
GND
SS
FB
OUT
OUT
PwPd
2 R111
100K
VSS
EN
BIAS
PG
IN
IN
U8
TPS74801DRC
0.1uF
C53
5
4
3
2
1
1V2@0.5A POWER SUPPLY
D
1 R107
2
0 Ohm,0402
0.1uF 2 R105
100K
C48
FB 1K@100MHz,0603
C91
NC1
NC2
1GND
1EN
1IN
1IN
NC3
NC4
2GND
2EN
2IN
2IN
NC5
NC6
U9
VSS
1uF
C47
1
1V8@1A POWER SUPPLY
3V3@1A POWER SUPPLY
4.7uF
C46
VSS
VDDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+5V
1
2
2
1 C42
180pF
1 C45 2
R100 1
560pF 52.3Kohm
2
R101 1
9.53Kohm
2
1 C43
150pF
1
1
2
J18
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
LM25576MH/NOPB
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
0 Ohm,0402
1
2 R109 1
0 Ohm,0402_open
2
1
1
2
2
0 Ohm,0402
1
R115
2
1
2
1
2
2
1
1
2
1
2
1
2
1
11
1
2
2
R104
1
2.49K
2
R108
2
PWPD
29
1
R116
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Copyright © 2014, Texas Instruments Incorporated
2
EVM PCB Schematics
2
2
1
2
1
1
2
1
2
1
4.99K
1
34
2
A
Rev
1E
1
2
3
4
Appendix A
www.ti.com
SNLU162 – October 2014
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SNLU162 – October 2014
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Copyright © 2014, Texas Instruments Incorporated
I2C_SCL
{3,4,5}
1
2
3
I2C_SDA
{3,4,5}
4
A
I2C_SCL
I2C_SDA
MISO
MOSI
SS
SPLK
INTB
{4}
{4}
{4}
{4}
{4}
B
SW0
MISO
MOSI
SS
SPLK
SW1
SW2
INTB
SW3
1
3
DVCCDVSS
P1.0 P2.6
P1.1 P2.7
P1.2 TEST
P1.3 RST
P1.4 SDA
P1.5
SCL
P2.0 P2.5
P2.1 P2.4
P2.2 P2.3
J19
20
19
18
17
16
15
14
13
12
11
2
4
RST
TEST
2X2-Pin Header
J21
RST
SPST
SW3
SW4
SW5
TEST
RST
I2C_SDA
I2C_SCL
PDB
SW6
SW7
2.2nF
C101
RST
47Kohm
0603
R119
VDD33
C
C99
0.1uF
PDB
VSS
{3,4}
VDD33
C100
0.1uF
TEST
D
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
2
4
6
8
10
12
14
SW SMD-8
S5
JTAG-14
1
3
5
7
9
11
13
J20
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
VSS
RST
TEST
0402
R118
330ohm
E
C
EVM PCB Schematics
Date:
Size
A
Title
D
Tuesday, September 16, 2014
Document Number
DS90UBUH948_940-Q1EVM
External MSP430 Controller
Sheet
7
E
of
Put RST switch at the bottom edge of the board. Mark down every Netname to the position
DIP20 SOCKET - MSP430G2403IN20
1
2
3
4
5
6
7
8
9
10
VDD33
2
1
VSS
VSS
VDD33
2
1
{3,4,5,6}
VSS
{5,6} VDD33
1
2
2
1
B
VSS
1 2 3 4 5 6 7 8
VSS
O
N
VSS
2
1
A
8
Rev
1E
1
2
3
4
www.ti.com
Appendix A
35
Appendix B
SNLU162 – October 2014
Board Layout
Board Layers
ART FILM - 01_TOP
ART FILM - 02_GND
ART FILM - 01_TOP
ART FILM - 02_GND
Figure 1. Top Layer
36
Board Layout
Figure 2. Ground Layer
SNLU162 – October 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Appendix B
www.ti.com
ART FILM - 03_POWER
ART FILM - 04_BOTTOM
ART FILM - 03_POWER
ART FILM - 04_BOTTOM
Figure 3. Power Layer
SNLU162 – October 2014
Submit Documentation Feedback
Figure 4. Bottom Layer
Board Layout
Copyright © 2014, Texas Instruments Incorporated
37
Appendix B
www.ti.com
ART FILM - BOTTOM-SILK
ART FILM - TOP-SILK
ART FILM - TOP-SILK
ART FILM - BOTTOM-SILK
Figure 5. Top Silkscreen
38
Board Layout
Figure 6. Bottom Silkscreen
SNLU162 – October 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Appendix B
ART FILM - FAB
ART FILM - FAB
www.ti.com
SNLU162 – October 2014
Submit Documentation Feedback
Board Layout
Copyright © 2014, Texas Instruments Incorporated
39
STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Copyright © 2015, Texas Instruments Incorporated
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