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Texas Instruments TPD1S514EVM (Rev. A) User guides
User's Guide
SLVUA31A – March 2014 – Revised May 2014
TPD1S514-1EVM
This user's guide describes the characteristics, operation, and use of the TPD1S514-1EVM evaluation
module (EVM). This EVM includes 4 TPD1S514-1’s in various configurations for testing. One TPD1S514-1
is configured with pin-outs and one TPD1S514-1 is configured with USB 2.0 Type A connectors for
throughput analysis. This user's guide includes setup instructions, schematic diagrams, a bill of materials,
and printed-circuit board layout drawings for the EVM.
.
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1
Introduction
1
2
3
4
5
www.ti.com
Contents
Introduction ...................................................................................................................
Board Setup ..................................................................................................................
2.1
U1 .....................................................................................................................
2.2
U2 .....................................................................................................................
Schematics ...................................................................................................................
Board Layout .................................................................................................................
Bill of Materials ...............................................................................................................
2
2
2
4
5
6
8
List of Figures
1
TPD1S514-1 Board Configuration for U1 ................................................................................. 3
2
TPD1S514 Board Configuration for U2 ................................................................................... 4
3
TPD1S514-1EVM Schematic
4
5
6
7
..............................................................................................
Top Layer Copper ...........................................................................................................
Second Layer Copper .......................................................................................................
Layer 3 Copper...............................................................................................................
Bottom Layer Copper........................................................................................................
5
6
6
6
6
List of Tables
1
1
EVM Configuration........................................................................................................... 2
2
Bill of Materials ............................................................................................................... 8
Introduction
Texas Instrument’s TPD1S514-1 evaluation module helps designers evaluate the operation and
performance of the TPD1S514-1 device. The TPD1S514-1 is a single-chip solution for USB connector’s
VBUS line protection. The bi-directional nFET switch ensures safe current flow in both charging and host
mode while protecting the internal system circuits from any over-voltage conditions at the VBUS_CON pin. On
the VBUS_CON pin, this device can handle over-voltage protection up to 30 V. After the EN pin toggles low,
the TPD1S514-1 waits 21 ms before turning ON the nFET through a startup delay. VBUS_POWER pin
indicates the nFET is completely turned ON.
Table 1. EVM Configuration
2
Reference Designator
TI Part Number
U1
TPD1S514-1
Configuration
Surge
U2 and U3
TPD1S514-1 and TPD3E001
Surge and ESD
Board Setup
This section describes the intended use of the TPD1S514-1EVM. A generalized outline of the procedure
given in IEC-61000-4-5 is described here. IEC-61000-4-5 should be referred to for a more specific testing
outline. Connect +5V and GND during any tests.
2.1
U1
TPD1S514-1 (U1) is pinned out to allow evaluating device performance during normal operating
conditions as well as during surge events. VBUS_CON is J1 and VBUS_SYS is J2. A 3-pin header (JP2) allows
shunting the EN pin on or off. Test points allow monitoring of VBUS_CON, VBUS_SYS, and
VBUS_POWER. TPD1S514-1 can pass up to 3.5 A continuous current from VBUS_CON to VBUS_SYS.
RDYN can be measured under these conditions using the test points VBUS_CON and VBUS_SYS, where
RDYN = IVBUS/(VVBUS_CON – VVBUS_SYS).
2
TPD1S514-1EVM
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Board Setup
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Surge can be injected onto VBUS_CON using J1. Over Voltage Protection (OVP) and Under Voltage Lockout
(UVLO) can be measured by sweeping 0 V - 30 V on VBUS_CONN and measuring at the three test
points. VBUS_SYS should have a load typical to the expected operational condition.
Figure 1. TPD1S514-1 Board Configuration for U1
Timing measurements should be performed after removal of C1, C2, and C3.
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3
Board Setup
2.2
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U2
Figure 2. TPD1S514 Board Configuration for U2
A pass through USB2.0 port is included for system level testing. The female USB connector (USB1) is the
“Connector” side of TPD1S514-1 and a male USB connector (USB2) is the “System” side. ESD protection
has been added to the Hi-Speed data lines and ID pin in the form of TPD3E001DRL to complete the port
protection example scheme.
Surge can be injected into VBUS_CON using J3.
A 3-pin header (JP2) allows shunting the EN pin on or off. Test points allow monitoring of VBUS_CON,
VBUS_SYS, and VBUS_POWER.
4
TPD1S514-1EVM
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Schematics
www.ti.com
3
Schematics
+5V
TP8
J1
TP1
JP1
TP2
1
OFF
TP3
U1
B3
C2
C3
2
EN
C1
3
ON
1uF
VBUS_CON
VBUS_CON
VBUS_CON
J2
A2
A3
B2
VBUS_SYS
VBUS_SYS
VBUS_SYS
C2
A1
EN
C1
A4
B4
C4
GND
GND
GND
GND
JP2
C5
1µF
TPD1S514-1YZ
1
OFF
2.2uF
B1
VBUS_POWER
2
EN
TP5
3
ON
TP6
TP4
U2
B3
C2
C3
VBUS_CON
VBUS_CON
VBUS_CON
VBUS_SYS
VBUS_SYS
VBUS_SYS
A2
A3
B2
C3
2.2uF
A1
EN
VBUS_POWER
GND
GND
GND
GND
J3
B1
C1
A4
B4
C4
C6
1µF
8
6
1
5
USB1
7
5
TPD1S514-1YZ
USB2
1
2
USB_DATA_N
2
3
USB_DATA_P
3
4
4
6
U3
5
VCC
IO1
IO2
4
IO3
GND
1
2
3
C4
1uF
TP7
TPD3E001DRLR
PS2
Figure 3. TPD1S514-1EVM Schematic
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5
Board Layout
4
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Board Layout
This section provides the TPD1S514-1EVM board layout. TPD1S514-1EVM is a 4-layer board of FR-4 at
0.062" thickness, with ½ oz. copper outer layers and 1 oz. copper inner layers.
Figure 4. Top Layer Copper
6
Figure 5. Second Layer Copper
TPD1S514-1EVM
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Board Layout
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Figure 6. Layer 3 Copper
Figure 7. Bottom Layer Copper
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7
Bill of Materials
5
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Bill of Materials
Table 2. Bill of Materials
Designator
Quantity
Value
Description
Package
Reference
Part Number
Manufacturer
C1, C4, C5, C6
4
1µF
CAP, CERM, 1µF, 25V, ±10%, X7R, 1206
1206
12063C105KAT2A
AVX
C2, C3
2
2.2µF
CAP, CERM, 2.2µF, 100V, ±10%, X7R, 1210
1210
GRM32ER72A225
KA35L
MuRata
H1, H2, H3, H4
4
Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead
Screw
NY PMS 440 0025
PH
B&F Fastener
Supply
H5, H6, H7, H8
4
Standoff, Hex, 0.5"L #4-40 Nylon
Standoff
1902C
Keystone
J1, J2, J3, PS2
4
Standard Banana Jack, Uninsulated, 5.5mm
Keystone_575-4
575-4
Keystone
JP1, JP2
2
PEC03SAAN
Header, Male 3-pin, 100mil spacing,
0.100 inch x 3
PEC03SAAN
Sullins
SH-J1A, SH-J2A
2
1x2
Shunt, 100mil, Gold plated, Black
Shunt
969102-0000-DA
3M
TP1, TP2, TP3,
TP4, TP5, TP6,
TP8
7
Red
Test Point, Miniature, Red, TH
Red Miniature
Testpoint
5000
Keystone
TP7
1
Black
Test Point, Multipurpose, Black, TH
Black Multipurpose
Testpoint
5011
Keystone
U1, U2
2
USB Charger Over Voltage, Surge and ESD Protection for
VBUS_CON Pin, YZ0012AFAV
YZ0012AFAV
TPD1S514-1YZ
Texas Instruments
U3
1
IC, LOW-CAPACITANCE 3-CHANNEL ±15-kV ESDPROTECTION ARRAY FOR HIGH-SPEED DATA
INTERFACES
SOP-5 (DRL)
TPD3E001DRL
Texas Instruments
USB1
1
Connector, Receptacle, USB TYPE A, 4POS SMD
USB TYPE A
CONNECTOR
RECEPTACLE
4POS SMD
896-43-004-00000000
Mill-Max
USB2
1
Connector, USB Type A, 4POS R/A, SMD
USB Type A right
angle
48037-1000
Molex
8
TPD3E001DRLR
TPD1S514-1EVM
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