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Texas Instruments TLK3132 2-Channel Multi-Rate Transceiver EVM User guides
User’s Guide Rev 0.1
September 2008
TLK3132 2-Channel Multi-Rate Transceiver Evaluation
Module (EVM) Users’ Guide
ABSTRACT
This User’s Guide describes the usage and construction of the TLK3132 evaluation module
(EVM). This document provides guidance on proper use by showing some device configurations
and test modes. In addition, design, layout and schematic information is provided to the
customer. Information in this guide can be used to assist the customer in choosing the optimal
design methods and materials in designing a complete system.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy
and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at own expense will be required to take whatever
measures may be required to correct this interference.
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Contents
Introduction............................................................................................................................................. 4
TLK3132 EVM Kit Contents.................................................................................................................... 5
Power ....................................................................................................................................................... 6
Power Monitoring LEDs ......................................................................................................................... 9
Control Signals ..................................................................................................................................... 12
MDIO ...................................................................................................................................................... 15
JTAG ...................................................................................................................................................... 16
Reset ...................................................................................................................................................... 17
Parallel Signals ..................................................................................................................................... 18
Jitter Cleaner External Loop Filter ...................................................................................................... 20
Peripheral Ports .................................................................................................................................... 22
Gigabit Ethernet Mode (RGMII) Test and Setup Configuration ........................................................ 23
Schematics............................................................................................................................................ 27
Board Layouts....................................................................................................................................... 47
Revision History ................................................................................................................................... 60
Figures
Figure 1. TLK3132 EVM Power Source Selection Example.....................................................................6
Figure 2. TLK3132 EVM VDDM Voltage Source Selection.......................................................................6
Figure 3. TLK3132 EVM VDDM Voltage Source Selection.......................................................................7
Figure 4. TLK3132 EVM Regulator Margin Selection ...............................................................................7
Figure 5. TLK3132 EVM Voltage Monitor LED Enabled Example ...........................................................9
Figure 6. TLK3132 EVM Voltage Monitor LED Disabled Example ........................................................10
Figure 7. TLK3132 EVM Voltage Monitor LED Connected Directly to Plane Example........................10
Figure 8. Control Connectors (JMP16, JMP17, JMP21, JMP22, JMP27, JMP28, JMP30, JMP31) ......12
Figure 9. TLK3132 EVM MDIO Connector (JMP29) ................................................................................15
Figure 10.
TLK3132 EVM JTAG Connector (JMP32).............................................................................16
Figure 11.
RESET Switch (SW1, JMP10, or JMP11)..............................................................................17
Figure 12.
Parallel Signal Header Block Diagram .................................................................................18
Figure 13.
Parallel Loopback Example ..................................................................................................18
Figure 14.
TXD Static Clock Data Pattern Example ..............................................................................19
Figure 15.
RXCLK Parallel Loop Back with Static Data Pattern Example ..........................................19
Figure 16.
Jitter Cleaner Loop Filter Default Configuration.................................................................20
Figure 17.
Jitter Cleaner Loop Filter Alternative Configuration ..........................................................21
Figure 18.
Example TLK3132 EVM Test Configuration – Gigabit Ethernet Mode (RGMII) Serial
Loopback ................................................................................................................................................25
Figure 19.
Example TLK3132 EVM Test Configuration – Gigabit Ethernet Mode (RGMII) Parallel
Loopback ................................................................................................................................................26
Figure 20.
TLK3132 EVM Schematic, Sheet 1 Cover Page and Index.................................................27
Figure 21.
TLK3132 EVM Schematic, Sheet 2 Device Power and Ground..........................................28
Figure 22.
TLK3132 EVM Schematic, Sheet 3 Global Signals .............................................................29
Figure 23.
TLK3132 EVM Schematic, Sheet 4 High Speed Differential...............................................30
Figure 24.
TLK3132 EVM Schematic, Sheet 5 Jitter Cleaner Clock.....................................................31
Figure 25.
TLK3132 EVM Schematic, Sheet 6 JTAG and MDIO ...........................................................32
Figure 26.
TLK3132 EVM Schematic, Sheet 7 TX and RX Data Lines .................................................33
Figure 27.
TLK3132 EVM Schematic, Sheet 8 TX/RX Clocks and Control..........................................34
Figure 28.
TLK3132 EVM Schematic, Sheet 9 Power Regulation ........................................................35
Figure 29.
TLK3132 EVM Schematic, Sheet 10 Power Distribution ....................................................36
Figure 30.
TLK3132 EVM Schematic, Sheet 11 1P2V and VJIT Supply LEDs ....................................37
Figure 31.
TLK3132 EVM Schematic, Sheet 12 1P5V and 1P8V Supply LEDs ...................................38
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Figure 32.
TLK3132 EVM Schematic, Sheet 13 2P5V and 5V Supply LEDs........................................39
Figure 33.
TLK3132 EVM Schematic, Sheet 14 VDDM Supply LEDs...................................................40
Figure 34.
TLK3132 EVM Schematic, Sheet 15 VDDR Supply LEDs ...................................................41
Figure 35.
TLK3132 EVM Schematic, Sheet 16 VREF Supply LEDs....................................................42
Figure 36.
TLK3132 EVM Schematic, Sheet 17 Peripheral Ports.........................................................43
Figure 37.
TLK3132 EVM Layout, Top Signal (Layer 1) ........................................................................47
Figure 38.
TLK3132 EVM Layout, Internal Ground (Layers 2,4,6,8,10) ..............................................48
Figure 39.
TLK3132 EVM Layout, Internal Power (Layer 3).................................................................49
Figure 40.
TLK3132 EVM Layout, Internal Signal (Layer 5).................................................................50
Figure 41.
TLK3132 EVM Layout, Internal Signal (Layer 7)..................................................................51
Figure 42.
TLK3132 EVM Layout, Internal Power (Layer 9)..................................................................52
Figure 43.
TLK3132 EVM Layout, Internal Ground and Power (Layer 11) .........................................53
Figure 44.
TLK3132 EVM Layout, Internal Signal (Layer 12)................................................................54
Figure 45.
TLK3132 EVM Layout, Internal Ground (Layers 13,15,17) .................................................55
Figure 46.
TLK3132 EVM Layout, Internal Signal (Layer 14)................................................................56
Figure 47.
TLK3132 EVM Layout, Internal Power (Layer 16)................................................................57
TLK3132 EVM Layout, Bottom Signal (Layer 18) .......................................................................................58
TLK3132 EVM Layer Construction ..............................................................................................................59
Table 1.
Tables
TLK3132 EVM Bill of Materials.................................................................................................44
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
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3
Introduction
The Texas Instruments (TI™) TLK3132 SerDes evaluation module (EVM) board is used to
evaluate the functionality and the performance of TLK3132 2-Channel Multi-Rate Transceiver
device (196-ball BGA). The TLK3132 is a flexible two channel independently configurable serial
transceiver that can be configured to be compliant with the 1000Base-X 1Gbps Ethernet
Specification and will also support 1X/2X/10X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI
(x1/x2/x4) data rates. Many common applications may be enabled by way of externally available
control pins and detailed control of the TLK3132 on a per channel basis is available by way of
accessing a register space of control bits available through a two-wire access port called the
1
Management Data Input/Output (MDIO) interface.
EVM PCB and High-speed Design Considerations
The board can be used to evaluate device parameters in addition to acting as a guide for highspeed board layout. As the frequency of operation increases, the board designer must take
special care to ensure that the highest signal integrity is maintained. To achieve this, the board's
impedance is controlled to 50 Ω for both the high-speed differential serial and low-speed parallel
data and clock connections. Vias are minimized and, when necessary, are designed to minimize
impedance discontinuities along the transmission line. Since the board contains both, serial and
parallel transmission lines, care was taken also to control trace length mismatch (board skew) to
less than +/- 0.5MIL.
Overall, the board layout is designed and optimized to support high-speed operation. Thus,
understanding impedance control and transmission line effects are crucial when designing highspeed boards. Some of the advanced features offered by this board include:
•
PCB (printed circuit board) is designed for optimal high-speed signal integrity.
•
SMP and parallel header fixtures are easily connected to test equipment.
•
All input/output signals are accessible for rapid prototyping.
•
The entire board can be powered from a single 5V power supply where the power planes
can be supplied through on-board regulators or through separate banana jacks for isolation.
•
On-board capacitors provide AC coupling of high-speed transmit and receive signals.
•
External parallel loop-back function can be achieved easily using simple 0.1 inch jumpers.
•
Entire Board can operate from a single 5V power supply, or from individual power supplies.
•
Voltage Monitoring LED circuits provide quick indication that the voltage is within
specification.
1
The MDIO register map is located within the TLK3132 2 Channel Multi-Rate Transceiver datasheet.
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TLK3132 EVM Kit Contents
The TLK3132 EVM kit contains the following:
•
TLK3132 EVM board
•
TLK3132 EVM User’s Guide (this document)
•
TLK3132 2-Channel Multi-Rate Transceiver datasheet
•
MDIO Interface EVM
•
MDIO Interface EVM Documentation
•
RS-232 Cable
•
20-conductor MDIO Ribbon Cable
•
CD-ROM Containing MDIO Software
•
10 3-Foot SMA to SMP cables
•
4 1-Foot SMP to SMP cables
•
5V DC Transformer Power Supply
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Power
The TLK3132 EVM can be operated off of a single 5V Power Supply utilizing the on-board
voltage regulators to generate the voltages required to correctly operate the TLK3132, off of
individual 1.2V, 1.5V or 1.8V, 2.5V, and 5V Power supplies, or a combination of both regulators
and separate individual supplies.
To modify your power supply configuration between either all Individual Supplies, all on-board
regulators, or a combination of both, simply change the jumper position on the appropriate power
supply headers (JMP130, JMP131, and JMP132) selecting either the “BANANA JACK” or the
“REG” pin in combination with the center pin. The following figure shows how to use the onboard regulators for the 1.5V or 1.8V and 2.5V supply rails, and an individual power supply
connected to the 1.2V Banana Jack (P2). The 5V power supply is required for operation of the
LEDs on this board even if you are not using the on-board voltage regulators and can be
provided from a lab power supply through the Banana Jack (P1) or through the supplied 5V DC
Transformer. Changing the jumper location on JMP121 will change the 5V power supply source.
Figure 1.
TLK3132 EVM Power Source Selection Example
The MDIO power supply VDDM can be operated off of either 1.2V or 2.5V depending upon your
specific setup. If you are using the supplied MDIO controller board that came with this
EVM kit, the 2.5V setting must be selected on the VDDM Power Select Header (JMP133).
Figure 2.
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TLK3132 EVM VDDM Voltage Source Selection
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
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The PTH05010WAS voltage regulators included on the TLK3132 EVM are adjustable and are
set with a single external resistor. Separate regulators have been provided and set to output
1.2V and 2.5V because both voltages are required simultaneously. However, since 1.5V and
1.8V are not necessarily required simultaneously, a single regulator has been configured to
provide both of those voltages, although not at the same time depending upon the jumper
position on JMP115 shown in the following figure. JMP125 selects between the 1.5V set resistor
and the 1.8V set resistor and connects one or the other to the Voltage Adjust pin of regulator
U63.
Figure 3.
TLK3132 EVM VDDM Voltage Source Selection
JMP125
JMP125
1p5V
1p5V
VADJ
VADJ
1p8V
1p8V
1.5V
SELECTED
1.8V
SELECTED
The PTH05010WAS voltage regulators are also equipped with a +/- 5% selectable Margin
Control allowing easy testing of the device near the min/max voltage limits specified in the
datasheet. Place the jumper position to either the “+5%”, “-5%”, or “NOM” positions keeping the
center pin in common as demonstrated in the following figure.
Figure 4.
TLK3132 EVM Regulator Margin Selection
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When the on-board regulators are not being used and independent power supplies are being
used instead, i.e. the case of a voltage tolerance test, the on-board regulators should be disabled
to prevent the regulator’s voltage sense line from trying to regulate the voltage supplied through
the banana jack and not from its own output. This is accomplished by placing a short on the
headers (JMP122, JMP124, and JMP127) labeled “DISABLE”. The remote sense feature is not
designed to compensate for the forward drop of non-linear or frequency dependent components
that may be placed in series with the converter output. Examples include OR-ing diodes, filter
inductors, ferrite beads, and fuses. When these components are enclosed by the remote sense
connection they are effectively placed inside the regulation control loop, which can adversely
affect the stability of the regulator. A large 0 ohm resistor has been installed at the voltage
entrance point of each power plane and can be replaced with a ferrite bead of desired. In this
situation, the 0 ohm resistors on the sense lines can be interchanged to connect the sense line
directly to its output and eliminate the additional components that could otherwise create
instability on the regulator’s output. For the 1.2V regulator, the R350 0 ohm resistor should be
removed and the R351 populated with a 0 ohm resistor. For the 1.5V or 1.8V regulator, R343
should be removed and placed on R345, and similarly R353 should be moved to R355 for the
2.5V regulator.
The VREF plane is sourced through a Voltage Divider providing half of the voltage on the 1p5/8V
plane. The VDDQ and VDDR power pins of the TLK3132 can both be operated off of either 1.5V
or 1.8V with VREF being half of whatever voltage is on the VDDQ pins. The VREF plane can be
powered through the plane monitoring header (JMP7) and removing the 0 ohm resistor (R347)
although this is not recommended. A separate VDDR plane has been added as there is no
relationship between the VDDR pin and the VDDQ pins, however, the VDDR plane is sourced
through a 0 ohm resistor (R344) from the voltage on the 1p5/8V plane that provides power to the
VDDQ pins. This resistor can be replaced with a ferrite bead or removed completely and an
external supply can be connected to the VDDR Header (JMP9) in the case different voltages are
desired on the two planes.
Furthermore, for more accurate current readings the PULLUP_EN Jumpers on all control pin
headers can be removed quickly disconnecting the pullup resistors from the voltage plane.
However, the removal of the PULLUP_EN jumpers will also require manual high/low control of
every control pins
A dedicated LDO 1.2V Regulator (U65) is used to power the Jitter Cleaner Power Plane and
should be considered for the end application. Due to the nature of the PLL circuitry, poor
performance could result from noise on the VDDA_VCO, VDDA_CP, VDD_CML, VDD_PLL
power and VSSA_VCO, VSSA_CP, VSS_CML, VSS_PLL ground pins. Separating the source
and using an Low Dropout Regulator instead of a switching regulator will provide the best
performance of the Jitter Cleaner Circuit. However, the performance of the device without this
LDO can be observed by removing the R340 0 ohm resistor and installing a Ferrite Bead or
Inductor of your choice on either of the L2 and L3 place holder footprints. When using a
switching regulator and/or trying to share a common source for the Jitter Cleaner Power pins and
the other 1.2V Digital Core power pins, noise filtering and suppression is crucial because all
digital and switching noise below the PLL cutoff frequency will be passed directly through to the
chip providing additional unwanted jitter. Additional de-coupling capacitors have been supplied
on this plane to facilitate the evaluation of this device with the power sources that may require
more or less bulk plane capacitance in order to achieve the desired level of performance.
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Power Monitoring LEDs
Each plane of the TLK3132 EVM has been equipped with a Voltage Monitoring circuit that will
monitor the voltage on the plane and light the LEDs when the voltage is within the min/max
datasheet limits for that power supply. A precision TI Voltage Reference chip is used along with
0.1% precision resistors setting min and max reference levels providing a detection circuit that is
accurate to approximately +/- 10mV. The LEDs should be used as a basic indication of the
status of power on the board being within the acceptable min/max limits given in the datasheet,
and not as a precise measurement tool as some LED circuits may turn off at slightly different
voltages when approaching the limits due to the manufacturing tolerances and available
component values.
The voltage monitor circuits can also be bypassed and the LEDs driven directly from the voltage
on the individual planes such as when performing voltage tolerance tests. Instead of being lit
only when the voltage on the plane is within the min/max range, the LED will be lit when the
voltage is greater than the voltage needed to turn on the LED drive circuit’s NPN transistor,
allowing current to flow, and the LED to be lit from the 5V source. In the Direct Connect mode,
the base resistors has been given extra margin to allow the LEDs to light when the voltage on
the plane is a little below the minimum limit of that supply in order to provide a LED indicator of
power on the plane during voltage tolerance tests near the lower supply limits.
Figure 5.
TLK3132 EVM Voltage Monitor LED Enabled Example
Placing the jumper on the ENABLE side of the Voltage Monitor Enable/Disable header connects
the power plane to the input of the voltage monitoring circuit. This input is high impedance and
will not load down the power source providing the voltage to the plane.
Placing the header on the MONITOR side of the LED Monitor/Direct Connect selection header
connects the LED drive circuit to the output of the Voltage Monitor circuit causing the LED to be
lit only when the voltage is within the acceptable range.
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
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Figure 6.
TLK3132 EVM Voltage Monitor LED Disabled Example
Placing the jumper on the DISABLE side of the Voltage Monitor Enable/Disable header
disconnects the power plane to the input of the voltage monitoring circuit and instead ties the
input to GND. This prevents the output of the Voltage Monitoring Circuit from floating and
possibly causing the LED to flicker during contact with the board.
Placing the jumper on the MONITOR side of the LED Monitor/Direct Connect selection header
connects the LED drive circuit to the output of the Voltage Monitor circuit causing the LED to be
off since the voltage monitor circuit will sense that the plane voltage is GND which is less than
the acceptable plane voltage.
Figure 7.
TLK3132 EVM Voltage Monitor LED Connected Directly to Plane Example
JUMPER POSITION DOES
NOT MATTER. THIS IS
MAINLY FOR THE
MONITORING CIRCUIT
JMP77
JMP78
ENABLE
DIRECT
LED
LED
DISABLE
MONITOR
1.2V LED CONNECTED DIRECTLY TO THE POWER PLANE
(MONITOR CIRCUIT BYPASSED)
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Placing the jumper on the DIRECT side of the LED Monitor/Direct Connect selection header
connects the LED drive circuit to the power plane itself causing the LED to be lit when the
voltage is great enough to cause current to flow through the LED drive circuit. This LED
configuration has been designed to be used when pushing the lower limits of the acceptable
voltage range to continue to provide an indicator that power is on the plane, however without
regards to what that voltage may actually be.
The jumper on the Voltage Monitor Enable/Disable header does not matter as this is only the
input to the voltage monitor circuit which has been bypassed when the LED drive circuit is
connected directly to the power plane itself.
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
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Control Signals
All of the external control pins on the TLK3132 EVM have been consolidated to a single location
on the board and broken out into several header blocks for easier reference. LEDs have been
added to the GPO[0:4] lines in addition to the headers for scope probes, to allow easy monitoring
of the High/Low value on the line. The LED will be ON when the line is a Logic High, and the
LED will be OFF when the line is a Logic Low.
Figure 8.
12
Control Connectors (JMP16, JMP17, JMP21, JMP22, JMP27, JMP28, JMP30, JMP31)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
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Control Signal Pin Description:
VCO_TL_TST: This pin is the VCO Testability Input and should be grounded in the application.
TST_OUT: This is the Jitter Cleaner Testability Pin.
(unconnected) in the System Application.
This signal should be left open
GPO[4:0]: These are General Purpose Outputs and must be left open (unconnected) in the
System Application.
GPI1: This is the General Purpose Input and must be Grounded in the System Application.
AMUX0: This is the SERDES Analog Mux 0 TX pin and must be open (unconnected) in the
System Application.
AMUX1: This is the SERDES Analog Mux 1 RX pin and must be open (unconnected) in the
System Application.
TESTEN: This is the Test Mode Enable Input pin and must be Grounded in the System
Application.
CODE: This signal is logically OR’d with the PCS_EN register bit (Register Bit 17.3).
RGMII/GMII applications can either tie this input signal high which is preferred, or tie this signal
low and program the PCS_EN 17.3 register bit after a device reset to high if CODE is tied off low.
Non RGMII/GMII applications must tie this input signal low.
PRBS_EN: This is the PRBS Enable Pin. When this pin is asserted HIGH, the internal PRBS
generator and comparator circuits are enabled on the transmit and receive data paths of all
channels. The PRBS results for each channel can be read through MDIO counters. Primary
chip output signals GPO1/GPO0 remain low during PRBS testing when the input serial stream
PRBS pattern is correct, and pulse high when PRBS errors are detected on the input serial
stream on a per channel basis.
GPO1: Contains the Channel 1 PRBS currently passing (when low) indication.
GPO0: Contains the Channel 0 PRBS currently passing (when low) indication.
An external loopback connection (via external cables) is required during PRBS
testing.
PRBS 27-1 is transmitted on each transmit channel serial output, and compared
on each receive channel serial input.
SLOOP: This pin is the Serial Loop Enable pin. When SLOOP is asserted HIGH, the serial
input from each channel is internally looped back to that channel’s serial output, making that
channel a serial repeater. In device configurations where clock tolerance compensation is not
performed in the transmit direction, there are two options for error free serial loopback operation:
1) Frequency lock (0 ppm) the incoming serial data rate to the local reference
clock device input.
2) Provision the TX SERDES REFCLK to run from a jitter cleaned version of the
RX SERDES RXBCLK (Receive Byte Clock).
PLOOP: This pin is the Parallel Loop Enable pin. When PLOOP is asserted HIGH, the serial
output for each channel is internally looped back to its serial input so that the transmit parallel
interface input data is output onto the receive parallel interface.
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SPEED[1:0]: These are the Speed Selection Pins and put both channels of the TLK3132 into
one of the three supported (full/half/quarter) channel operation speeds.
00 – BothChannels in Full Rate mode
01 – BothChannels in Half Rate mode
10 – Both Channels in Quarter Rate mode
11 – Software Selectable Rate
In the Software selectable rate mode, the rate for each channel may be
configured independently by the MDIO interface.
The SPEED[1:0] inputs control both RX and TX directions for both channels.
Please see Appendix A of the TLK3132 Datasheet for further information on
speed selection (full/half/quarter) for proper settings as a function of the
application mode and reference clock frequency.
Please note that if these pins are not configured on the application board to
select “Software Selectable Rate”, then the internal speed register bits
cannot be used to control the rate settings, and the full/half/quarter rate
selection is fixed.
ENABLE: This is the Device Enable pin. When ENABLE is held low, the device is in a low
power state. When ENABLE is high the device operates normally. A hard or soft reset must
be applied after a change of state occurs on this input signal.
PRTAD[4:0]: These are the Port Address Assignment Pins and are used to select the Device
ID/Port ID in Clause 22 MDIO mode.
PRTAD[4:1] selects a block of two sequential Clause 22 port addresses. Each
channel is implemented as a different port address, and can be accessed by
setting the appropriate port address field within the Clause 22 MDIO transaction.
PRTAD[0] is not used functionally, but is needed for device testability with other
devices in the family of products.
Channel 0 responds to port address 0 within the block of two port addresses.
Channel 1 responds to port address 1 within the block of two port addresses.
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MDIO
The TLK3132 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet Specification. The MDIO allows register-based management and control of
the serial links. Normal operation of the TLK3132 is possible without the use of this interface, however,
some additional features are accessible only through this interface.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device ID and port address are determined by control pins PRTAD[4:0
In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2
individual channels in TLK3132 are classified as 2 different ports. So for any PRTAD[4:1] value there
will be 2 ports per TLK3132. The TLK3132 will respond if the 4 MSB’s of PHY address field on MDIO
protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which
channel/port within the TLK3132 to respond to.
If PA[0] = 1’b0, TLK3132’s Channel 0 will respond.
If PA[0] = 1’b1, TLK3132’s Channel 1 will respond.
Write transactions which address an invalid register or read only registers will be ignored.
transactions of invalid registers will return a “0”.
Read
The bi-directional MDIO pin is pulled up to 1.2V or 2.5V (VDDM) with a 1.5k Ω resistor as per the MDIO
Standard.
Figure 9.
TLK3132 EVM MDIO Connector (JMP29)
MDIO
GND
MDC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
JMP29
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
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JTAG
The EVM also provides a separate connector to support the full five-pin JTAG interface of the TLK3132
as defined in IEEE 1149.1 for manufacturing tests.
TDI: This pin is the JTAG Input Data pin and is used to serially shift test data and test
instructions into the device during the operation of the test port.
TDO: This pin is the JTAG Output Data pin and is used to serially shift test data and test
instructions out of the device during operation of the test port. When the JTAG port is not in use,
TDO is in a high impedance state.
TMS: This pin is the JTAG Mode Select pin and is used to control the state of the internal testport controller.
TCK: This is the JTAG Clock pin and is used to clock state information and test data into and
out of the device during the operation of the test port.
TRST_N: This is the JTAG Test Reset pin and is used to reset the JTAG logic into system
operational mode. NOTE: TRST_N should be tied low when the JTAG port is not in use and
during normal operation of the port as shown in the following figure.
Figure 10. TLK3132 EVM JTAG Connector (JMP32)
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Reset
The TLK3132 EVM comes configured for Manual Reset operations involving the Pushbutton
Reset Switch (SW1). When switch SW1 is pressed, the TLK3132 device RESET pin (RST_N)
goes LOW and the entire TLK3132 device is reinitialized. A TI TPS3125J18 Ultra Low Voltage
Processor Supervisory Circuit is used to control the Reset line. During power-on, /RESET pin of
U2 is asserted when the supply voltage becomes higher than 0.75V. Thereafter, the supply
voltage supervisor monitors the voltage and keeps /RESET output active as long as the Voltage
remains below the threshold voltage (VIT). An internal timer delays the return of the output to the
inactive state (high) to ensure proper system reset. The delay time, td=180ms, starts after the
voltage has risen above the threshold voltage (VIT).
There is also a manual reset input to the supervisory circuit, /MR, which accepts the input from
the pushbutton switch SW1. A low level at /MR causes /RESET to become active, thus resetting
the TLK3132 device whenever the pushbutton RESET is pressed. By placing a jumper on
JMP15, the Manual Reset (/MR) is tied hard to ground causing the TLK3132 to be held in a
constant state of Reset without the need to continually hold the Reset Pushbutton SW1. The
Supervisory circuit will release the Reset line to a HIGH 180mS (td) from the time the /MR line
becomes greater than the threshold voltage (VIT).
By removing the jumper from JMP14, the Supervised Reset Circuit is disconnected from the
RST_N line. Reset control from an external controller or piece of equipment can be connected
directly to pin 2 (RST_N) of JMP14 and a ground pin GND has been added to the JMP14 header
next to the RST_N pin to allow easy access for the return current on that cable.
Figure 11. RESET Switch (SW1, JMP10, or JMP11)
JMP15
MANUAL RESET
GND
RESET
RESET
D1
RESET
D2
SW1
U2
SUPERVISORY
CIRCUIT
R4
C43
R3
R1
JMP14
RESET BUTTON
RESET
GND
NOTE: The Jumper on JMP14 connecting RESET SW to RST_N must be connected as shown
in order to cause the TLK3132 to be reset and reinitialized If switch SW1 is pressed, the device
RESET pin (RST_N) goes LOW, the entire TLK3132 device is reinitialized.
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
17
Parallel Signals
The parallel signals on the TLK3132 EVM have been routed to a 0.1” header block that is
configured like the following figure. All RXD pins on header blocks RXD[7:0], RXD[15:8], as well
as all TXD pins on header blocks TXD[7:0], TXD[15:8], have matched trace lengths to
themselves +/- 0.5MIL.
Figure 12. Parallel Signal Header Block Diagram
Parallel Signal
Bit Number
7 6 5 4 3 2 1 0
( 6
12
18
24
30
36
42
Pin Numbers of
Outer Row
48 )
PWR
PWR
TXD_7..0
TXD_7..0
GND
TXD_7..0
TXD_7..0
RXD_7..0
RXD_7..0
GND
JMP2
Parallel Signal
Bit Number
PIN TYPE OF
ROW
GND
GND
( 1
7
13
19
25
31
37
43 )
7 6 5 4 3 2 1 0
Pin Numbers of
Outer Row
Parallel Loop back, shown in the following figure, can be easily implemented by placing Jumpers
on the RXD/TXD pins of the header. For example, placing a jumper on pins 2 and 3 of JMP2 will
loop back TXD7 to RXD7.
Figure 13. Parallel Loopback Example
7 6 5 4 3 2 1 0
PWR
PWR
TXD_7..0
TXD_7..0
GND
TXD_7..0
TXD_7..0
RXD_7..0
RXD_7..0
GND
JMP2
18
GND
PARALLEL
LOOPBACK
GND
7 6 5 4 3 2 1 0
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Additional GND and VDD pins have been added into the header block for several reasons. The
GND pins next to the RXD and TXD pins provide a convenient ground reference for a scope
probe or coax cables. The additional TXD row and VDD pins allow a static pattern to be driven
into the TXD bus by placing jumpers across either the TXD and VDD pins for a HIGH, or TXD
and GND pins for a LOW eliminating the need for cables during quick tests. The extra row of
TXD can also be used to monitor the signals on the TXD pins. The following figure shows a
clock pattern (01010101) on TXD[7:0].
Figure 14. TXD Static Clock Data Pattern Example
The Transmit Data Clocks and Receive Data Clocks are located in header block JMP4 with the
clock pins next to each other. These signals are the parallel side input and output clocks per
channel. During Parallel Loopback, the clocks can be jumpered together as shown in the
following diagram.
GND
TXCLK 1
TXCLK 0
GND
RXCLK 1
RXCLK 0
GND
GND
Figure 15. RXCLK Parallel Loop Back with Static Data Pattern Example
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
19
Jitter Cleaner External Loop Filter
The TLK3132 Jitter Cleaner requires an external loop filter be added to the board as described in
the TLK3132 Datasheet. Package size and placement of these 5 resistor and capacitor
components is critical and can affect the performance of the Jitter Cleaner circuit. These 5
components have been carefully placed directly under the TLK3132 Device using 0402
packages in order to minimize the trace length and size of the loop filter circuit, as well as reduce
the exposure to other signals that will couple unwanted noise into this circuit.
Figure 16. Jitter Cleaner Loop Filter Default Configuration
20
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
However, due to cost and manufacturing requirements, an external placement of these
components relative to the TLK3132 Ball Field as well as an increase in package size to 0603
devices may be required. For this reason, a second Loop Filter circuit has been installed on this
EVM, though not connected by default, to allow for the evaluation of the TLK3132 under these
requirements. To engage the 0603 sized loop filter that has been placed outside the TLK3132
ball field instead of the 0402 sized loop filter that is placed inside the ball field, simply remove the
following components (R44, R45, C57, C58, and C59) and install a 0-ohm 0201 resistor (or
create a solder short) on R327 and R328. Refer to sheet 5 of the TLK3132 EVM Schematics
located in the Schematics section of this document.
Figure 17. Jitter Cleaner Loop Filter Alternative Configuration
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
21
Peripheral Ports
The TLK3132 EVM can support 3 small peripheral boards which could contain any sort of
additional circuitry required for effective evaluation of the TLK3132 device. Examples of
additional circuitry that could be implemented would include a clock source such as an oscillator
with multiplier/divider chip, FPGA, CPLD, or even an optical module just to name a few. All of
the power rails (1.2V, 1.5/8V, 2.5V, 3.3V and 5V) have been provided to allow for minimal power
circuitry on the peripheral board itself as well as the global reset signal which is connected to the
TLK3132 Reset Pin. TI is developing a clock multiplier and divider peripheral board specifically
for use with the TLk3132 EVM which would be capable of providing practically any clock
frequency needed for operation of the TLK3132 device. However, it is not complete and ready
for distribution with the TLk3132 EVM. Refer to sheet 17 of the TLK3132 EVM Schematic
located in the Schematics section as well as the line item in the BOM for connector Part Number
information.
22
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Gigabit Ethernet Mode (RGMII) Test and Setup Configuration
The device reset requirements and setup procedure to configure the TLK3132 for Gigabit
Ethernet Mode (RGMII) is as follows:
*Note: All global registers must be accessed indirectly through Clause 22.
REFCLK frequency = 125 MHz, Serdes Data Rate = Half Rate, Mode = Transceiver, Edge Mode = Source Centered Mode,
RX_CLK[n] out = TXBCLK[n], Jitter Cleaner PLL Multiplier Ratio = 1X or Off
•
•
•
Device Pin Setting(s) – Pin settings allow for maximum software configurability.
o Ensure CODE input pin is Low.
o Ensure PLOOP input pin is Low.
o Ensure SLOOP input pin is Low.
o Ensure SPEED [1:0] input pins are both High.
o Ensure ENABLE input pin is High.
o Ensure PRBS_EN input pin is Low.
Reset Device
o Issue a hard or soft reset (RST_N asserted for at least 10 us -or- Write 1’b1 to 0.15)
Clock Configuration
o If using JCPLL (JCPLL 1X)
JCPLL Mux Settings (Figure 2 on page 3 of the TLK3132 Datasheet rev 0.19)
ƒ
Select REFCLK input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
•
If Differential REFCLK used – Write 2’b00 to 37120.15:14
ƒ
Write 2’b11 to 37120.13:12 to select differential REFCLKP/N as RXBYTECLK
ƒ
Write 4’b0000 to 37120.11:8 to select jitter cleaned clock for SERDES TX/RX.
ƒ
Write 2’b11 to 37120.7:6 to select differential REFCLKP/N as Delay Stopwatch clock input
ƒ
Write 2’b00 to 37120.5:4 to select jitter cleaned clock for HSTL VTP 2x
ƒ
Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output (per channel)
ƒ
Write 16’h0081 to 37126 to set Charge pump control
ƒ
Write 16’h00A0 to 37128 to set TXRX output divider
Clock Divide Settings (Table 132 on page 114 of the TLK3132 Datasheet rev 0.19)
ƒ
Write 7’b1000000 to 37124.14:8 to set REF_DIV to value of 1
ƒ
Write 1’b1 to 37124.15 REFDIV_EN to enable reference clock divider
ƒ
Write 7’h18 to 37124.6:0 to set FB_DIV to value of 24
ƒ
Write 1’b1 to 37124.7 FBDIV_EN to enable feedback divider
ƒ
Write 7’h18 to 37125.6:0 to set RXTX_DIV to value of 24
ƒ
Write 1’b1 to 37125.7 OUTDIV_EN to enable RXTX_DIV output divider
ƒ
Write 7’h0D to 37121.14:8 to set HSTL_DIV to value of 13
ƒ
Write 7’h06 to 37121.6:0 to set HSTL_DIV2 to value of 6
ƒ
Write 2’b11 to 36864.14:13 to set RX Loop Bandwidth
ƒ
Write 2’b11 to 36864.6:5 to set TX Loop Bandwidth
ƒ
Write 4’h0101 to 36864.11:8 to set MPY RX multiplier factor to 10
ƒ
Write 4’h0101 to 36864.3:0 to set MPY TX multiplier factor to 10
ƒ
Write 16’h5050 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
ƒ
Write 3’b000 to 37127.14:2 to set control bits for VCO tail current to 0
ƒ
Write 1’b1 to 37127.15 to enable Jitter Cleaner
ƒ
Wait 50 ms in order for JCPLL to lock
o
Else if using clock bypass mode (JCPLL Off)
JCPLL Mux Settings (Figure 2 on page 3 of the TLK3132 Datasheet rev 0.19)
ƒ
Select REFCLK input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
•
If Differential REFCLK used – Write 2’b00 to 37120.15:14
ƒ
Select RXBYTE_CLK (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 37120.13:12
•
If Differential REFCLK used – Write 2’b11 to 37120.13:12
ƒ
Select SERDES TX Reference Clock Input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
23
• If Differential REFCLK used – Write 2’b11 to 4/5.37120.11:10
Select SERDES RX Reference Clock Input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
•
If Differential REFCLK used – Write 2’b11 to 37120.9:8
ƒ
Select DELAY_CLK (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 37120.7:6
•
If Differential REFCLK used – Write 2’b11 to 37120.7:6
ƒ
Select HSTL_2X_CLK (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 37120.5:4
•
If Differential REFCLK used – Write 2’b11 to 37120.5:4
ƒ
Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output (per channel)
ƒ
Write 7’h04 to 37121.6:0 to set HSTL_DIV2 to value of 4.
ƒ
Write 15’h1515 to 36864.14:0 SERDES_PLL_CONFIG to set MPY RX/TX multiplier factor to 10
ƒ
Write 16’h5050 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
Mode Control (Table 2 on page 16 of the TLK3132 Datasheet rev 0.19)
o Write 1’b0 to 17.0 for RX source centered mode (per channel)
o Write 1’b0 to 17.1 for TX source centered mode (per channel)
o Write 1’b1 to 17.2 to enable 8B/10B encode decode functions (per channel)
o Write 1’b1 to 17.3 to enable 1000Base-X PCS TX & PCS RX functions (per channel)
o Write 1’b1 to 17.4 to set nibble order, LSB on rising edge, MSB on falling edge (per channel)
o Write 1’b1 to 17.5 to enable DDR data on TX/RX directions (per channel)
o Write 1’b0 to 17.6 to disable FC_PH overlay detection (per channel)
o Write 1’b1 to 17.7 to enable comma detection (per channel)
o Write 1’b0 to 17.9 to disable full DDR mode (per channel)
o Write 1’b0 to 16.8 to disable Farend Loop back (per channel)
o Write 1’b0 to 0.14 to disable loop back mode (per channel)
o Write 3’b111 to 36874.11:9 to set channel 0 TX swing setting amplitude to 1375 mVdfpp
o Write 1’b1 to 36874.8 to set channel 0 TX CM bit
o Write 3’b111 to 36876.11:9 to set channel 1 TX swing setting amplitude to 1375 mVdfpp
o Write 1’b1 to 36876.8 to set channel 1 TX CM bit
RX equalization settings
o Write 4’b0001 to 36866.15:12 to turn on adaptive equalization (4’b0000 is off)
o Write 4’b0001 to 36868.15:12 to turn on adaptive equalization (4’b0000 is off)
o Write 2’b01 to 36866,3:2 for AC coupled mode (2’b00 is DC coupled mode)
o Write 2’b01 to 36868.3:2 for AC coupled mode (2’b00 is DC coupled mode)
TX DLL offset
o Write 16’h0028 to 37888 TX0_DLL_CONTROL
o Write 16’h0028 to 37889 TX1_DLL_CONTROL
Poll Serdes PLL Status for Locked State
o Read 36891.4,0 SERDES_PLL_STATUS – PLL_LOCK_TX/RX
o Keep polling until both bits are high.
Issue Data path Reset
o Write 1’b1 to 16.11 (per channel)
Clear Latched Registers
o Read 1 PHY_STATUS_1 to clear (per channel)
o Read 18 PHY_RX_CTC_FIFO_STATUS to clear (per channel)
o Read 19 PHY_TX_CTC_FIFO_STATUS to clear (per channel)
o Read 28 PHY_CHANNEL_STATUS to clear (per channel)
o Read 36891 SERDES_PLL_STATUS to clear
ƒ
•
•
•
•
•
•
•
24
Operational Mode Status
o Read Verify 1.2 PHY_STATUS_1 – Link Status (1’b1) (per channel)
o Read Verify 18.15 PHY_RX_CTC_FIFO_STATUS – RX_CTC_Reset (1’b0) (per channel)
o Read Verify 19.15 PHY_TX_CTC_FIFO_STATUS – TX_FIFO_Reset_1Gx (1’b0) (per channel)
o Read Verify 28.13:12 PHY_CHANNEL_STATUS – Enc/Dec Invalid Code Word (2’b00) (per channel)
o Read Verify 36891.4 SERDES_PLL_STATUS – PLL_LOCK_RX (1’b1)
o Read Verify 36891.0 SERDES_PLL_STATUS – PLL_LOCK_TX (1’b1)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 18.
Example TLK3132 EVM Test Configuration – Gigabit Ethernet Mode (RGMII) Serial Loopback
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
25
Figure 19.
26
Example TLK3132 EVM Test Configuration – Gigabit Ethernet Mode (RGMII) Parallel Loopback
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Schematics
Figure 20. TLK3132 EVM Schematic, Sheet 1 Cover Page and Index
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
27
28
SLLU192 - September 2008
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
A
B
C
D
5
4
1P2V
1P2V
1P5/8V
DGND0
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
DGND7
DGND8
DGND9
DGND10
DGND11
DGND12
DGND13
DGND14
DGND15
DGND16
DGND17
DGND18
DGND19
DGND20
DGND21
DGND22
DGND23
DGND24
DGND25
DGND26
DGND27
DGND28
DGND29
DGND30
DGND31
DGND32
A1
A9
B3
B4
B7
C10
C13
D5
E11
E13
F1
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J10
J5
J6
J7
J8
J9
K1
L14
P1
P14
5
NOTE: PLACE CAPACITORS NEAR TLK3132 DEVICE
NOTE: PLACE CAPACITORS NEAR TLK3132 DEVICE
NOTE: PLACE CAPACITORS NEAR TLK3132 DEVICE
TLK3132
U1R
DIGITAL GROUND
1P2V
2P5V
AGND0
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
AGND7
AGND8
AGND9
AGND10
AGND11
K11
L10
L4
L5
L6
L9
M8
N12
N4
P12
P5
P9
4
NOTE: PLACE CAPACITORS NEAR TLK3132 DEVICE
NOTE: PLACE CAPACITORS NEAR TLK3132 DEVICE
TLK3132
U1T
ANALOG GROUND
2. PLACE CAPACITORS NEAR VIAS AND CONNECTORS. THESE CAPACITORS SHOULD DECOUPLE THE DRIVER SUPPLY TO THE GROUND PLANE. IF A SIGNAL IS
REFERENCED TO A POWER PLANE AND THIS POWER PLANE IS NOT ASSOCIATED WITH THE DRIVER SUPPLY, THEN THIS PLANE SHOULD ALSO BE DECOUPLED TO GROUND
NEAR ALL ASSOCIATED VIAS AND CONNECTORS.
1. PLACE CAPACITORS SUCH THAT SMALLER VALUE CAPACITORS ARE NEARER THE DUT AND THEN SUCCESSIVELY PLACE LARGER VALUE CAPACITORS AS YOU MOVE
AWAY FROM THE DUT.
DECOUPLLING GENERAL GUIDELINES:
NOTES:
1P2V_VDDD0
1P2V_VDDD1
1P2V_VDDD2
1P2V_VDDD3
1P2V_VDDT0
1P2V_VDDT1
1P2V_VDDT2
1P2V_VDDT3
1P2V_VDDT4
1P2V_AVDD0
1P2V_AVDD1
1P2V_AVDD2
1P2V_AVDD3
1P2V_AVDD4
1P2V_AVDD5
1P2V_AVDD6
1P2V_AVDD7
1P2V_AVDD8
1P2V_DVDD0
1P2V_DVDD1
1P2V_DVDD2
1P2V_DVDD3
1P2V_DVDD4
1P2V_DVDD5
1P2V_DVDD6
1P2V_DVDD7
1P2V_DVDD8
1P2V_DVDD9
1P2V_DVDD10
P11
P13
P4
P8
L12
M7
N10
N5
N8
K6
K8
K9
L11
M12
M3
M6
P10
P7
E6
E8
F10
F4
F5
G10
K10
K5
L2
L8
N2
1P2V
1P2V
1P2V
1P2V
1P2V
AND LABEL ACCORDINGLY.
NEAR TLK3132 DEVICE
PLANE MONITORING
NOTE: PLACE HEADERS
1
2
JMP5
PIN, DECOUPLING, AND PLANE MONITORING HEADERS.
THE VDDA_VCO, VDDA_CP, VDD_CML, AND VDD_PLL POWER
3
2
2
DEVICE POWER
NOTE: SEE THE "S05/ JITTER CLEANER CLOCK" PAGE FOR
TLK3132
U1W
TLK3132
U1V
TLK3132
U1S
TLK3132
U1M
3
TLK3132
U1O
TLK3132
U1N
TLK3132
U1U
1P5V_VDDQ0
1P5V_VDDQ1
1P5V_VDDQ2
1P5V_VDDQ3
1P5V_VDDQ4
1P5V_VDDQ5
1P5V_VDDQ6
1P5V_VDDQ7
1P5V_VDDQ8
1P5V_VDDQ9
1P5V_VDDQ10
1P5V_VDDQ11
1P2V/2P5V_VDDM
2P5V_VDDO0
2P5V_VDDO1
2P5V_VDDO2
2P5V_VDDO3
1P5V/1P8V_VDDR0
1P5V/1P8V_VDDR1
0P75V/0P9V_VREF1
0P75V/0P9V_VREF2
TLK3132
U1Q
TLK3132
U1P
G14
F3
H13
K12
K4
K7
L7
E14
A11
A3
A7
B11
B13
B6
D1
E10
E5
E7
E9
F14
G11
AND LABEL ACCORDINGLY.
NEAR TLK3132 DEVICE
PLANE MONITORING
NOTE: PLACE HEADERS
1
2
JMP13
AND LABEL ACCORDINGLY.
NEAR TLK3132 DEVICE
PLANE MONITORING
NOTE: PLACE HEADERS
1
2
JMP11
AND LABEL ACCORDINGLY.
NEAR TLK3132 DEVICE
PLANE MONITORING
NOTE: PLACE HEADERS
1
2
JMP9
AND LABEL ACCORDINGLY.
NEAR TLK3132 DEVICE
PLANE MONITORING
NOTE: PLACE HEADERS
1
2
JMP7
AND LABEL ACCORDINGLY.
NEAR TLK3132 DEVICE
PLANE MONITORING
NOTE: PLACE HEADERS
1
2
JMP6
B
SIZE
1
DOCUMENT NUMBER
6502968
REV
-
PAGE
2 of
TEXAS INSTURMENTS
VDDM
2P5V
VDDR
VREF
1P5/8V
DEVICE POWER GROUND
PAGE TITLE
VDDM
2P5V
VDDR
VREF
1P5/8V
1
17
A
B
C
D
Figure 21. TLK3132 EVM Schematic, Sheet 2 Device Power and Ground
SLLU192 - September 2008
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
29
R22
DNI
R29
DNI
R28
R23
4.99K
R42
4.99K
R41
4.99K
R40
4.99K
R39
4.99K
R38
DNI
DNI
1
2
4.99K
R8
4.99K
R7
R9
R10
R11
R12
DNI
R25
DNI
R24
40.2K
R37
40.2K
R36
40.2K
R35
40.2K
R34
150
R33
150
R32
49.9
R31
4.99K
4.99K
4.99K
4.99K
DNI
R15
4.99K
R14
4.99K
R13
R16
R43
DNI
40.2K
1
1
1
1
1
1
1
D7
D6
HSMB-C170
2 GPO4_LED_VF
D5
D4
HSMB-C170
2 GPO2_LED_VF
HSMB-C170
2 GPO3_LED_VF
R30
R21
D3
D2
D1
LTST-C170KRKT
2
RESET_LED_VF
HSMG-C170
2 RESET_BAR_LED_VF
HSMB-C170
2 GPO0_LED_VF
HSMB-C170
2 GPO1_LED_VF
R20
R17
R6
R5
R2
130
130
49.9
49.9
49.9
49.9
49.9
Figure 22. TLK3132 EVM Schematic, Sheet 3 Global Signals
.
30
SLLU192 - September 2008
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
A
B
C
D
5
5
TLK3132
U1J
SERIAL TD AND RD NETS SHOULD MATCH WITHIN 0.5 MIL.
TDP0
TDN0
TDP1
TDN1
TDP0_SMP
J8
J6
J4
TDP0
TDN1
TDP1
3
RDP0
RDN1
RDP1
J9
J7
J5
RDP0_SMP
RDN1_SMP
RDP1_SMP
TDN0
0.01uF
C204
0.01uF
TDN0_SMP
J10
TDN0
RDN0
J11
RDN0_SMP
0.01uF
C50
0.01uF
C49
0.01uF
C48
0.01uF
C47
2
RDP0
RDN1
RDP1
RDN0
RDP0
RDN0
RDP1
RDN1
SIZE
B
1
DOCUMENT NUMBER
6502968
REV
-
PAGE
4 of
TEXAS INSTURMENTS
TLK3132
U1K
1
HIGH SPEED DIFFERENTIAL SIGNALS
PAGE TITLE
N9
M9
C203
TDN1_SMP
TDP1_SMP
2
M5
M4
0.01uF
C202
0.01uF
C201
NOTE: PLACE AC COUPLING CAPACITORS NEAR THE RD SMP CONNECTORS.
3
M11
N11
4
4
P6
N7
TDP0
TDN1
TDP1
SMP CONNECTORS SHOULD BE PLACED ON THE BOTTOM SIDE OF THE BOARD AND THE NETS KEPT AS SHORT AS POSSIBLE.
NOTE:
17
A
B
C
D
Figure 23. TLK3132 EVM Schematic, Sheet 4 High Speed Differential
.
Figure 24. TLK3132 EVM Schematic, Sheet 5 Jitter Cleaner Clock
VCO_RC_FILTER
VCO_RC_FILTER_EXT
VTUNE_EXT
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
31
Figure 25. TLK3132 EVM Schematic, Sheet 6 JTAG and MDIO
32
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 26. TLK3132 EVM Schematic, Sheet 7 TX and RX Data Lines
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
33
Figure 27. TLK3132 EVM Schematic, Sheet 8 TX/RX Clocks and Control
34
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 28. TLK3132 EVM Schematic, Sheet 9 Power Regulation
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
35
Figure 29. TLK3132 EVM Schematic, Sheet 10 Power Distribution
36
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 30. TLK3132 EVM Schematic, Sheet 11 1P2V and VJIT Supply LEDs
HSMB-C170
1
D14
2
1P2V_JIT_LED_VF
R195
49.9
HSMB-C170
1
D13
2
1P2V_LED_VF
R194
49.9
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
37
Figure 31. TLK3132 EVM Schematic, Sheet 12 1P5V and 1P8V Supply LEDs
38
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 32. TLK3132 EVM Schematic, Sheet 13 2P5V and 5V Supply LEDs
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
39
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
A
B
C
D
5
RANGE.
3
VIN
VOUT
REF2940
GND
U48
1
2
5
5V
C197
0.47uF
4P096V_REF8
AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET
R290
10.0K
R289
1.1K
R287
6.19K
R284
10.0K
R283
1.05K
R281
24.9K
2
LED ENABLE
3
1
JMP106
4
2P5V_VDDM_VREF_LOW
2P5V_VDDM_VREF_HIGH
VDDM
1P2V_VDDM_VREF_LOW
1P2V_VDDM_VREF_HIGH
4
VDDM_LED_IN
5V
10
11
8
9
4
5
6
7
3
4 IN_N
4 IN_P
U49E
3 IN_N
3 IN_P
U49D
2 IN_N
2 IN_P
U49C
1 IN_N
1 IN_P
U49B
1 OUT
LM339A
GND
VCC
12
4 OUT
LM339A
3 OUT
LM339A
2 OUT
LM339A
U49A
+
-
+
-
+
-
+
-
LM339A
13
14
VDDM
2
1
R288
105K
3
2P5V_VDDM_LED_PLANE_OUT
1P2V_VDDM_LED_PLANE_OUT
2P5V_VDDM_LED_WINDOW_OUT
41.2K
R286
5V
11.0K
1P2V_VDDM_LED_WINDOW_OUT
R285
R282
105K
5V
3
3
1
JMP107
1
3
JMP105
2
2
LED SELECT
2
2P5V_VDDM_LED_BASE
LED SELECT
1P2V_VDDM_LED_BASE
2
4
6
ZXTD09N50DE6
B2
B1
U50
E2
C2
E1
C1
B
SIZE
5V
1
5V
HSMB-C170
HSMB-C170
1
REV
-
14
TEXAS INSTURMENTS
DOCUMENT NUMBER
6502968
VDDM SUPPLY LEDS
2P5V_VDDM_LED_COL
1P2V_VDDM_LED_COL
PAGE TITLE
5
3
2
1
49.9
R279
1P2V_VDDM_LED_VF
2
D28
1
49.9
R280
2P5V_VDDM_LED_VF
2
D29
SLLU192 - September 2008
1
40
NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE
of
PAGE
17
A
B
C
D
Figure 33. TLK3132 EVM Schematic, Sheet 14 VDDM Supply LEDs
.
Figure 34. TLK3132 EVM Schematic, Sheet 15 VDDR Supply LEDs
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
41
Figure 35. TLK3132 EVM Schematic, Sheet 16 VREF Supply LEDs
42
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 36. TLK3132 EVM Schematic, Sheet 17 Peripheral Ports
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
43
Table 1.
Item
1
Qty
29
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
8
4
6
5
1
1
4
1
7
3
1
1
1
1
2
2
1
7
20
9
21
10
22
3
44
TLK3132 EVM Bill of Materials
Reference
C7, C8, C9, C10, C11, C20, C21, C22,C27,
C28, C34, C35, C36, C40, C41, C47, C48,
C49, C50, C51, C52, C53, C54, C55, C56,
C201, C202, C203, C204
C5, C6, C19, C26, C39, C221, C227, C233
C3, C4, C18, C32
C13, C14, C23, C29, C37, C42
C15, C16, C24, C30, C38
C57
C58
C1, C2, C17, C31
C43
C33, C190, C191, C192, C197, C199,C200
C25, C210, C240
C12
C214
C205
C206
C59, C207
C59, C207
C209
C219, C245, C248, C251, C256, C278,
C281
C218, C244, C247, C250, C255, C272,
C273, C277, C280
C213, C217, C243, C246, C249, C254,
C270, C271, C276, C279
C261, C262, C263
Value
0.01μF
Part
0402 CAP
Part_Number
Manufacturer
C0402X7R500-103KNE
Venkel
0.47μF
1.0μF
100pF
10pF
1500pF
1800pF
2.2μF
0.1uF
0.47μF
1.0μF
10000pF
1000pF
1500pF
1800pF
1.0μF
2.2μF
4.7μF
0.01μF
0402 CAP
0402 CAP
0402 CAP
0402 CAP
0402 CAP
0402 CAP
0402 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0603 CAP
0805 CAP
GRM155R61A474KE15D
C0402X7R500-152KNE
Murata Electronics
Murata Electronics
Venkel
Venkel
Venkel
04025C182KAT2A
Avx Corporation
GRM155R60J225ME15D
Murata Electronics
Venkel
Venkel
0.1uF
GRM155R61A105KE15D
C0402COG500-101JNE
C0402COG500-100JNE
C0603X7R500-104KNE
C0603X7R160-474KNE
C1608X7R1C105K
C0603C103J5RACTU
Tdk Corporation
C0603X7R101-152KNE
Kemet
Venkel
Venkel
ECJ-1VB1H182K
Panasonic
C1608X7R1C105K
Tdk Corporation
GRM188R71A225KE15D
GRM21BR72A103KA01L
Murata Electronics
Venkel
Murata Electronics
1206 CAP
GRM319R71H104KA01D
Murata Electronics
1.0μF
1206 CAP
C1206X7R500-105KNE
100μF
1206 CAP
C1206X5R6R3-107MNE
Venkel
Venkel
C0603COG500-102JNE
C0603X5R6R3-475KNE
Murata Electronics
23
2
C268, C269
10μF
1206 CAP
C1206X7R160-106KNE
24
2
C266, C267
22uF
1206 CAP
C1206X5R6R3-226KNE
Venkel
25
2
C264, C265
47μF
1206 CAP
C1206X5R6R3-476MNE
Venkel
1812 CAP
3216-18
(EIA) CAP
7343-31
(EIA) CAP
7343-31
(EIA) CAP
GRM43SR60J107ME20L
Murata Electronics
B45196H3106K109
Epcos Inc
TA025TCM106KDR
Venkel
B45197A3227K509
Kemet
26
27
4
3
C208, C225, C231, C237
C222, C228, C234
100μF
10μF
28
5
C212, C216, C242, C253, C275
10μF
29
13
220μF
30
5
C220, C223, C224, C226, C229, C230,
C232, C235, C236, C257, C258, C259,
C260
C211, C215, C241, C252, C274
68μF - LESR
7361-38
(EIA)CAP
TA020TCR686KER
Venkel
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
3
1
1
2
5
2
2
6
1
3
2
2
2
1
3
R26, R27, R341
R44
R45
R32, R33
R34, R35, R36, R37, R43
R18, R19
R31, R52
R48, R49, R340, R346, R352, R356
R321
R198, R204, R283
R222, R289
R325, R333
R216, R313
R330
R210, R307, R319
0.0 (Zero Ohm)
1.21K
100
150
40.2K
45.3K
49.9
0.0 (Zero Ohm)
1.00K
1.05K
1.10K
1.15K
1.20K
1.21K
1.40K
0402 RES
0402 RES
0402 RES
0402 RES
0402 RES
0402 RES
0402 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
ERJ-2GE0R00X
Panasonic - Ecg
RR0510P-1211-D
Susumu Co
Susumu Co
Susumu Co
Susumu Co
RG1005P-101-B-T5
RG1005P-151-D-T10
RG1005P-4022-B-T5
ERJ-2RKF4532X
RR0510R-49R9-D
ERJ-3GEY0R00V
RR0816P-102-B-T5
RR0816P-1051-B-T5-03H
RG1608P-112-B-T5
RG1608P-1151-B-T5
RG1608P-122-B-T5
RG1608P-1211-B-T5
RG1608P-1401-B-T5
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
Panasonic - Ecg
Susumu Co
Panasonic - Ecg
Susumu Co
Susumu Co
Susumu Co
Susumu Co
Susumu Co
Susumu Co
Susumu Co
.
46
47
48
49
50
51
1
6
2
1
1
11
R46
R199, R205, R223, R284, R290, R320
R217, R314
R329
R4
R197, R203, R209, R215, R221, R282,
R288, R306, R312, R318, R324
R200, R201, R285
R214, R311
R2, R5
R208, R305, R336
R212, R309
R339
R196, R202, R281
R213, R310
R332
R322
R323
R1, R7, R8, R9, R10, R11, R12, R13, R14,
R38, R39, R40, R41, R42, R53, R54, R55,
R56, R57, R331
R224, R286
R317
R3, R6, R17, R20, R21, R30, R194, R195,
R206, R207, R218, R227, R279, R280,
R303, R304, R315, R316, R334
R338
R220, R287
R335
R337
R211, R308, R326
R348, R349
R343, R344, R347, R350, R353, R354
D37
52
53
54
55
56
57
58
59
60
61
62
63
3
2
2
3
2
1
3
2
1
1
1
20
64
65
66
2
1
19
67
68
69
70
71
72
73
74
1
2
1
1
3
2
6
1
75
11
76
77
78
79
80
6
1
1
1
6
U3, U4, U5, U6, U29, U32, U35, U50, U56,
U59, U61
U28, U31, U34, U49, U55, U58
U1
U65
U60
U27, U30, U33, U48, U54, U57
81
1
U2
82
83
3
18
84
1
U62, U63, U64
D3, D4, D5, D6, D7, D13, D14, D15, D16,
D17, D19, D28, D29, D32, D33, D34, D35,
D36
D2
85
1
D1
86
87
88
1
6
1
SW1
J1, J2, J33
JMP29
89
90
91
75
1
3
JMP4
JMP22, JMP31, JMP32
1.50K
10.0K
10.2K
100
100K
105K
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
RG1608P-152-B-T5
ERA-3AEB103V
RG1608P-1022-B-T5
RG1608P-101-B-T5
TNPW06031003BT9
RR0816P-1053-B-T5-03D
Susumu Co
Panasonic - Ecg
Susumu Co.
Susumu Co.
Vishay/Dale
Susumu Co.
11K
13.0K
130
17.4K
18.7K
2.21K
24.9K
26.7K
3.57K
3.90K
36.0K
4.99K
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
RG1608P-113-B-T5
RG1608P-133-B-T5
RG1608P-131-B-T5
RR0816P-1742-B-T5-24C
RG1608P-1872-B-T5
CR0603-16W-2211FT
RG1608P-2492-B-T5
RR0816P-2672-B-T5-42C
RG1608P-3571-B-T5
RG1608P-392-B-T5
RR0816P-363-B-T5
RG1608P-4991-B-T5
Susumu Co.
Susumu Co.
Susumu Co.
Susumu Co.
Susumu Co.
Venkel
Susumu Co.
Susumu Co.
Susumu Co.
Susumu Co.
Susumu Co.
Susumu Co.
41.2K
47.0K
49.9
0603 RES
0603 RES
0603 RES
RG1608P-4122-B-T5
RG1608P-473-B-T5
ERJ-3EKF49R9V
Susumu Co.
Susumu Co.
Panasonic - Ecg
5.49K
6.19K
64.9K
8.87K
9.76K
100
0.0 (Zero Ohm)
Zener Diode
0603 RES
0603 RES
0603 RES
0603 RES
0603 RES
0805 RES
1210 RES
SOD-323
CR0603-10W-5491FT
RR0816P-6191-B-T5-77H
ERJ-3EKF6492V
CR0603-10W-8871FT
RR0816P-9761-B-T5-96H
RG2012P-101-B-T5
RK73Z2ETTE
BAT 60A E6327
ZXTD09N50DE6
TA
LM339AD
TLK3132
TPS79912DDCR
TPS74401KTWT
REF2940AIDBZ
T
TPS3125J18DB
VR
PTH05010WAS
LED - Blue
Diffused
SOT-23-6
ZXTD09N50DE6TA
Venkel
Susumu Co.
Panasonic - Ecg
Venkel
Susumu Co.
Susumu Co.
Koa Speer
Infineon
Technologies
Zetex Inc
14-SOIC
196-BGA
5-TSOT
7-DD
SOT-23
LM339AD
TLK3132
TPS79912DDCR
TPS74401KTWT
REF2940AIDBZT
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
SOT-23-5
TPS3125J18DBVR
Texas Instruments
SMT PCB
0805 LED
PTH05010WAS
HSMB-C170
LED - Green
Diffused
0805 LED
HSMG-C170
LED - SUPER
RED CLEAR
EVQ-PBE05R
LST-103-07-S-D
20 Pin Shrouded
Shunt
2X4
2X5
0805 LED
LTST-C170KRKT
Texas Instruments
Avago
Technologies Us
Inc
Avago
Technologies Us
Inc
Lite-On Inc
6mm
0.1x0.1"
0.1" SP
EVQ-PBE05R
LST-103-07-S-D
5103308-5
0.1" SP
0.1x0.1"
0.1x0.1"
382811-6
HTSW-150-08-G-D
HTSW-150-08-G-D
Panasonic - Ecg
Samtec
Tyco
Electronics/Amp
Amp/Tyco
Samtec
Samtec
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
45
92
93
94
95
1
8
2
17
96
26
97
98
99
3
1
8
100
12
101
102
7
7
J3, J4, J5, J6, J7, J8, J9, J10, J11, J12,
J13, J16
Screws
Standoff
103
104
105
106
107
108
109
110
4
1
1
1
7
5
2
3
C60, C61, C238, C239
L1
L2
L3
R15, R16, R24, R25, R47, R50, R51
R22, R23, R28, R29, R342
R327, R328
R345, R351, R355
46
JMP17
JMP1, JMP2
JMP3
JMP5, JMP6, JMP7, JMP9, JMP11,
JMP13,
JMP23, JMP129, JMP15, JMP28, JMP30,
JMP16, JMP21, JMP120, JMP122,
JMP124, JMP127
JMP14, JMP27, JMP121, JMP130,
JMP131, JMP132, JMP133, JMP77,
JMP80, JMP81, JMP85, JMP106, JMP112,
JMP115, JMP78, JMP79, JMP82, JMP83,
JMP86, JMP105, JMP107, JMP111,
JMP113, JMP114, JMP116, JMP125
JMP123, JMP126, JMP128
P8
P1, P2, P3, P4, P5, P6, P7, P9
2 X 10
2X6
2X6
1X2
0.1x0.1"
0.1x0.1"
0.1x0.1"
0.1x0.1"
HTSW-150-08-G-D
HTSW-150-08-G-D
HTSW-150-08-G-D
HTSW-150-08-G-S
Samtec
Samtec
Samtec
Samtec
1X3
0.1x0.1"
HTSW-150-08-G-S
Samtec
1X4
Power Jack
Banana Plug Metal
19S101-40ML5
0.1x0.1"
2.1mm
4mm
HTSW-150-08-G-S
PJ-002AH
108-0740-001
SMP
19S101-40ML5
Samtec
Cui Inc
Emerson Network
Power Co
Rosenberger
4-40/0.25"
Round Threaded
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
PMSSS 440 0025 PH
2029
0603 CAP
0603 IND
1210 IND
1210 IND
0603 RES
0402 RES
0201 RES
0603 RES
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
Building Fasteners
Keystone
Electronics
.
Board Layouts
Figure 37. TLK3132 EVM Layout, Top Signal (Layer 1)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
47
Figure 38. TLK3132 EVM Layout, Internal Ground (Layers 2,4,6,8,10)
48
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 39. TLK3132 EVM Layout, Internal Power (Layer 3)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
49
Figure 40. TLK3132 EVM Layout, Internal Signal (Layer 5)
50
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 41. TLK3132 EVM Layout, Internal Signal (Layer 7)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
51
Figure 42. TLK3132 EVM Layout, Internal Power (Layer 9)
52
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 43. TLK3132 EVM Layout, Internal Ground and Power (Layer 11)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
53
Figure 44. TLK3132 EVM Layout, Internal Signal (Layer 12)
54
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 45. TLK3132 EVM Layout, Internal Ground (Layers 13,15,17)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
55
Figure 46. TLK3132 EVM Layout, Internal Signal (Layer 14)
56
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
Figure 47. TLK3132 EVM Layout, Internal Power (Layer 16)
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
57
TLK3132 EVM Layout, Bottom Signal (Layer 18)
58
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
.
TLK3132 EVM Layer Construction
Subclass
Name
TOP
Type
Material
SURFACE
AIR
CONDUCTOR
COPPER
DIELECTRIC
FR-4
L2_GND
PLANE
COPPER
DIELECTRIC
FR-4
L3_VCC
CONDUCTOR
COPPER
DIELECTRIC
FR-4
L4_GND
L5_SIG
L6_GND
Thickness
(MIL)
Conductivity
(mho/cm)
Dielectric
Constant
Loss
Tangent
2.4
595900
1
0
5
0
4.1
0.035
1.2
595900
1
0
0.035
3
0
4.1
1.2
595900
1
0
3
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
CONDUCTOR
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
3
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
3
0
4.1
0.035
L10_GND
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
3
0
4.1
0.035
L11_GND
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
L7_SIG
L8_GND
L9_VCC
L12_SIG
L13_GND
L14_SIG
L15_GND
L16_VCC
L17_GND
BOTTOM
CONDUCTOR
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
CONDUCTOR
COPPER
1.2
595900
1
0
DIELECTRIC
FR-4
6.5
0
4.1
0.035
PLANE
COPPER
1.2
595900
1
0
0.035
DIELECTRIC
FR-4
PLANE
COPPER
DIELECTRIC
FR-4
PLANE
COPPER
DIELECTRIC
FR-4
CONDUCTOR
COPPER
SURFACE
AIR
3
0
4.1
1.2
595900
1
0
3
0
4.1
0.035
1.2
595900
1
0
3
0
4.1
0.035
2.4
595900
1
0
Artwork
POSITIVE
Width
(MIL)
Impedance
(ohm)
9.5
47.917
6.5
46.469
NEGATIVE
NEGATIVE
NEGATIVE
POSITIVE
NEGATIVE
POSITIVE
6.5
46.469
NEGATIVE
NEGATIVE
NEGATIVE
NEGATIVE
POSITIVE
6.5
46.469
6.5
46.469
9.5
47.917
NEGATIVE
POSITIVE
NEGATIVE
NEGATIVE
NEGATIVE
POSITIVE
**NOTE: The Impedance is set to be slightly less than 50 ohms on the traces in order to
compensate for slight over-etching during the manufacturing process.
The end
impedance after etching should result in a 50 ohm Impedance. Always consult with your
board manufacturer for their process/design requirements to ensure the desired
impedance is achieved.
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
59
Revision History
Initial Creation (09/09/08 – JN)
Rev 0.1 Added (09/16/08 – JN)
60
TLK3132 2-Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide Rev 0.1
SLLU192 - September 2008
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
【Important Notice for Users of EVMs for RF Products in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
http://www.tij.co.jp
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks
associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
2.
3.
4.
You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable
regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,
contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to
minimize the risk of electrical shock hazard.
Since the EVM is not a completed product, it may not meet all applicable regulatory and safety compliance standards (such as UL,
CSA, VDE, CE, RoHS and WEEE) which may normally be associated with similar items. You assume full responsibility to determine
and/or assure compliance with any such standards and related certifications as may be applicable. You will employ reasonable
safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even if the EVM should fail to
perform as described or expected.
You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.
Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the
user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact
a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the
specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or
interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the
load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures
greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include
but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the
EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please
be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable
in electronic measurement and diagnostics normally found in development environments should use these EVMs.
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connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims
arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.
Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such
as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices
which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate
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