Texas Instruments | AMC1100 Fully-Differential Isolation Amplifier (Rev. B) | Datasheet | Texas Instruments AMC1100 Fully-Differential Isolation Amplifier (Rev. B) Datasheet

Texas Instruments AMC1100 Fully-Differential Isolation Amplifier (Rev. B) Datasheet
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AMC1100
SBAS562B – APRIL 2012 – REVISED DECEMBER 2019
AMC1100 Fully-Differential Isolation Amplifier
1 Features
3 Description
•
The AMC1100 is a precision isolation amplifier with
an output separated from the input circuitry by a
silicon dioxide (SiO2) barrier that is highly resistant to
magnetic interference. This barrier is certified to
provide galvanic isolation of up to 4250 VPEAK,
according to DIN VDE V 0884-11: 2017-01 and
UL1577. Used in conjunction with isolated power
supplies, this device prevents noise currents on a
high common-mode voltage line from entering the
local ground and interfering with or damaging
sensitive circuitry.
1
•
•
•
•
•
•
•
•
•
•
±250-mV input voltage range optimized for shunt
resistors
Very low nonlinearity: 0.075% max at 5 V
Low offset error: 1.5 mV max
Low noise: 3.1 mVRMS typ
Low high-side supply current:
8 mA max at 5 V
Input bandwidth: 60 kHz min
Fixed gain: 8 (0.5% Accuracy)
High common-mode rejection ratio: 108 dB
Low-side operation: 3.3 V
Safety-related certifications:
– 4250-VPK basic isolation per
DIN VDE V 0884-11: 2017-01
– 3005-VRMS isolation for 1 minute per UL1577
– CAN/CSA no. 5A-component acceptance
service notice and DIN EN 61010-1 standard
– Working voltage: 1200 VPEAK
– Transient immunity: 2.5 kV/µs min
Fully specified over the extended industrial
temperature range
The AMC1100 input is optimized for direct connection
to shunt resistors or other low voltage level signal
sources. The excellent performance of the device
enables accurate current and voltage measurement
in energy-metering applications. The output signal
common-mode voltage is automatically adjusted to
either the 3-V or 5-V low-side supply.
The AMC1100 is fully specified over the extended
industrial temperature range of –40°C to +105°C and
is available in the SMD-type, wide-body SOIC-8
(DWV) and gullwing-8 (DUB) packages.
Device Information(1)
PART NUMBER
AMC1100
2 Applications
Shunt resistor based current sensing in:
• Electricity meters
• String inverters
• Power measurement applications
PACKAGE
BODY SIZE (NOM)
SOP (8)
9.50 mm × 6.57 mm
SOIC (8)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Floating
Power Supply
HV+
AMC1100
5.0 V
Gate Driver
RSHUNT
VDD1
VDD2
GND1
GND2
3.3 V, or 5.0 V
RFLT
To Load
RFLT
Gate Driver
Optional
VINN
VOUTP
VINP
VOUTN
CFLT
RFLT
ADS7263
RFLT
HV-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1100
SBAS562B – APRIL 2012 – REVISED DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
3
3
4
4
4
5
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Ratings...........................................................
Insulation Specifications............................................
Safety-Related Certifications.....................................
Safety Limiting Values ..............................................
Electrical Characteristics...........................................
Insulation Characteristics Curves ...........................
Typical Characteristics ............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Revision A (December 2014) to Revision B
Page
•
Changed certification details as per ISO standard in safety-related certifications Features bullet ........................................ 1
•
Deleted typical life span Features bullet ................................................................................................................................ 1
•
Changed Applications section to include end equipment links ............................................................................................. 1
•
Changed IEC60747-5-2 to DIN VDE V 0884-11: 2017-01 in Description section ................................................................. 1
•
Changed page 1 figure and added title .................................................................................................................................. 1
•
Added Power Ratings table .................................................................................................................................................... 4
•
Changed Insulation Specifications table per ISO standard .................................................................................................... 5
•
Added DWV-package related details in Insulation Specifications table ................................................................................. 5
•
Changed Safety-Related Certification table per ISO standard............................................................................................... 6
•
Changed Safety Limiting Values table per ISO standard....................................................................................................... 6
•
Deleted VDD1 and VDD2 from Electrical Characteristics table (repeated in Recommended Operating Conditions
table) ...................................................................................................................................................................................... 7
•
Added Insulation Characteristics Curves section ................................................................................................................... 8
•
Changed Zener Diode Based High-Side Supply figure ........................................................................................................ 21
Changes from Original (April 2012) to Revision A
Page
•
Changed format to meet latest data sheet standards ............................................................................................................ 1
•
Added ESD Rating table and Feature Description, Device Functional Modes, Application and
Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information sections..................................................................................................................... 1
•
Added DWV package to document ........................................................................................................................................ 1
•
Deleted Package and Ordering Information section............................................................................................................... 3
2
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SBAS562B – APRIL 2012 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
DUB and DWV Packages
SOP-8 and SOIC-8
(Top View)
VDD1
1
8
VDD2
VINP
2
7
VOUTP
VINN
3
6
VOUTN
GND1
4
5
GND2
Pin Descriptions
PIN
FUNCTION
NAME
NO.
GND1
4
Power
High-side analog ground
DESCRIPTION
GND2
5
Power
Low-side analog ground
VDD1
1
Power
High-side power supply
VDD2
8
Power
Low-side power supply
VINN
3
Analog input
Inverting analog input
Noninverting analog input
VINP
2
Analog input
VOUTN
6
Analog output
Inverting analog output
VOUTP
7
Analog output
Noninverting analog output
6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
MAX
UNIT
–0.5
6
V
GND1 – 0.5
VDD1 + 0.5
V
Input current to any pin except supply pins
±10
mA
Maximum junction temperature, TJ Max
150
°C
150
°C
Supply voltage, VDD1 to GND1 or VDD2 to GND2
Analog input voltage at VINP, VINN
Storage temperature range, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TA
Operating ambient temperature range
–40
105
°C
VDD1
High-side power supply
4.5
5.0
5.5
V
VDD2
Low-side power supply
2.7
5.0
5.5
V
6.4 Thermal Information
AMC1100
THERMAL METRIC (1)
DUB (SOP)
DWV (SOIC)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
75.1
102.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.6
49.8
°C/W
RθJB
Junction-to-board thermal resistance
39.8
56.6
°C/W
ψJT
Junction-to-top characterization parameter
27.2
16.0
°C/W
ψJB
Junction-to-board characterization parameter
39.4
55.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation
(both sides)
PD1
Maximum power dissipation
(high-side supply)
PD2
Maximum power dissipation
(low-side supply)
4
TEST CONDITIONS
MIN
TYP
MAX
VDD1 = VDD2 = 5.5 V
82.5
VDD1 = 5.5 V, VDD2 = 3.6 V
65.6
VDD1 = 5.5 V
44.0
VDD2 = 5.5 V
38.5
VDD2 = 3.6 V
21.6
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UNIT
mW
mW
mW
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SBAS562B – APRIL 2012 – REVISED DECEMBER 2019
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
DTI
External clearance (1)
External creepage (1)
Distance through insulation
CTI
Comparative tracking index
Material group
Overvoltage category per IEC 60664-1
Shortest pin-to-pin distance through air, DUB package
≥7
Shortest pin-to-pin distance through air, DWV package
≥ 8.5
Shortest pin-to-pin distance across the package
surface, DUB package
≥7
Shortest pin-to-pin distance across the package
surface, DWV package
≥ 8.5
Minimum internal gap (internal clearance) of the
insulation
≥ 0.014
DIN EN 60112 (VDE 0303-11); IEC 60112, DUB
package
≥ 400
DIN EN 60112 (VDE 0303-11); IEC 60112, DWV
package
≥ 600
mm
mm
mm
V
According to IEC 60664-1, DUB package
II
According to IEC 60664-1, DWV package
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-III
DIN VDE V 0884-11: 2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage
VIOWM
Maximum-rated isolation working voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage (3)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Insulation resistance, input to output (5)
RIO
At ac voltage (bipolar)
1200
VPK
At ac voltage (sine wave)
849
VRMS
At dc voltage
1200
VDC
VTEST = VIOTM, t = 60 s (qualification test)
4250
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
5100
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.3 × VIOSM = 6000 VPK (qualification)
4615
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1440 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.3 × VIORM = 1560 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.5 × VIORM = 1800 VPK, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
VPK
VPK
pC
1.2
pF
VIO = 500 V at TA < 85°C
> 1012
VIO = 500 V at 85°C < TA < 105°C
> 1011
Ω
9
VIO = 500 V at TS = 150°C
> 10
Pollution degree
2
Climatic category
40/125/21
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 3005 VRMS or 4250 VDC, t = 60 s
(qualification), VTEST = 1.2 × VISO = 3606 VRMS, t = 1 s
(100% production test)
3005
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
UL
CSA
Certified according to
DIN VDE V 0884-11: 2017-01 and
DIN EN 61010-1 (VDE 0411-1) : 2011-07
VDE
Recognized under 1577 component
recognition program
Recognized under CSA component
acceptance NO 5 program, IEC 60950-1,
and IEC 61010-1
Basic insulation
Single protection
Basic insulation
Certificate number: 40047657
File number: E181974
Certificate number: 2643952
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
PS
TS
(1)
6
Safety input, output,
or supply current
Safety input, output,
or total power (1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DUB package, RθJA = 75.1°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see Figure 1
302
DWV package, RθJA =102.8°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see Figure 1
221
DUB package, RθJA = 75.1°C/W, TJ = 150°C, TA = 25°C,
see Figure 2
1664
mW
DWV package, RθJA = 102.8°C/W, TJ = 150°C,
TA = 25°C, see Figure 2
1216
mW
150
°C
Maximum safety temperature
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDD1max + IS × VDD2max, where VDD1max is the maximum high-side supply voltage and VDD2max is the maximum low-side
supply voltage.
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6.9 Electrical Characteristics
All minimum and maximum specifications are at TA = –40°C to +105°C and are within the specified voltage range, unless
otherwise noted. Typical values are at TA = +25°C, VDD1 = 5 V, and VDD2 = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Maximum input voltage before
clipping
VINP – VINN
Differential input voltage
VINP – VINN
±320
mV
–250
250
–0.16
VDD1
mV
VCM
Common-mode operating range
VOS
Input offset voltage
–1.5
±0.2
1.5
mV
TCVOS
Input offset thermal drift
–10
±1.5
10
µV/K
CMRR
Common-mode rejection ratio
CIN
Input capacitance to GND1
CIND
Differential input capacitance
RIN
Differential input resistance
VIN from 0 V to 5 V at 0 Hz
VIN from 0 V to 5 V at 50 kHz
VINP or VINN
Small-signal bandwidth
60
V
108
dB
95
dB
3
pF
3.6
pF
28
kΩ
100
kHz
OUTPUT
Nominal gain
GERR
Gain error
TCGERR
Gain error thermal drift
Nonlinearity
8
Initial, at TA = +25°C
–0.5%
±0.05%
0.5%
–1%
±0.05%
1%
±56
4.5 V ≤ VDD2 ≤ 5.5 V
–0.075%
±0.015%
0.075%
2.7 V ≤ VDD2 ≤ 3.6 V
–0.1%
±0.023%
0.1%
Nonlinearity thermal drift
Output noise
PSRR
Power-supply rejection ratio
Rise-and-fall time
VIN to VOUT signal delay
CMTI
Common-mode transient
immunity
Output common-mode voltage
ROUT
ppm/K
2.4
ppm/K
VINP = VINN = 0 V
3.1
mVRMS
vs VDD1, 10-kHz ripple
80
dB
vs VDD2, 10-kHz ripple
61
0.5-V step, 10% to 90%
3.66
6.6
µs
0.5-V step, 50% to 10%, unfiltered output
1.6
3.3
µs
0.5-V step, 50% to 50%, unfiltered output
3.15
5.6
µs
0.5-V step, 50% to 90%, unfiltered output
5.26
9.9
µs
VCM = 1 kV
dB
2.5
3.75
kV/µs
2.7 V ≤ VDD2 ≤ 3.6 V
1.15
1.29
1.45
V
4.5 V ≤ VDD2 ≤ 5.5 V
2.4
2.55
2.7
V
Short-circuit current
20
mA
Output resistance
2.5
Ω
POWER SUPPLY
IDD1
High-side supply current
IDD2
Low-side supply current
PDD1
High-side power dissipation
PDD2
Low-side power dissipation
5.4
8
mA
2.7 V < VDD2 < 3.6 V
3.8
6
mA
4.5 V < VDD2 < 5.5 V
4.4
7
mA
27.0
44.0
mW
2.7 V < VDD2 < 3.6 V
11.4
21.6
mW
4.5 V < VDD2 < 5.5 V
22.0
38.5
mW
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6.10 Insulation Characteristics Curves
2000
500
DUB-package
DWV-package
DUB-package
DWV-package
1800
400
1600
PS (mW)
IS (mA)
1400
300
200
1200
1000
800
600
100
400
200
0
0
0
25
50
75
TA (°C)
100
125
150
Figure 1. Thermal Derating Curve for Safety-Limiting
Current per VDE
8
0
D001
25
50
75
TA (°C)
100
125
150
D002
Figure 2. Thermal Derating Curve for Safety-Limiting
Power per VDE
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6.11 Typical Characteristics
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
2
2
1.5
1.5
1
1
Input Offset (mV)
Input Offset (mV)
VDD2 = 2.7 V to 3.6 V
0.5
0
−0.5
0.5
0
−0.5
−1
−1
−1.5
−1.5
−2
4.5
4.75
5
VDD1 (V)
5.25
−2
2.7
5.5
3
3.3
3.6
VDD2 (V)
Figure 3. Input Offset vs High-Side Supply Voltage
Figure 4. Input Offset vs Low-Side Supply Voltage
2
2
1.5
1
1
Input Offset (mV)
Input Offset (mV)
VDD2 = 4.5 V to 5.5 V
1.5
0.5
0
−0.5
0.5
0
−0.5
−1
−1
−1.5
−1.5
−2
4.5
4.75
5
VDD2 (V)
5.25
−2
−40 −25 −10
5.5
130
40
120
30
110
20
100
90
80
110 125
−10
60
−30
100
95
0
−20
1
10
Input Frequency (kHz)
80
10
70
50
0.1
20 35 50 65
Temperature (°C)
Figure 6. Input Offset vs Temperature
Input Current (µA)
CMRR (dB)
Figure 5. Input Offset vs Low-Side Supply Voltage
5
−40
−400
Figure 7. Common-Mode Rejection Ratio vs
Input Frequency
−300
−200
−100
0
100
Input Voltage (mV)
200
300
Figure 8. Input Current vs Input Voltage
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Typical Characteristics (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
120
1
0.8
0.6
0.4
100
Gain Error (%)
Input Bandwidth (kHz)
110
90
80
0.2
0
−0.2
−0.4
−0.6
70
−0.8
60
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
−1
4.5
110 125
Figure 9. Input Bandwidth vs Temperature
5.5
0.6
0.6
0.4
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
3
3.3
VDD2 = 4.5 V to 5.5 V
0.8
Gain Error (%)
Gain Error (%)
5.25
1
VDD2 = 2.7 V to 3.6 V
−1
2.7
−1
4.5
3.6
VDD2 (V)
Figure 11. Gain Error vs Low-Side Supply Voltage
0.8
0
0.6
−10
Normalized Gain (dB)
10
0.2
0
−0.2
−0.4
−50
−70
80
95
Figure 13. Gain Error vs Temperature
110 125
5.5
−40
−0.8
20 35 50 65
Temperature (°C)
5.25
−30
−60
5
5
VDD2 (V)
−20
−0.6
−1
−40 −25 −10
4.75
Figure 12. Gain Error vs Low-Side Supply Voltage
1
0.4
Gain Error (%)
5
VDD1 (V)
Figure 10. Gain Error vs High-Side Supply Voltage
1
0.8
10
4.75
−80
1
10
100
Input Frequency (kHz)
500
Figure 14. Normalized Gain vs Input Frequency
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Typical Characteristics (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
0
5
−30
4.5
−60
VOUTP
VOUTN
4
Output Voltage (V)
Output Phase (°)
−90
−120
−150
−180
−210
−240
3.5
3
2.5
2
1.5
−270
1
−300
0.5
−330
−360
1
10
100
Input Frequency (kHz)
0
−400
1000
Figure 15. Output Phase vs Input Frequency
−200
−100
0
100
Input Voltage (mV)
200
300
400
Figure 16. Output Voltage vs Input Voltage
3.6
3.3
−300
0.1
VDD2 = 2.7 V to 3.6 V
VOUTP
VOUTN
3
0.08
0.06
2.4
Nonlinearity (%)
Output Voltage (V)
2.7
2.1
1.8
1.5
1.2
0.04
0.02
0
−0.02
−0.04
0.9
−0.06
0.6
−0.08
0.3
0
−400
−300
−200
−100
0
100
Input Voltage (mV)
200
300
−0.1
4.5
400
Figure 17. Output Voltage vs Input Voltage
5.25
5.5
0.1
VDD2 = 2.7 V to 3.6 V
0.08
0.06
0.06
0.04
0.04
0.02
0
−0.02
−0.04
0.02
0
−0.02
−0.04
−0.06
−0.06
−0.08
−0.08
3
3.3
3.6
−0.1
4.5
VDD2 (V)
Figure 19. Nonlinearity vs Low-Side Supply Voltage
VDD2 = 4.5 V to 5.5 V
0.08
Nonlinearity (%)
Nonlinearity (%)
5
VDD1 (V)
Figure 18. Nonlinearity vs High-Side Supply Voltage
0.1
−0.1
2.7
4.75
4.75
5
VDD2 (V)
5.25
5.5
Figure 20. Nonlinearity vs Low-Side Supply Voltage
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Typical Characteristics (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
0.1
0.1
VDD2 = 3 V
VDD2 = 5 V
0.08
0.06
0.06
0.04
0.04
Nonlinearity (%)
Nonlinearity (%)
0.08
0.02
0
−0.02
−0.04
0.02
0
−0.02
−0.04
−0.06
−0.06
−0.08
−0.08
−0.1
−250 −200 −150 −100 −50
0
50 100
Input Voltage (mV)
150
200
−0.1
−40 −25 −10
250
2600
100
2400
90
2200
80
2000
70
1800
1600
1400
110 125
20
800
10
100
VDD1
VDD2
40
30
10
95
50
1000
1
80
60
1200
600
0.1
20 35 50 65
Temperature (°C)
Figure 22. Nonlinearity vs Temperature
PSRR (dB)
Noise (nV/sqrt(Hz))
Figure 21. Nonlinearity vs Input Voltage
5
0
1
10
Ripple Frequency (kHz)
Frequency (kHz)
Figure 23. Output Noise Density vs Frequency
100
Figure 24. Power-Supply Rejection Ratio vs
Ripple Frequency
10
Output Rise/Fall Time (µs)
9
8
7
500 mV/div
6
5
4
3
200 mV/div
2
1
0
−40 −25 −10
500 mV/div
5
20 35 50 65
Temperature (°C)
80
95
110 125
Time (2 ms/div)
Figure 25. Output Rise and Fall Time vs Temperature
12
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Typical Characteristics (continued)
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
10
5
8
Signal Delay (µs)
7
6
5
4
3
2
1
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
VDD2 rising
VDD2 falling
Output Common−Mode Voltage (V)
50% to 10%
50% to 50%
50% to 90%
9
4
3
2
1
0
3.5
110 125
Figure 27. Output Signal Delay Time vs Temperature
3.7
3.8
3.9
4
4.1
VDD2 (V)
4.2
4.3
4.4
4.5
Figure 28. Output Common-Mode Voltage vs
Low-Side Supply Voltage
5
8
VDD2 = 2.7 V to 3.6 V
VDD2 = 4.5 V to 5.5 V
Output Common−Mode Voltage (V)
3.6
IDD1
IDD2
7
Supply Current (mA)
4
3
2
6
5
4
3
2
1
1
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
0
4.5
110 125
Figure 29. Output Common-Mode Voltage vs Temperature
4.75
5
Supply Voltage (V)
5.25
5.5
Figure 30. Supply Current vs Supply Voltage
8
8
7
6
6
Supply Current (mA)
IDD2 (mA)
VDD2 = 2.7 V to 3.6 V
7
5
4
3
2
4
3
2
1
1
0
2.7
5
3
3.3
3.6
IDD1
IDD2
0
−40 −25 −10
VDD2 (V)
Figure 31. Low-Side Supply Current vs
Low-Side Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 32. Supply Current vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1100 consists of a delta-sigma modulator input stage including an internal reference and clock
generator. The output of the modulator and clock signal are differentially transmitted over the integrated
capacitive isolation barrier that separates the high- and low-voltage domains. The received bitstream and clock
signals are synchronized and processed by a third-order analog filter with a nominal gain of 8 on the low-side
and presented as a differential output of the device, as shown in the Functional Block Diagram section.
The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity, as described in
application report SLLA181, ISO72x Digital Isolator Magnetic-Field Immunity (available for download at
www.ti.com).
7.2 Functional Block Diagram
VDD1
VDD2
Isolation
Barrier
2.5-V
Reference
2.56-V
Reference
DATA
TX
RX
Retiming and
3rd-Order
Active
Low-Pass
Filter
VINP
û Modulator
VINN
TX
VOUTP
VOUTN
RX
CLK
RC Oscillator
GND1
14
GND2
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7.3 Feature Description
The differential analog input of the AMC1100 is a switched-capacitor circuit based on a second-order modulator
stage that digitizes the input signal into a 1-bit output stream. The device compares the differential input signal
(VIN = VINP – VINN) against the internal reference of 2.5 V using internal capacitors that are continuously
charged and discharged with a typical frequency of 10 MHz. With the S1 switches closed, CIND charges to the
voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then both
S2 switches close. CIND discharges to approximately GND1 + 0.8 V during this phase. Figure 33 shows the
simplified equivalent input circuitry.
VDD1
GND1
GND1
CINP = 3 pF
3 pF
Equivalent
Curcuit
400 :
S1
S2
GND1 + 0.8 V
CIND = 3.6 pF
RIN = 28 k:
400 :
S1
S2
GND1 + 0.8 V
3 pF
CINN = 3 pF
R IN
GND1
GND1
1
f CLK * C IND
GND1
(fCLK = 10 MHz)
Figure 33. Equivalent Input Circuit
The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for
current sensing. However, there are two restrictions on the analog input signals, VINP and VINN. If the input
voltage exceeds the range GND1 – 0.5 V to VDD1 + 0.5 V, the input current must be limited to 10 mA to protect
the implemented input protection diodes from damage. In addition, the device linearity and noise performance
are ensured only when the differential analog input voltage remains within ±250 mV.
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7.4 Device Functional Modes
The AMC1100 is powered on when the supplies are connected. The device is operated off a 5-V nominal supply
on the high-side. The potential of the ground reference GND1 can be floating, which is usually the case in shuntbased current-measurement applications. TI recommends tying one side of the shunt to the GND1 pin of the
AMC1100 to maintain the operating common-mode range requirements of the device.
The low-side of the AMC1100 can be powered from a supply source with a nominal voltage of 3.0 V, 3.3 V, or
5.0 V. When operated at 5 V, the common-mode voltage of the output stage is set to 2.55 V nominal; in both
other cases, the common-mode voltage is automatically set to 1.29 V.
Although usually applied in shunt-based current-sensing circuits, the AMC1100 can also be used for isolated
voltage measurement applications, as shown in a simplified way in Figure 34. In such applications, usually a
resistor divider (R1 and R2 in Figure 34) is used to match the relatively small input voltage range of the
AMC1100. R2 and the AMC1100 input resistance (RIN) also create a resistance divider that results in additional
gain error. With the assumption that R1 and RIN have a considerably higher value than R2, the resulting total gain
error can be estimated using Equation 1:
R
GERRTOT = GERR + 2
RIN
where:
•
GERR = device gain error.
(1)
L1
R1
R2
RIN
L2
Figure 34. Voltage Measurement Application
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The AMC1100 offers unique linearity, high input common-mode rejection, and low dc errors and drift. These
features make the AMC1100 a robust, high-performance isolation amplifier for industrial applications where users
and subsystems must be protected from high voltage potentials.
8.2 Typical Applications
8.2.1 The AMC1100 in Frequency Inverters
A typical operation for the AMC1100 is isolated current and voltage measurement in frequency inverter
applications (such as industrial motor drives, photovoltaic inverters, or uninterruptible power supplies), as
conceptually shown in Figure 35. Depending on the end application, only two or three phase currents are being
sensed.
DC Link
Gate Driver
Gate Driver
Gate Driver
RSHUNT
RSHUNT
RSHUNT
AMC1100
Gate Driver
Gate Driver
Gate Driver
AMC1100
VDD1
AMC1100
AMC1100
VDD1
GND1
GND1
VDD1
VDD2
GND1
GND2
VINP
VOUTP
ADC1P
VINN
VOUTN
ADC1N
VDD2
GND2
VDD1
VDD2
VINP
VOUTP
GND1
GND2
VINN
VOUTN
ADC2P
ADC2N
VDD2
VINP
VOUTP
ADC3P
GND2
VINN
VOUTN
ADC3N
VINP
VOUTP
ADC4P
VINN
VOUTN
ADC4N
Figure 35. Isolated Current and Voltage Sensing in Frequency Inverters
8.2.1.1 Design Requirements
Current measurement through the phase of a motor power line is done via the shunt resistor RSHUNT (in a twoterminal shunt); see Figure 36. For better performance, the differential signal is filtered using RC filters
(components R2, R3, and C2). Optionally, C3 and C4 can be used to reduce charge dumping from the inputs. In
this case, care must be taken when choosing the quality of these capacitors; mismatch in values of these
capacitors leads to a common-mode error at the modulator input. Using NP0 capacitors is recommended, if
necessary.
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Typical Applications (continued)
Isolation
Barrier
Phase
TMC320
C/F28xxx
R1
Device
1
C1(1)
0.1 mF
R2
12 W
RSHUNT
R3
12 W
2
VDD1
VINP
VDD2
VOUTP
14
13
C5(1)
0.1 mF R
(1)
C2
330 pF
C
3
C3
10 pF
(optional)
C4
10 pF
(optional)
4
VINN VOUTN
GND1
GND2
11
ADC
R
9
Figure 36. Shunt-Based Current Sensing with the AMC1100
The isolated voltage measurement can be performed as described in the Device Functional Modes section.
8.2.1.2 Detailed Design Procedure
The floating ground reference (GND1) is derived from the end of the shunt resistor, which is connected to the
negative input of the AMC1100 (VINN). If a four-terminal shunt is used, the inputs of the AMC1100 are
connected to the inner leads and GND1 is connected to one of the outer shunt leads. The differential input of the
AMC1100 ensures accurate operation even in noisy environments.
The differential output of the AMC1100 can either directly drive an analog-to-digital converter (ADC) input or can
be further filtered before being processed by the ADC.
8.2.1.3 Application Curve
In frequency inverter applications the power switches must be protected in case of an overcurrent condition. To
allow fast powering off of the system, low delay caused by the isolation amplifier is required. Figure 37 shows the
typical full-scale step response of the AMC1100.
500 mV/div
200 mV/div
500 mV/div
Time (2 ms/div)
Figure 37. Typical Step Response of the AMC1100
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Typical Applications (continued)
8.2.2 The AMC1100 in Energy Metering
Resulting from its immunity to magnetic fields, the AMC1100 can be used for shunt-based current sensing in
smart electricity meter (e-meter) designs, as shown in Figure 38. Three AMC1100 devices are used for isolated
current sensing. For voltage sensing, resistive dividers are usually used to reduce the common-mode voltage to
levels that allow non-isolated measurement.
L1
L2
L3
VDD2 = DVDD
VDD1A
AMC1100
4G-Modulator
VDD1B
AMC1100
ADC
3x dig. filter for
currents
DVDD
MSP430F47167
Metrology
MCU
VDD1C
AMC1100
ADC
Sync
ADC
SysCLK
ADC
3x dig. filter for
voltage
Data
Application
MCU
ADC
ADC
Digital Core
N
Figure 38. The AMC1100 in an E-Meter Application
8.2.2.1 Design Requirements
For best performance, an RC low-pass filter can be used in front of the AMC1100. Further improvement can be
achieved by filtering the output signal of the device. In both cases, the values of the resistors and the capacitors
must be tailored to the bandwidth requirements of the system.
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Typical Applications (continued)
The analog output of the device is converted to the digital domain using the on-chip analog-to-digital converters
(ADCs) of a suitable metrology microcontroller. The architecture of the MSP430F471x7 family of ultra-low power
microcontrollers is tailored for this kind of applications. The MSP430F471x7 offers up to seven ADCs for
simultaneous sampling: six of which are used for the three phase currents and voltages whereas the seventh
channel can be used for additional voltage sensing of the neutral line for applications that require anti-tampering
measures.
8.2.2.2 Detailed Design Procedure
The high-side supply for the AMC1100 can be derived from the phase voltage using a capacitive-drop power
supply (cap-drop), as shown in Figure 39 and described in the application report SLAA552, AMC1100:
Replacement of Input Main Sensing Transformer in Inverters with Isolate Amplifier.
Phase
5.1 V
470 n / 400 V
220
1N4007
470 µ / 10 V
5.6V
Neutral
GND
Figure 39. Cap-Drop High-Side Power Supply for the AMC1100
Alternatively, the high-side power supply for each AMC1100 can also be derived from the low-side supply using
the SN6501 to drive a transformer, as proven by the TI reference design TIPD121, Isolated Current Sensing
Reference Design Solution, 5A, 2kV.
8.2.2.3 Application Curve
One of the key parameters of an e-meter is its noise performance, which is mainly influenced by the performance
of the ADC and the current sensor. When using a shunt-based approach, the sensor front-end consists of the
actual shunt resistor and the isolated amplifier. Figure 40 shows the typical output noise density of the AMC1100
as a basis for overall performance estimations.
2600
2400
Noise (nV/sqrt(Hz))
2200
2000
1800
1600
1400
1200
1000
800
600
0.1
1
10
100
Frequency (kHz)
Figure 40. Output Noise Density of the AMC1100
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9 Power Supply Recommendations
In a typical frequency inverter application, the high-side power supply for the AMC1100 (VDD1) is derived from
the system supply, as shown in Figure 41. For lowest cost, a Zener diode can be used to limit the voltage to 5 V
± 10%. A 0.1-µF decoupling capacitor is recommended for filtering this power-supply path. Place this capacitor
(C1) as close as possible to the VDD1 pin for best performance. If better filtering is required, an additional 1-µF to
10-µF capacitor can be used.
HV+
Floating
Power Supply
20 V
R1
800
Gate Driver
AMC1100
5.1 V
Z1
1N751A
VDD1
VDD2
3.3 V, or 5.0 V
C1
0.1 F
C4
0.1 F
GND1
GND2
RSHUNT
VINN
to load
R2
12
ADS7263
VINP
Gate Driver
VOUTP
C3
330pF
VOUTN
R3
12
HV-
Figure 41. Zener Diode Based High-Side Supply
For higher power efficiency and better performance, a buck converter can be used; an example of such an
approach is based on the LM5017. A reference design including performance test results and layout
documentation can be downloaded at PMP9480, Isolated Bias Supplies + Isolated Amplifier Combo for Line
Voltage or Current Measurement.
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10 Layout
10.1 Layout Guidelines
A layout recommendation showing the critical placement of the decoupling capacitors that be placed as close as
possible to the AMC1100 while maintaining a differential routing of the input signals is shown in Figure 42.
To maintain the isolation barrier and the common-mode transient immunity (CMTI) of the device, keep the
distance between the high-side ground (GND1) and the low-side ground (GND2) at a maximum; that is, the
entire area underneath the device must be kept free of any conducting materials.
10.2 Layout Example
Top View
12 W
SMD 0603
To Shunt
12 W
SMD 0603
330 pF
SMD
0603
VDD1
VDD2
VINP
VOUTP
0.1mF
VINN
VOUTN
1206
SMD
1206
GND1
GND2
0.1 mF
SMD
1206
LEGEND
Top layer; copper pour and traces
0.1 mF
SMD
Device
To Filter or ADC
Clearance area.
Keep free of any
conductive materials.
High-side area
Controller-side area
Via
Figure 42. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Isolation Glossary
Creepage Distance: The shortest path between two conductive input-to-output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance: The shortest distance between two conductive input-to-output leads measured through air (line of
sight).
Input-to-Output Barrier Capacitance: The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to-Output Barrier Resistance: The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit: An internal circuit directly connected to an external supply mains or other equivalent source that
supplies the primary circuit electric power.
Secondary Circuit: A circuit with no direct connection to primary power that derives its power from a separate
isolated source.
Comparative Tracking Index (CTI): CTI is an index used for electrical insulating materials. It is defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface. The higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive insulation surface degradation by small localized sparks. Such
sparks result from a surface film of a conducting contaminant breaking on the insulation. The resulting break in
the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated.
These sparks often cause carbonization on insulation material and lead to a carbon track between points of
different potential. This process is known as tracking.
11.1.1.1.1 Insulation:
Operational insulation—Insulation needed for correct equipment operation.
Basic insulation—Insulation to provide basic protection against electric shock.
Supplementary insulation—Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
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Device Support (continued)
Double insulation—Insulation comprising both basic and supplementary insulation.
Reinforced insulation—A single insulation system that provides a degree of protection against electric shock
equivalent to double insulation.
11.1.1.1.2 Pollution Degree:
Pollution Degree 1—No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence on
device performance.
Pollution Degree 2—Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation is to be expected.
Pollution Degree 3—Conductive pollution, or dry nonconductive pollution that becomes conductive because of
condensation, occurs. Condensation is to be expected.
Pollution Degree 4—Continuous conductivity occurs as a result of conductive dust, rain, or other wet conditions.
11.1.1.1.3 Installation Category:
Overvoltage Category—This section is directed at insulation coordination by identifying the transient overvoltages
that may occur, and by assigning four different levels as indicated in IEC 60664.
I. Signal Level: Special equipment or parts of equipment.
II. Local Level: Portable equipment and so forth
III. Distribution Level: Fixed installation.
IV. Primary Supply Level: Overhead lines, cable systems.
Each category should be subject to smaller transients than the previous category.
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11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, High-Voltage Lifetime of the ISO72x Family of Digital Isolators application report
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, AMC1100: Replacement of Input Main Sensing Transformer in Inverters with Isolate Amplifier
application report
Texas Instruments, Isolated Current Sensing Reference Design Solution, 5A, 2kVreference guide
Texas Instruments, PMP9480 Isolated Bias Supplies + Isolated Amplifier Combo for Line Voltage or Current
Measurement
Texas Instruments, TPS6212x 15-V, 75-mA Highly Efficient Buck Converter data sheet
Texas Instruments, MSP430F471xx Mixed Signal Microcontroller data sheet
Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, LM5017 100-V, 600-mA Constant On-Time Synchronous Buck Regulator data sheet
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2012–2019, Texas Instruments Incorporated
Product Folder Links: AMC1100
25
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AMC1100DUB
ACTIVE
SOP
DUB
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
AMC1100
AMC1100DUBR
ACTIVE
SOP
DUB
8
350
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
AMC1100
AMC1100DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-2-260C-1 YEAR
-40 to 105
AMC1100
AMC1100DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-2-260C-1 YEAR
-40 to 105
AMC1100
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AMC1100DUBR
SOP
DUB
8
350
330.0
24.4
10.9
10.01
5.85
16.0
24.0
Q1
AMC1100DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1100DUBR
SOP
DUB
8
350
346.0
346.0
29.0
AMC1100DWVR
SOIC
DWV
8
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DUB0008A
SOP - 4.85 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
10.7
TYP
10.1
SEATING PLANE
PIN 1 ID
A
0.1 C
8
1
6X 2.54
9.55
9.02
NOTE 3
2X
7.62
4X
(1.524)
4
5
4X (0.99)
B
6.87
6.37
8X
0.555
0.355
0.1 C A B
6.82
6.32
TOP MOLD
0.355
TYP
0.204
SEE DETAIL A
4.85 MAX
0.635
GAGE PLANE
0 -8
1.45
1.15
0.38 MIN
DETAIL A
TYPICAL
4222355/G 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.254 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DUB0008A
SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE
8X (2.35)
8X (2.35)
SYMM
SYMM
1
1
8
8
(R0.05)
TYP
8X (0.65)
(R0.05)
TYP
8X (0.65)
SYMM
SYMM
6X (2.54)
6X (2.54)
5
4
5
4
(9.1)
(9.45)
IPC-7351 NOMINAL
6.75 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
7.1 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLES
EXPOSED METAL SHOWN
SCALE:5X
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
0.07 MIN
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222355/G 04/2019
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DUB0008A
SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE
8X (2.35)
8X (2.35)
SYMM
1
SYMM
1
8
8
(R0.05)
TYP
8X (0.65)
(R0.05)
TYP
8X (0.65)
SYMM
SYMM
6X (2.54)
6X (2.54)
5
4
5
4
(9.1)
(9.45)
IPC-7351 NOMINAL
6.75 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
7.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:5X
4222355/G 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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