Texas Instruments | AMC1035-Q1 Delta-Sigma Modulator With a Bipolar Input of ±1 V and Reference Output of 2.5 V (Rev. A) | Datasheet | Texas Instruments AMC1035-Q1 Delta-Sigma Modulator With a Bipolar Input of ±1 V and Reference Output of 2.5 V (Rev. A) Datasheet

Texas Instruments AMC1035-Q1 Delta-Sigma Modulator With a Bipolar Input of ±1 V and Reference Output of 2.5 V (Rev. A) Datasheet
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AMC1035-Q1
SBAS941A – MAY 2019 – REVISED NOVEMBER 2019
AMC1035-Q1 Delta-Sigma Modulator
With a Bipolar Input of ±1 V and Reference Output of 2.5 V
1 Features
3 Description
•
The AMC1035-Q1 is a precision, delta-sigma (ΔΣ)
modulator that operates from a single 3.0-V to 5.5-V
supply and with an externally supplied clock signal in
the range of 9 MHz to 21 MHz. In Manchester mode,
the specified clock range is 9 MHz to 11 MHz. The
differential ±1-V input structure of the device is
optimized for voltage and temperature sensing
applications.
1
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Delta-sigma modulator optimized for voltage and
temperature sensing:
– Input voltage range: ±1 V
– High differential input resistance: 1.6 GΩ (typ)
– Integrated 2.5-V, ±5-mA reference for
ratiometric measurement
Excellent DC performance:
– Offset error: ±0.5 mV (max)
– Offset drift: ±6 µV/°C (max)
– Gain error: ±0.25% (max)
– Gain drift: ±45 ppm/°C (max)
– Ratiometric gain drift: ±15 ppm/°C (max)
Selectable Manchester encoded or uncoded
bitstream output
Select the output bitstream of the AMC1035-Q1 to be
Manchester coded to prevent setup and hold time
requirement considerations of the receiving device
and to reduce overall circuit layout efforts. When
used with a digital filter (such as integrated in the
TMS320F28004x,
TMS320F2807x,
or
TMS320F2837x microcontroller families) to decimate
the output bitstream, the device can achieve 16 bits
of resolution with a dynamic range of 87 dB at a data
rate of 82 kSPS.
The internal reference source of the AMC1035-Q1
supports a ratiometric circuit architecture to minimize
the negative impact of the supply voltage variation
and temperature drift on the accuracy of the
measurement.
2 Applications
•
Voltage and temperature sensing in:
– Traction inverters
– Onboard chargers
– DC/DC converters
– Integrated power modules
The AMC1035-Q1 can also be used for high
common-mode AC voltage sensing with a digital
isolator and isolated power supply.
Device Information(1)
PART NUMBER
AMC1035-Q1
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Application Example
3.3 V or 5 V
AMC1035-Q1
VDD
REFOUT
2.5 V, 3.3 V or 5 V
Voltage
Reference
ISO7721-Q1
OUTA
û -Modulator
T
AINN
GND
Manchester
Coding
MCE
INB
GND1
VDD2
ISOLATION
VDD1
AINP
INA
CLKIN
OUTB
DOUT
GND2
GND2
GND1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1035-Q1
SBAS941A – MAY 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings Automotive ..........................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2019) to Revision A
•
2
Page
Changed document status from Advance Information to Production Data ............................................................................ 1
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
MCE
1
8
VDD
AINP
2
7
CLKIN
AINN
3
6
DOUT
REFOUT
4
5
GND
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
MCE
I
Manchester coding enabled, active high, with internal pulldown resistor (typical value: 200 kΩ).
The polarity of this signal must not be changed when the clock signal is applied.
2
AINP
I
Noninverting analog input.
3
AINN
I
Inverting analog input.
4
REFOUT
O
Reference output: 2.5 V nominal, maximum ±5-mA sink and source capability.
5
GND
—
Ground reference.
6
DOUT
O
Modulator bitstream data output, updated with the rising edge of the clock signal present on CLKIN.
This pin is a Manchester coded output if MCE is pulled high. Use the rising edge of the clock to latch the
modulator bitstream at the input of the digital filter device.
7
CLKIN
I
Modulator clock input: 9 MHz to 21 MHz with an internal pulldown resistor (typical value: 200 kΩ).
The clock signal must be applied continuously for proper device operation; see the Clock Input section for
additional details.
8
VDD
—
1
Power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
PARAMETER
MIN
MAX
–0.3
7
V
GND – 5
VDD + 0.5
V
At REFOUT
GND – 0.5
VDD + 0.5
V
Digital input voltage
At CLKIN or MCE
GND – 0.5
VDD + 0.5
V
Digital output voltage
At DOUT
GND – 0.5
VDD + 0.5
Input current
Any pin except supply pins
–10
10
Supply voltage
VDD to GND
Analog input voltage
At AINP or AINN
Analog output voltage
Temperature
(1)
Maximum virtual junction, TJ
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings Automotive
VALUE
Human body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C6
UNIT
±2000
Corner pins (1, 4, 5, and 8)
±1000
Other pins
±1000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
3.0
3.3
5.5
UNIT
POWER SUPPLY
VDD
Supply voltage
VDD to GND
V
ANALOG INPUT
VClipping
Differential input voltage before clipping output
VIN = VAINP – VAINN
VFSR
Specified linear differential full-scale voltage
VIN = VAINP – VAINN
–1
1
V
(VAINP + VAINN) / 2 to GND
–2
VDD
V
(VAINP + VAINN) / 2 to GND,
3.0 V ≤ VDD < 4 V,
VAINP = VAINN
–1.4
VDD –
1.4
(VAINP + VAINN) / 2 to GND,
3.0 V ≤ VDD < 4.5 V,
|VAINP – VAINN| = 1.25 V
–0.8
VDD –
2.4
(VAINP + VAINN) / 2 to GND,
4 V ≤ VDD ≤ 5.5 V,
VAINP = VAINN
–1.4
2.7
(VAINP + VAINN) / 2 to GND,
4.5 V ≤ VDD ≤ 5.5 V,
|VAINP – VAINN| = 1.25 V
–0.8
2.1
VMCE or VCLKIN to GND
GND
VDD
V
125
°C
Absolute common-mode input voltage
VCM
(1)
Operating common-mode input voltage (2)
±1.25
V
V
DIGITAL INPUT
Input voltage
TEMPERATURE RANGE
TA
(1)
(2)
4
Operating ambient temperature
–40
25
Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
See the Analog Input section for more details.
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6.4 Thermal Information
AMC1035-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RΘJA
Junction-to-ambient thermal resistance
120
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
52
°C/W
RΘJB
Junction-to-board thermal resistance
61
°C/W
YJT
Junction-to-top characterization parameter
10
°C/W
YJB
Junction-to-board characterization parameter
60
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
minimum and maximum specifications are at TA = –40°C to 125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN = 0 V,
and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, and VDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VCMuv
VCMov
Negative common-mode
undervoltage detection
level
Positive common-mode
overvoltage detection level
(VAINP + VAINN) / 2 to GND, VAINP = VAINN
–1.45
(VAINP + VAINN) / 2 to GND, |VAINP – VAINN| = 1.25 V
–0.85
(VAINP + VAINN) / 2 to GND, VAINP = VAINN,
3.0 V ≤ VDD < 4.5 V
VDD – 1.35
(VAINP + VAINN) / 2 to GND, |VAINP – VAINN| = 1.25 V,
3.0 V ≤ VDD < 4.5 V
VDD – 2.35
2.75
(VAINP + VAINN) / 2 to GND, |VAINP – VAINN| = 1.25 V,
4.5 V ≤ VDD ≤ 5.5 V
2.15
Single-ended input
resistance
RIND
Differential input resistance
CIN
Single-ended input
capacitance
CIND
Differential input
capacitance
IIB
Input bias current
AINP = AINN = GND; IIB = (IIBP + IIBN) / 2
TCIIB
Input bias current drift
AINP = AINN = GND; IIB = (IIBP + IIBN) / 2
IIO
Input offset current
IIO = IIBP - IIBN
Common-mode rejection
ratio
fIN = 0 Hz, VCMmin ≤ VIN ≤ VCMmax
CMRR
V
(VAINP + VAINN) / 2 to GND, VAINP = VAINN,
4.5 V ≤ VDD ≤ 5.5 V
RIN
AINN = GND
V
0.1
0.4
GΩ
0.16
1.6
GΩ
2
pF
2
pF
AINN = GND
–10
±3
10
±5
–5
±1
nA
pA/°C
5
nA
–104
fIN from 0.1 Hz to 50 kHz, VCMmin ≤ VIN ≤ VCMmax
dB
–88
DC ACCURACY
Resolution
Decimation filter output set to 16 bits
INL
Integral nonlinearity
Resolution: 16 bits
–12
±2
12
EO
Offset error
Initial, at 25°C, AINP = AINN = GND
–0.5
±0.03
0.5
TCEO
Offset error thermal drift
–6
±0.1
6
EG
Gain error
–0.25
±0.02
0.25
–0.3
±0.02
0.3
TCEG
Gain error thermal drift
–45
±20
45
–15
±4
15
PSRR
Power-supply rejection
ratio
Initial, at 25°C
Initial, at 25°C, ratiometric mode
ratiometric mode
16
Bit
AINP = AINN = GND, VDD from 3.0 V to 5.5 V, at DC
–90
AINP = AINN = GND, VDD from 3.0 V to 5.5 V,
10 kHz / 100 mV ripple
–84
LSB
mV
µV/°C
%
ppm/°C
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Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –40°C to 125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN = 0 V,
and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, and VDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
81
87
SINAD
Signal-to-noise + distortion
fIN = 1 kHz
77
83
THD
Total harmonic distortion
fIN = 1 kHz
SFDR
Spurious-free dynamic
range
fIN = 1 kHz
–87
dB
dB
–78
78
87
2.495
2.5
2.505
–50
±20
50
0.15
0.35
dB
dB
REFERENCE OUTPUT
VREF
Reference output voltage
TCVREF
Reference output voltage
drift
IREF
Reference output current
CLOAD < 1 nF
Load regulation
Load to GND or VDD, 0mA to 5mA
ISC
Short-circuit current
PSRR
Power-supply rejection
ratio
Initial, at 25°C, no load
–5
5
REFOUT to GND
23
REFOUT to VDD
–21
–200
±30
V
ppm/°C
mA
mV/mA
mA
200
μV/V
35
μA
DIGITAL INPUT/OUTPUT
GND ≤ VIN ≤ VDD
IIN
Input current
CIN
Input capacitance
VIH
High-level input voltage
0.7 x VDD
VDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 x VDD
V
CLOAD
Output load capacitance
30
pF
VOH
High-level output voltage
VOL
Low-level output voltage
3
fCLKIN = 21 MHz
15
IOH = –20 µA
VDD – 0.1
IOH = –4 mA
VDD – 0.4
pF
V
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
V
POWER SUPPLY
IVDD
6
Supply current
3.0 V ≤ VDD ≤ 3.6 V, IREFOUT = 0 mA, MCE = 0,
CLOAD = 15 pF
5.2
6.8
3.0 V ≤ VDD ≤ 3.6 V, IREFOUT = 0 mA, MCE = 1,
CLOAD = 15 pF
4.6
6.1
4.5 V ≤ VDD ≤ 5.5 V, IREFOUT = 0 mA, MCE = 0,
CLOAD = 15 pF
6.4
8.3
4.5 V ≤ VDD ≤ 5.5 V, IREFOUT = 0 mA, MCE = 1,
CLOAD = 15 pF
5.4
7.2
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6.6 Switching Characteristics
PARAMETER
MIN
TYP
MAX
MCE = 0
TEST CONDITIONS
9
20
21
MCE = 1
9
10
11
40%
50%
60%
UNIT
fCLK
CLKIN clock frequency
DutyCycle
CLKIN duty cycle
tH1
DOUT hold time after rising edge of CLKIN
MCE = 0, CLOAD = 15 pF
6
tH2
DOUT hold time after rising edge of CLKIN
MCE = 1, CLOAD = 15 pF
6
23
ns
tH3
DOUT hold time after falling edge of CLKIN
MCE = 1, CLOAD = 15 pF
10
26
ns
tD1
Rising edge of CLKIN to DOUT valid delay
MCE = 0, CLOAD = 15 pF
25
ns
tD2
Rising edge of CLKIN to DOUT valid delay
MCE = 1, CLOAD = 15 pF
11
27
ns
tD3
Falling edge of CLKIN to DOUT valid delay
MCE = 1, CLOAD = 15 pF
15
30
ns
tr
DOUT rise time
tf
DOUT fall time
tASTART
Analog startup time
ns
10% to 90%, 3.0 V ≼ VDD ≼ 3.6 V, CLOAD = 15 pF
2.5
5
10% to 90%, 4.5 V ≼ VDD ≼ 5.5 V, CLOAD = 15 pF
1.5
3.5
10% to 90%, 3.0 V ≼ VDD ≼ 3.6 V, CLOAD = 15 pF
2.5
5.8
10% to 90%, 4.5 V ≼ VDD ≼ 5.5 V,CLOAD = 15 pF
1.8
4.4
VDD step to 3.0 V; 0.1%-settling, clock applied
MHz
0.25
ns
ns
ms
tCLKIN
CLKIN
tHIGH
tLOW
tH1
tr / tf
tD1
DOUT
(MCE = 0)
tD2
tD3
tH2
tH3
tr / tf
DOUT
(MCE = 1)
Figure 1. Digital Interface Timing
VDD
tASTART
CLKIN
...
DOUT
Bitstream not valid (analog settling)
Valid bitstream
Figure 2. Device Startup Timing
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6.7 Typical Characteristics
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
0
10
7.5
-20
5
-40
CMRR (dB)
IIB (nA)
2.5
0
-2.5
-60
-80
-5
-100
-7.5
-10
-0.65
-0.3
0.05
0.4
0.75
VCM (V)
1.1
1.45
1.8
-120
0.01
2.15
0.1
1
10
100
1000
fIN (kHz)
D001
D002
VDD = 5.5 V
Figure 3. Input Bias Current vs
Common-Mode Input Voltage
Figure 4. Common-Mode Rejection Ratio vs
Input Signal Frequency
12
12
MCE = 0, fCLKIN = 20 MHz
MCE = 1, fCLKIN = 10 MHz
9
10
8
3
INL (|LSB|)
INL (LSB)
6
0
-3
6
4
-6
2
-9
-12
-1
-0.75
-0.5
-0.25
0
0.25
VIN (mV)
0.5
0.75
0
-40
1
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.4
-0.5
4.5
5
VDD (V)
80
95
110 125
D003
5.5
-0.5
-40
Device 1
Device 2
Device 3
-25
D004
Figure 7. Offset Error vs Supply Voltage
8
20 35 50 65
Temperature (°C)
-0.1
-0.3
4
5
0
-0.2
3.5
-10
Figure 6. Integral Nonlinearity vs Temperature
0.5
EO (mV)
EO (mV)
Figure 5. Integral Nonlinearity vs Input Voltage
0.5
3
-25
D031
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-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D005
Figure 8. Offset Error vs Temperature
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Typical Characteristics (continued)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
0.3
0.5
MCE = 0
MCE = 1
0.4
0.2
0.3
0.1
0.1
EG (%)
EO (mV)
0.2
0
-0.1
0
-0.1
-0.2
-0.3
-0.2
-0.4
-0.5
-0.3
9
10
11
12
13
14 15 16
fCLKIN (MHz)
17
18
19
20
21
3
3.5
4
4.5
5
Figure 9. Offset Error vs Clock Frequency
D007
Figure 10. Gain Error vs Supply Voltage
0.3
0.25
Device 1
Device 2
Device 3
0.2
0.2
0.15
0.1
0.05
EG (%)
EG (%)
0.1
0
-0.05
0
-0.1
-0.1
-0.15
Device 1
Device 2
Device 3
-0.2
-0.25
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-0.2
-0.3
-40
110 125
-25
-10
5
D008
Figure 11. Gain Error vs Temperature
20 35 50 65
Temperature (qC)
80
95
110 125
D009
Figure 12. Ratiometric Gain Error vs Temperature
0
0.3
MCE = 0
MCE = 1
0.2
-20
-40
PSRR (dB)
0.1
EG (%)
5.5
VDD (V)
D006
0
-60
-0.1
-80
-0.2
-100
-0.3
9
11
13
15
fCLKIN (MHz)
17
19
21
-120
0.1
1
D010
Figure 13. Gain Error vs Clock Frequency
10
100
Ripple Frequency (kHz)
1000
D011
Figure 14. Power-Supply Rejection Ratio vs
Ripple Frequency
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Typical Characteristics (continued)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
91
91
SNR
SINAD
SNR
SINAD
89
SNR and SINAD (dB)
SNR and SINAD (dB)
89
87
85
83
81
79
87
85
83
81
79
77
3
3.5
4
4.5
5
77
-40
5.5
VDD (V)
-25
-10
D012
Figure 15. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Supply Voltage
5
20 35 50 65
Temperature (qC)
80
95
110 125
D013
Figure 16. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Temperature
91
91
89
89
SNR and SINAD (dB)
SNR and SINAD (dB)
87
87
85
83
81
SNR, MCE = 0
SNR, MCE = 1
SINAD, MCE = 0
SINAD, MCE = 1
79
11
13
15
fCLKIN (MHz)
17
19
83
81
79
77
SNR
SINAD
75
73
0.1
77
9
85
21
1
10
100
fIN (kHz)
D014
Figure 17. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Clock Frequency
D015
Figure 18. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Input Signal Frequency
100
-76
SNR
SINAD
95
-80
-84
85
THD (dB)
SNR and SINAD (dB)
90
80
75
70
-88
-92
-96
65
-100
60
55
-104
0
0.2
0.4
0.6
0.8
1
1.2
VIN (Vpp)
1.4
1.6
1.8
2
Figure 19. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Input Signal Voltage
10
3
3.5
4
4.5
VDD (V)
D016
5
5.5
D017
Figure 20. Total Harmonic Distortion vs Supply Voltage
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Typical Characteristics (continued)
-76
-76
-80
-80
-84
-84
THD (dB)
THD (dB)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
-88
-92
-92
-96
-100
-100
-104
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
9
-80
-80
-84
-84
THD (dB)
-76
-88
-92
17
19
21
D019
-92
-96
-100
-100
-104
1
fIN (kHz)
10
0
105
105
101
101
97
97
SFDR (dB)
109
93
89
0.6
81
81
77
5
VDD (V)
5.5
77
-40
-25
D022
Figure 25. Spurious-Free Dynamic Range vs
Supply Voltage
1.4
1.6
1.8
2
D021
89
85
4.5
0.8
1
1.2
VIN (Vpp)
93
85
4
0.4
Figure 24. Total Harmonic Distortion vs
Input Signal Voltage
109
3.5
0.2
D020
Figure 23. Total Harmonic Distortion vs
Input Signal Frequency
SFDR (dB)
15
fCLKIN (MHz)
-88
-96
3
13
Figure 22. Total Harmonic Distortion vs Clock Frequency
-76
-104
0.1
11
D018
Figure 21. Total Harmonic Distortion vs Temperature
THD (dB)
-88
-96
-104
-40
MCE = 0
MCE = 1
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D023
Figure 26. Spurious-Free Dynamic Range vs
Temperature
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Typical Characteristics (continued)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
109
109
MCE = 0
MCE = 1
105
101
101
97
97
SFDR (dB)
SFDR (dB)
105
93
89
93
89
85
85
81
81
77
0.1
77
9
11
13
15
fCLKIN (MHz)
17
19
21
Figure 27. Spurious-Free Dynamic Range vs
Clock Frequency
10
D025
Figure 28. Spurious-Free Dynamic Range vs
Input Signal Frequency
109
0
105
-20
101
-40
Magnitude (dB)
SFDR (dB)
1
fIN (kHz)
D024
97
93
89
-60
-80
-100
85
-120
81
-140
77
-160
0
0.2
0.4
0.6
0.8
1
1.2
VIN (Vpp)
1.4
1.6
1.8
2
0
5
10
D026
15
20
25
Frequency (kHz)
30
35
40
D027
4096-point FFT, VIN = 2 VPP
Figure 29. Spurious-Free Dynamic Range vs
Input Signal Voltage
Figure 30. Frequency Spectrum With 1-kHz Input Signal
2.505
0
-20
2.503
-60
VREFOUT (V)
Magnitude (dB)
-40
-80
-100
2.501
2.499
-120
2.497
-140
2.495
-160
0
5
10
15
20
25
Frequency (kHz)
30
35
40
3
3.5
4
4.5
VDD (V)
D028
5
5.5
D029
4096-point FFT, VIN = 2 VPP
Figure 31. Frequency Spectrum With 5-kHz Input Signal
12
Figure 32. Reference Output Voltage vs Supply Voltage
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Typical Characteristics (continued)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
2.52
11
Device 1
Device 2
Device 3
2.51
9
2.505
8
2.5
2.495
7
6
2.49
5
2.485
4
2.48
-40
MCE = 0
MCE = 1
10
IVDD (mA)
VREFOUT (V)
2.515
3
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
3
Figure 33. Reference Output Voltage vs Temperature
4.5
5
5.5
D032
Figure 34. Supply Current vs Supply Voltage
11
MCE = 0
MCE = 1
10
MCE = 1
MCE = 0
10
9
9
8
8
IVDD (mA)
IVDD (mA)
4
VDD (V)
11
7
6
7
6
5
5
4
4
3
-40
3.5
D030
3
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
9
11
D033
Figure 35. Supply Current vs Temperature
13
15
fCLKIN (MHz)
17
19
21
D034
Figure 36. Supply Current vs Clock Frequency
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7 Detailed Description
7.1 Overview
The differential analog input (comprised of input signals AINP and AINN) of the AMC1035-Q1 is a chopperstabilized buffer, followed by the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage
that digitizes the input signal into a 1-bit output stream. The data output DOUT of the converter provides a
stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin
with a frequency in the range of 9 MHz to 21 MHz. The time average of this serial bitstream output is proportional
to the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1035-Q1. The 1.6-GΩ
differential input resistance of the analog input stage supports low gain-error signal sensing in high-voltage
applications using resistive dividers. The external clock input simplifies the synchronization of multiple
measurement channels on the system level. The extended frequency range of up to 21 MHz supports higher
performance levels compared to the other solutions available on the market.
7.2 Functional Block Diagram
VDD
MCE
Manchester
Coding
AINP
DOUT
û -Modulator
CLKIN
AINN
Voltage
Reference
REFOUT
GND
7.3 Feature Description
7.3.1 Analog Input
The AMC1035-Q1 incorporates front-end circuitry that contains a buffered sampling stage, followed by a ΔΣ
modulator. To support a bipolar input range, the device uses a charge pump that allows single-supply operation
to simplify the overall system design and minimize the circuit cost. For reduced offset and offset drift, the input
buffer is chopper-stabilized with the switching frequency set at fCLKIN / 32. Figure 37 shows the spur created by
the switching frequency.
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
100
Frequency (kHz)
1000
10000
D036
sinc3 filter, OSR = 2, fCLKIN = 20 MHz, fIN = 1 kHz
Figure 37. Quantization Noise Shaping
14
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Feature Description (continued)
The linearity and noise performance of the device are ensured only when the differential analog input voltage
remains within the specified linear full-scale range (FSR), that is ±1 V, and within the specified input commonmode range.
Figure 38 shows the specified common-mode input voltage that applies for the full-scale input voltage range as
specified in this document along with the corresponding common-mode undervoltage and overvoltage threshold
levels.
If smaller input signals are used, the operational common-mode input voltage range widens. Figure 39 shows the
common-mode input voltage that applies with no differential input signal; that is, when the voltage applied on
AINP is equal to the voltage applied on AINN. The common-mode input voltage range scales with the actual
differential input voltage between this range and the range in Figure 38.
4
4
VCMov
VCMuv
3
3
2
2
VCM (V)
VCM (V)
VCMov
VCMuv
1
1
Specified VCM
Range
Specified VCM
Range
0
0
-1
-1
-2
3
3.25
3.5
3.75
4
4.25
4.5
5
5.5
-2
3
3.25
VDD (V)
3.5
3.75
4
4.25
4.5
5
5.5
VDD (V)
Figure 38. Common-Mode Input Voltage Range With a
Full-Scale Differential Input Signal of ±1.25 V
Figure 39. Common-Mode Input Voltage Range With a
Zero Differential Input Signal
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Feature Description (continued)
7.3.2 Modulator
The modulator implemented in the AMC1035-Q1 (such as the one conceptualized in Figure 40) is a secondorder, switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage VIN and the output V5 of the 1-bit
digital-to-analog converter (DAC) are subtracted, providing an analog voltage V1 at the input of the first integrator
stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage
V3 that is summed with the input signal VIN and the output of the first integrator V2. Depending on the polarity of
the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the
next clock pulse by changing the associated analog output voltage V5, causing the integrators to progress in the
opposite direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
Integrator 1
VIN
V3
V4
Integrator 2
CMP
0V
V5
DAC
Figure 40. Block Diagram of a Second-Order Modulator
As depicted in Figure 37, the modulator shifts the quantization noise to high frequencies. Therefore, use a lowpass digital filter at the output of the device to increase the overall performance. This filter is also used to convert
from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's
microcontroller families TMS320F28004x, TMS320F2807x, and TMS320F2837x offer a suitable programmable,
hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1035-Q1.
Alternatively, a field-programmable gate array (FPGA) can be used to implement the filter.
7.3.3 Reference Output
The AMC1035-Q1 offers a voltage reference output that can source or sink current to significantly reduce the
gain error thermal drift in ratiometric applications as specified in the Electrical Characteristics table. The IGBT
Temperature Sensing section provides an example of a ratiometric use case for the AMC1035-Q1.
The reference output can drive capacitive loads less than 1 nF. Use a series resistor to avoid oscillations and
degradation of performance for capacitive loads ≥ 1 nF. Table 1 lists the recommended series resistor values for
given capacitor value examples. Interpolate for capacitive loads with a value between the given examples.
Table 1. Series Resistor Value for Capacitive Loads ≥ 1 nF on the REFOUT Pin
16
CAPACITIVE LOAD ON THE REFOUT PIN
RECOMMENDED SERIES RESISTOR
1 nF
33 Ω
3.3 nF
56 Ω
10 nF
47 Ω
33 nF
33 Ω
100 nF
15 Ω
330 nF
10 Ω
1 μF
5.6 Ω
3.3 μF
3.3 Ω
10 μF
1.8 Ω
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7.3.4 Clock Input
The AMC1035-Q1 system clock is provided externally at the CLKIN pin. The clock signal must be applied
continuously for proper device operation.
To support the bipolar input voltage range with a single supply, the AMC1035-Q1 includes a charge pump. This
charge pump stops operating if the clock signal is below the specified frequency range or if the signal is paused
or missing. Additionally, the input bias current increases beyond the specified range and significantly reduces the
input resistance of the device. When the clock signal is paused or missing, the modulator stops the analog signal
conversion and the digital output signal remains frozen in the last logic state. When the clock signal is applied
again after a pause, the internal analog circuitry biasing must settle for proper device performance. In this case,
consider the tASTART specification in the Switching Characteristics table.
7.3.5 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of
resolution, that percentage ideally corresponds to code 58982 (an unsigned code). A differential input of –1 V
produces a stream of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit
resolution. These input voltages are also the specified linear range of the AMC1035-Q1 with performance as
specified in this document. If the input voltage value exceeds this range, the output of the modulator shows
nonlinear behavior when the quantization noise increases. The output of the modulator clips with a stream of only
zeros with an input less than or equal to –1.25 V or with a stream of only ones with an input greater than or equal
to 1.25 V. In this case, however, the AMC1035-Q1 generates a single 1 (if the input is at negative full-scale) or 0
every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details).
Figure 41 shows the input voltage versus the output modulator signal.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 41. Analog Input versus the AMC1035-Q1 Modulator Output
Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception
of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
VIN
VClipping
2 u VClipping
(1)
The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN
pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.
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7.3.6 Manchester Coding Feature
The AMC1035-Q1 offers the IEEE 802.3-compliant Manchester coding feature that generates at least one
transition per bit to support clock signal recovery from the bitstream. The Manchester coding combines the clock
and data information using exclusive-OR (XOR) logical operation that results in a bitstream free of DC
components. Figure 42 shows the resulting bitstream from this coding. The duty cycle of the Manchester
encoded bitstream depends on the duty cycle of the input clock CLKIN. To enable Manchester coding on the
AMC1035-Q1, pull the input pin MCE high. The DOUT signal is inverted if the MCE status changes when CLKIN
is high.
Clock
Uncoded
Bitstream
1
0
1
0
1
1
1
0
0
1
0
1
0
0
1
Machester
Coded
Bitstream
Figure 42. Manchester Coded Output of the AMC1035-Q1
7.4 Device Functional Modes
The AMC1035-Q1 is operational when the power supply VDD and clock signal CLKIN are applied, as specified in
the Recommended Operating Conditions and Switching Characteristics tables.
7.4.1 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1035-Q1 (that is, |VIN| ≥ |VClipping|), the device generates a single
one or zero every 128 bits at DOUT, as shown in Figure 43, depending on the actual polarity of the signal being
sensed. This feature is also supported with a Manchester coded output and allows full-scale and invalid input
signals to be identified as described in the Fail-Safe Output section and can be used for advanced system-level
diagnostics.
127 CLKIN cycles
127 CLKIN cycles
CLKIN
...
DOUT
(MCE = 0)
...
(VAINP t VAINN) ” t1.25 V
...
...
...
...
...
...
DOUT
(MCE = 1)
DOUT
(MCE = 0)
(VAINP t VAINN) • 1.25 V
...
...
DOUT
(MCE = 1)
Figure 43. Overrange Output of the AMC1035-Q1
18
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Device Functional Modes (continued)
7.4.2 Fail-Safe Output
Figure 44 shows that if the common-mode voltage of the input reaches or exceeds the specified common-mode
undervoltage, VCMuv, or overvoltage detection level, VCMov as defined in the Electrical Characteristics table, the
DOUT of the AMC1035-Q1 is held at steady-state high.
VCMuv < VCM < VCMov
VCM
VCMov G sCM or VCM G sCMuv
CLKIN
DOUT
(MCE = 0)
DOUT
(MCE = 1)
Figure 44. Fail-Safe Output of the AMC1035-Q1
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Digital Filter Usage
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). Equation 2 shows a sinc3-type filter, which
is a very simple filter, built with minimal effort and hardware:
H z
§ 1 z OSR
¨¨
1
© 1 z
·
¸¸
¹
3
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a secondorder modulator. All the characterization in this document is also done with a sinc3 filter with an oversampling
ratio (OSR) of 256 and an output word width of 16 bits.
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an
FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.
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8.2 Typical Applications
8.2.1 Voltage Sensing
ΔΣ modulators are widely used in high-efficiency systems because of their high AC and DC performance. In
automotive applications, the AMC1035-Q1 can be used in traction inverters, on-board chargers, DC/DC
converters, and as parts of integrated power modules.
Figure 45 shows a simplified schematic of a traction inverter application with the AMC1035-Q1 used for the DClink and output phase voltage sensing. In this example, all resistive dividers reference to the negative DC-link
voltage that is also used as a ground reference point for the microcontroller. An additional fifth AMC1035-Q1 can
be used for temperature sensing of the insulated-gate bipolar transistor (IGBT) module; see the IGBT
Temperature Sensing section for more details.
Current feedback is performed with shunt resistors (RSHUNT) and TI's AMC1305M25-Q1 isolated modulators.
Depending on the system design, either all three or only two motor phase currents are sensed.
Depending on the overall digital processing power requirements, and with a total of eight ΔΣ modulator
bitstreams to be processed by the MCU, a derivate from either the low-cost single-core TMS320F2807x or the
dual-core TMS320F2837x families can be used in this application.
+VBUS
Motor
IDC
RSHUNT
U
RSHUNT
VBUS
V
IAC
RSHUNT
W
RDC1
RAC1
RAC1
RAC1
5 VISO AMC1305M25-Q1 3.3 V
RDC2
RAC2
RAC2
RFLT
RAC2
CFLT
RDC3
RFLT
RAC3
RAC3
AVDD
AINP
DVDD
DOUT
AINN
AGND
CLKIN
DGND
RAC3
AMC1035-Q1 3.3 V
-VBUS
MCE
AINP
RFLT
CFLT
5 VISO AMC1305M25-Q1 3.3 V
RFLT
CFLT
RFLT
AVDD
AINP
DVDD
DOUT
AINN
AGND
CLKIN
DGND
CFLT
RFLT
MCE
AINP
RFLT
CFLT
RFLT
VDD
DOUT
CFLT
RFLT
AVDD
AINP
DVDD
DOUT
AINN
AGND
CLKIN
DGND
SDFM2
SD2_D1
SD2_D2
SD2_D3
SD2_D4
SD2_C1
SD2_C2
SD2_C3
SD2_C4
AMC1035-Q1 3.3 V
AINN
CLKIN
REFOUT GND
RFLT
RFLT
AMC1035-Q1 3.3 V
MCE
AINP
SDFM1
SD1_D1
SD1_D2
SD1_D3
SD1_D4
SD1_C1
SD1_C2
SD1_C3
SD1_C4
5 VISO AMC1305M25-Q1 3.3 V
CFLT
RFLT
TMS320F28x7x
AINN
CLKIN
REFOUT GND
RFLT
AMC1035-Q1 3.3 V
RFLT
VDD
DOUT
MCE
AINP
VDD
DOUT
AINN
CLKIN
REFOUT GND
VDD
DOUT
AINN
CLKIN
REFOUT GND
PWMx
3.3 V
LMK00804B-Q1
VDD
VDDO
CLK_SEL
GND
LVCMOS_CLK
Q0
Q1
Q2
Q3
3.3 V
LMK00804B-Q1
VDD
VDDO
CLK_SEL
GND
LVCMOS_CLK
Q0
Q1
Q2
Q3
Figure 45. The AMC1035-Q1 in a Traction Inverter Application
20
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Typical Applications (continued)
8.2.1.1 Design Requirements
Table 2 lists the parameters for this typical application.
Table 2. Design Requirements
PARAMETER
VALUE
Supply voltage
3.3 V
Voltage drop across the sensing resistor RDC1 for a linear response
1 V (maximum)
Voltage drop across the sensing resistors RACx for a linear response
±1 V (maximum)
Current through the sensing resistors RACx
±100 µV (maximum)
8.2.1.2 Detailed Design Procedure
Use Ohm's Law to calculate the minimum total resistance of the resistive dividers to limit the cross current to the
desired values:
• For the voltage sensing on the DC bus: RDC1 + RDC2 + RDC3 = VBUS / IDC
• For the voltage sensing on the output phases U, V, and W: RAC1 + RAC2 + RAC3 = VPHASE (max) / IAC
Consider the following two restrictions to choose the proper value of the resistors RDC3 and RAC3:
• The voltage drop caused by the nominal voltage range of the system must not exceed the recommended
input voltage range of the AMC1035-Q1: VxC3 ≤ VFSR
• The voltage drop caused by the maximum allowed system overvoltage must not exceed the input voltage that
causes a clipping output: VxC3 ≤ VClipping
Use similar approach for calculation of the shunt resistor values RSHUNT and see the AMC1305M25-Q1 data
sheet for further details.
Table 3 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 600 V and 800 V
on the DC bus.
Table 3. Resistor Value Examples for DC Bus Sensing
PARAMETER
600-V DC BUS
800-V DC BUS
Resistive divider resistor RDC1
3.01 MΩ
4.22 MΩ
Resistive divider resistor RDC2
3.01 MΩ
4.22 MΩ
Sense resistor RDC3
10 kΩ
10.5 kΩ
Resulting current through resistive divider IDC
99.5 µA
94.7 µA
Resulting voltage drop on sense resistor VRDC3
0.995 V
0.994 V
Table 4 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 400 V and 690 V
on the output phases.
Table 4. Resistor Value Examples for Output Phase Voltage Sensing
PARAMETER
±400-VAC PHASE
±690-VAC PHASE
Resistive divider resistor RAC1
2.0 MΩ
3.48 MΩ
Resistive divider resistor RAC2
2.0 MΩ
3.48 MΩ
Sense resistor RAC3
10.0 kΩ
10.0 kΩ
Resulting current through resistive divider IAC
99.8 µA
99.0 µA
Resulting voltage drop on sense resistor VRAC3
±0.998 V
±0.990 V
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Use a power supply with a nominal voltage of 3.3 V to directly connect all modulators to the microcontroller.
For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers
(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These MCU families support up to eight
channels of dedicated hardwired filter structures called sigma-delta filter modules (SDFMs) that significantly
simplify system level design by offering two filtering paths per channel: one providing high accuracy results for
the control loop and one that offers a fast response path for overcurrent detection. Use one of the pulse-width
modulation (PWM) sources inside the MCU to generate the clock for the modulators and for easy
synchronization of all feedback signals and the switching control of the gate drivers.
Figure 45 uses a clock buffer to distribute the clock reference signal generated on one of the PWM outputs of the
MCU (called PWMx in Figure 45) to all modulators used in the circuit and as a reference for the digital filters in
the MCU. In this example, TI's LMK00804B-Q1 is used for this purpose. Each LMK00804B-Q1 output can drive
two modulator or two SDFM clock inputs.
8.2.1.3 Application Curve
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 46 shows the ENOB of the AMC1035-Q1 with different oversampling ratios on a sinc3 filter. This number
is calculated from the SINAD by using following equation: SINAD = 1.76 dB + 6.02 × ENOB.
16
15
ENOB (Bits)
14
13
12
11
10
9
8
7
10
100
OSR
1000
D035
sinc3 filter
Figure 46. Measured Effective Number of Bits vs Oversampling Ratio
22
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8.2.2 IGBT Temperature Sensing
The high input impedance of the AMC1035-Q1 is optimized for usage in voltage-sensing applications.
Additionally, the internal voltage reference supports temperature sensing using a positive temperature coefficient
(PTC) or a negative temperature coefficient (NTC) sensor often integrated in the IGBT module.
The same reference is internally used by the modulator, resulting in a ratiometric system solution that minimizes
the overall temperature drift of the sensing path. Figure 47 shows a simplified schematic of the AMC1035-Q1
used for temperature sensing of the IGBT module. See the Application Example on the front page of this
document for an application solution that requires isolating the temperature sensor.
3.3 V
VDD
REFOUT
IGBT Module
TMS320F28x7x
AMC1035-Q1
AINP
AINN
T
MCE
GND
DOUT
CLKIN
SD-Dx
SD-Cx
Digital
Filter
PWMx
Figure 47. Using the AMC1035-Q1 for Temperature Sensing
8.2.3 What to Do and What Not to Do
Do not leave the analog inputs of the AMC1035-Q1 unconnected (floating) when the device is powered up. If
either modulator input is left floating, the input bias current can drive this input beyond the specified commonmode input voltage range. If both inputs are beyond that range, the gain of the front-end diminishes. In both
cases, the modulator outputs a fail-safe bitstream as described in the Fail-Safe Output section.
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9 Power Supply Recommendations
To decouple the power supply, place a 0.1-µF capacitor as close to the VDD pin of the AMC1035-Q1 as
possible, as shown in Figure 48, followed by an additional capacitor in the range of 1 µF to 10 µF.
Phase X
R1
AMC1035-Q1
VDD
R2
3.0 V to 3.6 V
C1
0.1 F
MCE
optional
anti-aliasing filter
C2
2.2 F
GND
DOUT
AINP
R3
AINN
TMS320F2837x
û Modulator
SD-Dx
CLKIN
SD-Cx
PWMx
Figure 48. Decoupling the AMC1035-Q1
Safety considerations or high common-mode voltage levels can require the AMC1035-Q1 to be galvanically
isolated from other parts of the system. Figure 49 shows an example of a circuit that uses the ISO7721-Q1 to
isolate the signal path and the SN6501-Q1 and a transformer are used to generate the required isolated power.
AMC1035-Q1
2.2 …F
0.1 …F
û Modulator
DATA
CLKIN
VDD
MCE
0.1 …F
VDD1
GND1
GND
GND1
ISOLATION
AINN
VDD1
ISO7721-Q1
DOUT
AINP
CLK
VDD2
VDD2
0.1 …F
GND2
GND2
GND1
TPS7B6933-Q1
OUT
IN
10 …F
0.1 …F
GND
10 …F
SN6501-Q1
20 V
GND1
20 V
GND1
D1
VCC
D2
GND
0.1 …F
10 …F
GND2
Figure 49. Galvanic Isolation of the AMC1035-Q1
24
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10 Layout
10.1 Layout Guidelines
Figure 50 shows two layout recommendations for designs based on 1206-SMD or 0603-SMD size decoupling
capacitors placed as close as possible to the AMC1035-Q1. For best performance, place the AMC1035-Q1 as
close as possible to the source of the analog signal to be converted and keep the layout of the AINP and AINN
traces symmetrical.
10.2 Layout Example
AMC1035-Q1
To
Sensor
AMC1035-Q1
MCE
VDD
AINP
CLKIN
AINN
REFOUT
DOUT
0.1 µF
2.2 µF
1206
1206
To
digital
filter
To
Sensor
GND
MCE
VDD
AINP
CLKIN
AINN
DOUT
REFOUT
0.1
µF
2.2
µF
0603
0603
To
digital
filter
GND
LEGEND
Copper Pour and Traces
Via to Ground Plane
Via to Supply Plane
Figure 50. Recommended Layout of the AMC1035-Q1
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TMS320F28004x Piccolo™ Microcontrollers data sheet
• Texas Instruments, TMS320F2807x Piccolo™ Microcontrollers data sheet
• Texas Instruments, TMS320F2837xD Dual-Core Delfino™ Microcontrollers data sheet
• Texas Instruments, ISO772x-Q1 High-Speed, Robust EMC Reinforced Dual-Channel Digital Isolators data
sheet
• Texas Instruments, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor
Control Applications application report
• Texas Instruments, AMC1305x-Q1 High-Precision, Reinforced Isolated Delta-Sigma Modulators data sheet
• Texas Instruments, LMK00804B-Q1 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fan-out buffer and
level translator data sheet
• Texas Instruments, TPS7B69xx-Q1 High-Voltage Ultra-Low IQ Low-Dropout Regulator data sheet
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Product Folder Links: AMC1035-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
AMC1035QDRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
A1035Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1035-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2019
• Catalog: AMC1035
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
AMC1035QDRQ1
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1035QDRQ1
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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