Texas Instruments | ISO7741E-Q1 Grade 0, High-Speed, Robust-EMC Reinforced Quad-Channel Digital Isolator (Rev. A) | Datasheet | Texas Instruments ISO7741E-Q1 Grade 0, High-Speed, Robust-EMC Reinforced Quad-Channel Digital Isolator (Rev. A) Datasheet

Texas Instruments ISO7741E-Q1 Grade 0, High-Speed, Robust-EMC Reinforced Quad-Channel Digital Isolator (Rev. A) Datasheet
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ISO7741E-Q1
SLLSFB3A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
ISO7741E-Q1 Grade 0, High-Speed, Robust-EMC Reinforced Quad-Channel Digital Isolator
1 Features
2 Applications
•
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•
1
•
•
•
•
•
•
•
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Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 0: –40°C to 150°C
ambient operating temperature
100 Mbps data rate
Robust isolation barrier:
– >100-year projected lifetime at 1500 VRMS
working voltage
– Up to 5000 VRMS isolation rating
– Up to 12.8 kV surge capability
– ±100 kV/μs typical CMTI
Wide supply range: 2.25 V to 5.5 V
2.25-V to 5.5-V level translation
Default output high (ISO7741) and low
(ISO7741F) options
Low power consumption, typical 1.5 mA per
channel at 1 Mbps
Low propagation delay: 10.7 ns typical
(5-V Supplies)
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
Wide-SOIC (DW-16) Package
Safety-related certifications:
– DIN VDE V 0884-11:2017-01
– UL 1577 component recognition program
– CSA certification according to IEC 60950-1,
IEC 62368-1, IEC 61010-1 and IEC 60601-1
end equipment standards
– CQC approval per GB4943.1-2011
– TUV certification according to EN 60950-1, EN
62368-1 and EN 61010-1
•
Hybrid, electric and power train system (EV/HEV)
– Battery management system (BMS)
– On-board charger
– Traction inverter
– DC/DC converter
– Starter/generator
Body electronics
– Automotive parking heater module
– HVAC compressor module
– HVAC control module
– HVAC sensor
– Interior heater module
3 Description
The ISO7741E-Q1 device is a grade 0, highperformance, quad-channel digital isolator with 5000
VRMS isolation ratings per UL 1577. This device has
reinforced insulation ratings according to VDE, CSA,
TUV and CQC. The high temperature range up to
150°C makes this device suitable for applications like
belt starter generators, water pumps, cooling fans,
soot sensors etc.,which may experience greater than
125°C ambient temperature.
Device Information(1)
PART NUMBER
ISO7741E-Q1
PACKAGE
SOIC (DW)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7741E-Q1
SLLSFB3A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description Continued ..........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Rating............................................................. 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics—5-V Supply ..................... 9
Supply Current Characteristics—5-V Supply .......... 9
Electrical Characteristics—3.3-V Supply .............. 10
Supply Current Characteristics—3.3-V Supply ..... 10
Electrical Characteristics—2.5-V Supply .............. 11
Supply Current Characteristics—2.5-V Supply ..... 11
Switching Characteristics—5-V Supply................. 12
Switching Characteristics—3.3-V Supply.............. 12
Switching Characteristics—2.5-V Supply.............. 13
7.18 Insulation Characteristics Curves ......................... 14
7.19 Typical Characteristics .......................................... 15
8
9
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
20
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ................................................ 22
11 Power Supply Recommendations ..................... 25
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 26
13 Device and Documentation Support ................. 27
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2019) to Revision A
•
2
Page
Changed device status to production data ............................................................................................................................ 1
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5 Description Continued
The ISO7741E-Q1 device provide high electromagnetic immunity and low emissions at low power consumption,
while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer
separated by a double capacitive silicon dioxide (SiO2) insulation barrier. This device comes with enable pins
which can be used to put the respective outputs in high impedance for multi-master driving applications and to
reduce power consumption. The ISO7741E-Q1 device has three forward and one reverse-direction channels. If
the input power or signal is lost, default output is high for devices without suffix F and low for devices with suffix
F. See the Device Functional Modes section for further details.
Used in conjunction with isolated power supplies, these devices help prevent noise currents on data buses, such
as CAN, or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.
Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO7741E-Q1 device
havehas been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance. The
ISO7741E-Q1 device is available in 16-pin SOIC package.
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6 Pin Configuration and Functions
ISO7741E-Q1 DW Package
16-Pin SOIC-WB
Top View
1
16 VCC2
GND1 2
15 GND2
INA
3
INB
4
INC
5
14 OUTA
ISOLATION
VCC1
OUTD 6
EN1
7
13 OUTB
12 OUTC
11
IND
10
EN2
GND1 8
9 GND2
Table 1. Pin Functions
PIN
DESCRIPTION
NUMBER
EN1
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in
high-impedance state when EN1 is low.
EN2
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in
high-impedance state when EN2 is low.
GND1
GND2
4
I/O
NAME
2
8
9
15
—
Ground connection for VCC1
—
Ground connection for VCC2
INA
3
I
Input, channel A
INB
4
I
Input, channel B
INC
5
I
Input, channel C
IND
11
I
Input, channel D
OUTA
14
O
Output, channel A
OUTB
13
O
Output, channel B
OUTC
12
O
Output, channel C
OUTD
6
O
Output, channel D
VCC1
1
—
Power supply, side 1
VCC2
16
—
Power supply, side 2
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7 Specifications
7.1 Absolute Maximum Ratings
See
(1)
MIN
MAX
VCC1, VCC2
Supply voltage (2)
–0.5
6
V
Voltage at INx, OUTx, ENx
–0.5
VCCX + 0.5 (3)
IO
Output current
–15
15
mA
TJ
Junction temperature
175
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 3A
±4000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
Contact Discharge per IEC 61000-4-2
Isolation Barrier Withstand Test (2) (3)
±8000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
7.3 Recommended Operating Conditions
MIN
NOM
UNIT
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
IOL
High-level output current
Low-level output current
2.25
MAX
VCC1, VCC2
2
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
5.5
V
2.25
V
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
mA
VIH
High-level input voltage
0.7 × VCCI (1)
VCCI
VIL
Low-level input voltage
0
0.3 × VCCI
DR
Data rate
0
100
Mbps
TA
Ambient temperature
150
°C
(1)
-40
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
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7.4 Thermal Information
ISO7741E-Q1
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 Pins
RθJA
Junction-to-ambient thermal resistance
83.4
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
46
°C/W
Junction-to-board thermal resistance
48
ψJT
°C/W
Junction-to-top characterization parameter
19.1
°C/W
ψJB
Junction-to-board characterization parameter
47.5
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Rating
PARAMETER
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
6
TEST CONDITIONS
MIN
VCC1 = VCC2 = 5.5 V, TJ = 175°C, CL = 15 pF, Input a
50-MHz 50% duty cycle square wave
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TYP
MAX
UNIT
200
mW
75
mW
125
mW
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7.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
DW-16
UNIT
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
V
Material group
According to IEC 60664-1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
VPK
Maximum working isolation voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test; See Figure 22
1500
VRMS
DC voltage
2121
VDC
8000
VPK
VPK
CLR
Overvoltage category per IEC 60664-1
DIN VDE V 0884-11:2017-01 (2)
VIORM
VIOWM
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 x VIOTM,
t= 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM (qualification)
8000
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 x VIORM, tm = 10 s
≤5
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM, tm = 1 s
≤5
VIO = 0.4 x sin (2pft), f = 1 MHz
~1
qpd
Apparent charge
(4)
Barrier capacitance, input to output (5)
CIO
Isolation resistance (5)
RIO
pC
pF
12
VIO = 500 V, TA = 25°C
>10
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500 V at TS = 150°C
>109
Pollution degree
2
Climatic category
40/150/21
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Maximum withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO , t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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7.7 Safety-Related Certifications
VDE
CSA
UL
Recognized under UL 1577
Component Recognition
Program
CQC
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to IEC
60950-1, IEC 62368-1 and IEC
61010-1
Maximum transient
isolation voltage, 8000 VPK
Maximum repetitive peak
isolation voltage, 2121
VPK;
Maximum surge isolation
voltage, 8000 VPK
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC 609501 2nd Ed.+A1+A2, CSA 623681-14 and IEC 62368-1:2014
800 VRMS max working voltage
(pollution degree 2, material
Single protection, 5000 VRMS
group I);
Reinforced insulation per CSA
61010-1-12+A1 and IEC 61010-1
3rd Ed.
300 VRMS max working voltage
(overvoltage category III)
Reinforced Insulation, Altitude
≤ 5000 m, Tropical Climate,
700 VRMS maximum working
voltage;
Certificate number:
40040142
Master contract number: 220991
Certificate number:
CQC15001121716
File number: E181974
Certified according to GB
4943.1-2011
TUV
Certified according to EN
61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A2:2013
5000 VRMS Reinforced
insulation per EN 610101:2010 (3rd Ed) up to
working voltage of 600 VRMS
5000 VRMS Reinforced
insulation per EN 609501:2006/A2:2013 up to
working voltage of 800 VRMS
Client ID number: 77311
7.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
8
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 83.4 °C/W, VI = 5.5 V, TJ = 175°C, TA = 25°C, see Figure 1
327
RθJA = 83.4 °C/W, VI = 3.6 V, TJ = 175°C, TA = 25°C, see Figure 1
500
RθJA = 83.4 °C/W, VI = 2.75 V, TJ = 175°C, TA = 25°C, see Figure 1
654
RθJA = 83.4 °C/W, TJ = 175°C, TA = 25°C, see Figure 2
UNIT
mA
1799
mW
175
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –4 mA; see Figure 9
VOL
Low-level output voltage
IOL = 4 mA; see Figure 9
VCCO
(1)
MIN
TYP
– 0.4
4.8
VIT+(IN) Rising input voltage threshold
VIT-(IN) Falling input voltage threshold
VI(HYS)
Input threshold voltage
hysteresis
(1)
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see
Figure 12
CI
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz,
VCC = 5 V
(1)
(2)
MAX
UNIT
V
0.2
0.4
V
0.6 × VCCI
0.7 × VCCI
V
0.3 × VCCI
0.4 × VCCI
V
0.1 × VCCI
0.2 × VCCI
V
10
at INx or ENx
–10
μA
μA
85
100
kV/μs
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
7.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
Supply current - Disable
Supply current - DC signal
SUPPLY
CURRENT
TEST CONDITIONS
MAX
ICC1
1
1.7
ICC2
0.7
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7741E-Q1);
VI = VCCI (ISO7741E-Q1 with F suffix)
ICC1
4.3
6.5
ICC2
1.8
2.9
EN1 = EN2 = VCCI; VI = VCCI (ISO7741E-Q1);
VI = 0 V (ISO7741E-Q1 with F suffix)
ICC1
1.5
2.4
ICC2
2
3.5
EN1 = EN2 = VCCI; VI = 0 V (ISO7741E-Q1);
VI = VCCI (ISO7741E-Q1 with F suffix)
ICC1
4.8
7.3
ICC2
3.2
5.3
ICC1
3.2
5
ICC2
2.8
4.4
ICC1
3.7
5.2
ICC2
4.2
6.2
ICC1
8.6
11.3
ICC2
18
22
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
TYP
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741E-Q1);
VI = 0 V (ISO7741E-Q1 with F suffix)
1 Mbps
Supply current - AC signal
MIN
UNIT
mA
VCCI = Input-side VCC
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 9
VOL
Low-level output voltage
IOL = 2 mA; see Figure 9
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 12
(1)
MAX
UNIT
V
0.1
0.3
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
μA
–10
μA
85
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
7.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
Supply current - Disable
Supply current - DC signal
SUPPLY
CURRENT
TEST CONDITIONS
10
MAX
ICC1
1
1.7
ICC2
0.7
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7741E-Q1);
VI = VCCI (ISO7741E-Q1 with F suffix)
ICC1
4.3
6.4
ICC2
1.9
2.8
EN1 = EN2 = VCCI; VI = VCCI (ISO7741E-Q1);
VI = 0 V (ISO7741E-Q1 with F suffix)
ICC1
1.5
2.4
ICC2
2
3.5
EN1 = EN2 = VCCI; VI = 0 V (ISO7741E-Q1);
VI = VCCI (ISO7741E-Q1 with F suffix)
ICC1
4.8
7.2
ICC2
3.2
5.3
ICC1
3.2
4.6
ICC2
2.7
4.3
ICC1
3.5
5
ICC2
3.7
5.4
ICC1
6.8
9.3
ICC2
13.7
16.5
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
TYP
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741E-Q1);
VI = 0 V (ISO7741E-Q1 with F suffix)
1 Mbps
Supply current - AC signal
MIN
UNIT
mA
VCCI = Input-side VCC
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7.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 9
VOL
Low-level output voltage
IOL = 1 mA; see Figure 9
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 12
(1)
MAX
UNIT
V
0.05
0.2
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
μA
–10
μA
85
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
7.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
Supply current - Disable
Supply current - DC signal
TEST CONDITIONS
TYP
MAX
ICC1
1
1.7
ICC2
0.7
1.2
EN1 = EN2 = 0 V; VI = 0 V (ISO7741E-Q1);
VI = VCCI (ISO7741E-Q1 with F suffix)
ICC1
4.3
6.4
ICC2
1.8
2.8
EN1 = EN2 = VCCI; VI = VCCI (ISO7741E-Q1);
VI = 0 V (ISO7741E-Q1 with F suffix)
ICC1
1.4
2.4
ICC2
2
3.4
EN1 = EN2 = VCCI; VI = 0 V (ISO7741E-Q1);
VI = VCCI (ISO7741E-Q1 with F suffix)
ICC1
4.7
7.2
ICC2
3.2
5.3
ICC1
3.1
5
ICC2
2.7
4.4
ICC1
3.4
4.9
ICC2
3.5
5.1
ICC1
6.2
8.3
ICC2
10.8
13.8
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
MIN
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741E-Q1);
VI = 0 V (ISO7741E-Q1 with F suffix)
1 Mbps
Supply current - AC signal
SUPPLY
CURRENT
UNIT
mA
VCCI = Input-side VCC
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7.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
6
10.7
16.5
ns
0
4.9
ns
4
ns
4.4
ns
2.4
4.1
ns
2.4
4.1
ns
Disable propagation delay, high-to-high impedance output
9
20
ns
Disable propagation delay, low-to-high impedance output
9
20
ns
Enable propagation delay, high impedance-to-high output
for ISO7741E-Q1
7
20
ns
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7741E-Q1
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7741E-Q1 with F suffix
7
20
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
Same-direction channels
See Figure 9
See Figure 10
Measured from the time VCC goes
below 1.7 V. See Figure 12
Default output delay time from input power loss
tie
(3)
See Figure 9
Enable propagation delay, high impedance-to-high output
for ISO7741E-Q1 with F suffix
tPZL
(1)
(2)
TEST CONDITIONS
16
Time interval error
2
0.8
– 1 PRBS data at 100 Mbps
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
6
11
16.5
ns
0.1
5
ns
4.1
ns
4.5
ns
1.3
3.1
ns
1.3
3.1
ns
Disable propagation delay, high-to-high impedance output
17
30
ns
Disable propagation delay, low-to-high impedance output
17
30
ns
Enable propagation delay, high impedance-to-high output
for ISO7741E-Q1
17
30
ns
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO7741E-Q1
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO7741E-Q1 with F suffix
17
30
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
12
TEST CONDITIONS
See Figure 9
Same-direction channels
See Figure 9
Enable propagation delay, high impedance-to-high output
for ISO7741E-Q1 with F suffix
Default output delay time from input power loss
Time interval error
See Figure 10
Measured from the time VCC goes
below 1.7 V. See Figure 12
16
2
– 1 PRBS data at 100 Mbps
0.9
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
7.5
12
19
ns
0.2
5.1
ns
4.1
ns
4.6
ns
1
3.6
ns
1
3.6
ns
Disable propagation delay, high-to-high impedance output
22
40
ns
Disable propagation delay, low-to-high impedance output
22
40
ns
Enable propagation delay, high impedance-to-high output
for ISO7741E-Q1
18
40
ns
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO7741E-Q1
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO7741E-Q1 with F suffix
18
40
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
TEST CONDITIONS
See Figure 9
Same-direction Channels
See Figure 9
Enable propagation delay, high impedance-to-high output
for ISO7741E-Q1 with F suffix
Default output delay time from input power loss
Time interval error
See Figure 10
Measured from the time VCC goes
below 1.7 V. See Figure 12
16
2
– 1 PRBS data at 100 Mbps
0.7
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.18 Insulation Characteristics Curves
2000
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Power (mW)
Safety Limiting Current (mA)
800
600
400
200
0
1000
500
0
0
50
100
150
Ambient Temperature (oC)
200
0
D001
Figure 1. Thermal Derating Curve for Safety Limiting
Current for DW-16 Package
14
1500
50
100
150
Ambient Temperature (oC)
200
D002
Figure 2. Thermal Derating Curve for Safety Limiting Power
for DW-16 Package
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7.19 Typical Characteristics
20
9
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
Supply Current (mA)
16
14
12
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
7
Supply Current (mA)
18
10
8
6
6
5
4
3
4
2
2
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
0
25
D007
CL = 15 pF
TA = 25°C
Figure 3. Supply Current vs Data Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D008
CL = No Load
Figure 4. Supply Current vs Data Rate
(With No Load)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
TA = 25°C
15
D012
TA = 25°C
Figure 5. High-Level Output Voltage vs High-level Output
Current
Figure 6. Low-Level Output Voltage vs Low-Level Output
Current
2.05
15
14
Propogation Delay Time (ns)
Power Supply UVLO Threshold (V)
5
10
Low-Level Output Current (mA)
D011
1.95
VCC1 Rising
VCC2 Rising
VCC1 Falling
VCC2 Falling
1.85
13
12
11
10
tPLH at 5 V
tPHL at 5 V
tPLH at 3.3 V
9
1.75
-50
0
50
100
Free-Air Temperature (oC)
150
8
-50
D013
Figure 7. Power Supply Undervoltage Threshold vs Free-Air
Temperature
0
tPHL at 3.3 V
tPLH at 2.5 V
tPHL at 2.5 V
50
100
Free-Air Temperature (oC)
150
D014
Figure 8. Propagation Delay Time vs Free-Air Temperature
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8 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VO
VOH
90%
50%
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
IN
0V
VO
VI
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
VCC
VO
OUT
VCC / 2
VCC / 2
VI
0V
tPZH
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
RL = 1 k
±1%
VOH
VO
50%
0.5 V
tPHZ
50
0V
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Enable/Disable Propagation Delay Time Test Circuit and Waveform
16
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Parameter Measurement Information (continued)
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 11. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
S1
Isolation Barrier
C = 0.1 µF ±1%
IN
Pass-fail criteria:
The output must
remain stable.
OUT
+
CL
See Note A
VOH or VOL
±
GNDI
A.
+
VCM ±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISO7741E-Q1 device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is low
then the output goes to high impedance. The ISO7741E-Q1 device also incorporates advanced circuit techniques
to maximize the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO
buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 13, shows a functional
block diagram of a typical channel.
9.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 14 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 14. On-Off Keying (OOK) Based Modulation Scheme
18
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9.3 Feature Description
provides an overview of the device features.
Table 2. Device Features
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PACKAGE
RATED ISOLATION
ISO7741E-Q1
3 Forward,
1 Reverse
100 Mbps
High
DW-16
5000 VRMS / 8000 VPK
ISO7741E-Q1 with F
suffix
3 Forward,
1 Reverse
100 Mbps
Low
DW-16
5000 VRMS / 8000 VPK
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISO7741E-Q1 device incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
Table 3 lists the functional modes for the ISO7741E-Q1 device.
Table 3. Function Table (1)
VCCI
PU
X
(1)
(2)
(3)
20
VCCO
INPUT
(INx) (2)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
PU
PU
PD
PU
X
H or open
Default
X
PD
X
X
Undetermined
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is High for ISO7741E-Q1 and
Low for ISO7741E-Q1 with F suffix.
A low value of output enable causes the outputs to be highimpedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO7741E-Q1 and Low for ISO7741E-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
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9.4.1 Device I/O Schematics
Input (ISO774x)
VCCI
VCCI
Input (ISO774xF)
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 MW
985 W
985 W
INx
INx
1.5 MW
Enable
Output
VCCO
VCCO
VCCO VCCO
VCCO
2 MW
~20 W
OUTx
1970 W
ENx
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Device I/O Schematics
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO7741E-Q1 devices are high-performance, quad-channel digital isolators. These devices come with
enable pins on each side which can be used to put the respective outputs in high impedance for multi master
driving applications and reduce power consumption. The ISO7741E-Q1 devices use single-ended CMOS-logic
switching technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When
designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators
do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL
digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data
converter or a line transceiver, regardless of the interface type or standard.
10.2 Typical Application
Figure 16 shows ISO7741E-Q1 in belt starter generator application.
48V Side
12V Side
WAKE
MCU
TMS570
ISO7741E
nSTB
EN
TXD
RXD
TCAN1043
CANH
CANL
Figure 16. Belt Starter Generator Application
22
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Typical Application (continued)
10.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 4.
Table 4. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
10.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7741E-Q1 device only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
7
10
8
9
GND1
GND2
EN2
EN1
GND2
GND1
Figure 17. Typical ISO7741E-Q1 Circuit Hook-up
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10.2.3 Application Curve
Ch4 = 1 V / div
Ch4 = 1 V / div
The following typical eye diagrams of the ISO7741E-Q1 device indicates low jitter and wide open eye at the
maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
Figure 19. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
and 25°C
Ch4 = 500 mV / div
Figure 18. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and
25°C
Time = 2.5 ns / div
Figure 20. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 21 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 22 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS and DBQ-16 package up to 400
VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years.
24
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ISO7741E-Q1
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SLLSFB3A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 21. Test Setup for Insulation Lifetime Measurement
Figure 22. Insulation Lifetime Projection Data
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet.
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Product Folder Links: ISO7741E-Q1
25
ISO7741E-Q1
SLLSFB3A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
www.ti.com
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 23. Layout Example Schematic
26
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ISO7741E-Q1
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SLLSFB3A – SEPTEMBER 2019 – REVISED NOVEMBER 2019
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, TCAN1043xx-Q1 Low-Power Fault Protected CAN Transceiver with CAN FD and Wake
data sheet
• Texas Instruments, TMS570LS0714 16- and 32-Bit RISC Flash Microcontroller data sheet
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: ISO7741E-Q1
27
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7741EDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
ISO7741E
ISO7741EDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
ISO7741E
ISO7741FEDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
ISO7741FE
ISO7741FEDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
ISO7741FE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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