Texas Instruments | SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (Rev. C) | Datasheet | Texas Instruments SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (Rev. C) Datasheet

Texas Instruments SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (Rev. C) Datasheet
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SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies
1 Features
3 Description
•
The SN6505x-Q1 is a low-noise, low-EMI push-pull
transformer driver, specifically designed for small
form factor, isolated power supplies. It drives lowprofile, center-tapped transformers from a 2.25 V to
5 V DC power supply. Very low noise and EMI are
achieved by slew rate control of the output switch
voltage and through Spread Spectrum Clocking
(SSC). The SN6505x-Q1 consists of an oscillator
followed by a gate drive circuit that provides the
complementary output signals to drive groundreferenced N-channel power switches. The device
includes two 1-A Power-MOSFET switches to ensure
start-up under heavy loads. The switching clock can
also be provided externally for accurate placement of
switcher harmonics, or when operating with multiple
transformer drivers. The internal protection features
include a 1.7 A current limiting, under-voltage lockout,
thermal shutdown, and break-before-make circuitry.
SN6505A-Q1 and SN6505B-Q1 include a soft-start
feature that prevents high inrush current during power
up with large load capacitors. Soft-start feature has
been disabled in SN6505D-Q1 for applications that
require fast output start-up. SN6505A-Q1 has a 160
kHz internal oscillator for applications that need to
minimize emissions whereas SN6505B-Q1 and
SN6505D-Q1 have a 420 kHz internal oscillators for
applications that require higher efficiency and smaller
transformer size. The SN6505x-Q1 is available in a
small 6-pin SOT23/DBV package. The device
operation is characterized for a temperature range
from -40°C to 125°C.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 (Grade 1) qualified for automotive
applications
– Device temperature grade 1: –40°C to +125°C,
TA
Push-pull driver for transformers
Wide input voltage range: 2.25 V to 5.5 V
High output drive: 1 A at 5 V supply
Low RON 0.25 Ω max at 4.5 V supply
Reduced conducted and radiated EMI
Spread spectrum clocking
Precision internal oscillator options: 160 kHz
(SN6505A-Q1) and 420 kHz (SN6505B-Q1 and
SN6505D-Q1)
Synchronization of multiple devices with external
clock input
Slew-rate control
1.7 A Current-limit
Low shutdown current: <1 μA
Thermal shutdown
Small 6-Pin SOT23 (DBV) package
Soft-start enabled (SN6505A-Q1 and SN6505BQ1) to reduce in-rush current and soft-start
disabled (SN6505D-Q1) for fast start-up
2 Applications
•
Isolated power supplies for
– Traction inverter and motor control
– DC/DC converter
– Battery management system (BMS)
– On-board charger (OBC)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOT23 (6 Pin)
2.90 mm × 1.60 mm
SN6505A-Q1
SN6505B-Q1
SN6505D-Q1
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
SN6505
4
Enable
GND
5 EN
Ext Clock 6 CLK
D2
VOUT
3
VCC 2
VCC
D1 1
10µF
0.1µF
10µF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics, SN6505A-Q1 ......................
Typical Characteristics, SN6505B-Q1 or SN6505DQ1 ..............................................................................
9
Parameter Measurement Information ................ 13
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 19
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Revision B (July 2019) to Revision C
Page
•
Added UNIT V to EN, CLK Voltage specification in Absolute Maximum Ratings table ...................................................... 4
•
Changed '<' or 'less than' sign to '≤' or 'less than or equal' sign in VCC range description at multiple location for better
clarity ...................................................................................................................................................................................... 5
•
Added Revision History comments for data sheet Revision B............................................................................................ 6
•
Added 'Power up time' or tPWRUP specification for two VCC TEST CONDITIONS.................................................................. 6
Changes from Revision A (April 2019) to Revision B
•
Page
Split 'Soft-start time' or tSS specification for SN6505A-Q1 and SN6505B-Q1 ........................................................................ 6
Changes from Original (November 2018) to Revision A
Page
•
Changed device status to "Production Data" ........................................................................................................................ 1
•
Added DA2303-AL transformer to Table 3 table .................................................................................................................. 24
•
Added DA2304-AL transformer to Table 3 table .................................................................................................................. 24
2
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SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
5 Pin Configuration and Functions
DBV Package
SOT-23 (6 Pin)
Top View
D1
1
6
CLK
VCC
2
5
EN
D2
3
4
GND
Pin Functions
PIN
NAME
DESCRIPTION
NO.
TYPE
D1
1
O
Open drain output of the first power MOSFETs. Typically connected to the outer terminals of the
center tap transformer. Because large currents flow through these pins, their external traces
should be kept short.
VCC
2
P
This is the device supply pin. It should be bypassed with a 4.7 μF or greater, low ESR capacitor.
When VCC ≤ 2.25 V, an internal undervoltage lockout circuit trips and turns both outputs off.
D2
3
O
Open drain output of the second power MOSFETs. Typically connected to the outer terminals of
the center tap transformer. Because large currents flow through these pins, their external traces
should be kept short.
GND
4
P
GND is connected to the source of the power MOSFET switches via an internal sense circuit.
Because large currents flow through it, the GND terminals must be connected to a low-inductance
quality ground plane.
EN
5
I
The EN pin turns the device on or off. Grounding or leaving this pin floating disables all internal
circuitry. If unused this pin should be tied directly to VCC.
CLK
6
I
This pin is used to run the device with external clock. Internally it is pulled down to GND. If valid
clock is not detected on this pin, the device shifts automatically to internal clock.
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SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1). All typical values are at TA = 25°C, VCC = 5 V.
MIN
MAX
VCC
–0.5
6
V
Voltage
EN, CLK
–0.5
VCC + 0.5 (3)
V
Output switch voltage
D1, D2
16
V
Peak output switch current
I(D1)Pk, I(D2)Pk
2.4
A
Supply voltage
(2)
UNIT
Junction temperature, TJ
-40
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND) and are peak voltage values.
Maximum voltage must not exceed 6V. A strongly driven EN or CLK input signal can weakly power the floating VCC via an internal
protection diode and cause undetermined output.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 3A
±6000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
VCC
Supply voltage
TYP
2.25
ID1, ID2
Output switch current - Primary side
TA
Ambient temperature
MAX
5.5
2.25 V ≤ VCC ≤ 2.8 V
0.75
2.8 V < VCC ≤ 5.5 V
1
–40
125
UNIT
V
A
°C
6.4 Thermal Information
SN6505x-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
137.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.7
°C/W
RθJB
Junction-to-board thermal resistance
46.0
°C/W
ψJT
Junction-to-top characterization parameter
13.4
°C/W
ψJB
Junction-to-board characterization parameter
44.9
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE SUPPLY
Supply Current (2.8 V ≤ VCC ≤ 5.5 V) (SN6505AQ1)
RL = 50 Ω
1
1.4
mA
Supply Current (2.8 V ≤ VCC ≤ 5.5 V) (SN6505BQ1 and SN6505D-Q1)
RL = 50 Ω
1.56
2.3
mA
IIH
Leakage Current on EN and CLK pin
EN / CLK = VCC
10
20
µA
IDIS
VCC current for EN = 0
ILKG(D1)
ILKG(D2)
Leakage Current on D1, D2 for EN=0
VCC+
(UVLO)
Positive-going UVLO threshold
VCC-
(UVLO)
Negative-going UVLO threshold
VHYS
(UVLO1)
UVLO threshold hysteresis
I(Vcc)
VIN(ON)
EN, CLK pin logic high threshold
VIN(OFF)
EN, CLK pin logic low threshold
VIN(HYS)
EN, CLK pin threshold hysteresis
Voltage of D1, D2 = VCC
0.1
µA
0.1
µA
2.25
1.7
V
V
0.3
V
0.7
0.3
VCC
VCC
0.2
VCC
CLK
FSW
F(EXT)
D1, D2 average switching Frequency (SN6505AQ1)
RL = 50 Ω to VCC; Refer to Figure 36
138
160
203
Khz
D1, D2 average switching Frequency (SN6505BQ1 and SN6505D-Q1)
RL = 50 Ω to VCC; Refer to Figure 36.
363
424
517
kHz
External clock frequency on CLK pin (SN6505AQ1)
100
600
kHz
External clock frequency on CLK pin (SN6505BQ1 and SN6505D-Q1)
100
1600
kHz
OUTPUT STAGE
DMM
R(ON)
Average ON time mismatch between D1 and D2
Output switch on resistance
RL = 50 Ω
0%
VCC = 4.5 V, ID1, ID2 = 1 A
0.16
0.25
Ω
VCC = 2.8 V, ID1, ID2 = 1 A
0.19
0.31
Ω
VCC = 2.25 V, ID1, ID2 = 0.5 A
0.21
0.45
Ω
V(SLEW)
Voltage slew rates on D1 and D2 for SN6505AQ1
RL = 50 Ω to VCC; Refer to Figure 36
48
V/µs
I(SLEW)
Current slew rates at D1 and D2 for SN6505A-Q1
RL = 5 Ω through transformer;
Refer to Figure 37
11
A/µs
V(SLEWHF)
Voltage slew rates on D1 and D2 for SN6505BQ1 and SN6505D-Q1
RL = 50 Ω to VCC; Refer to Figure 36
152
V/µs
I(SLEWHF)
Current slew rates at D1 and D2 for SN6505B-Q1 RL = 5 Ω through transformer;
and SN6505D-Q1
Refer to Figure 37
41
A/µs
ILIM
Current clamp limit (2.8 V < VCC ≤ 5.5V )
1.42
Current clamp limit (2.25 V ≤ VCC ≤ 2.8 V)
0.65
1.75
2.15
A
1.85
A
THERMAL SHUT DOWN
TSD+
TSD turn on temperature
154
168
181
°C
TSD-
TSD turn off temperature
135
150
166
°C
TSD-
TSD hysteresis
13
17
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°C
5
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CLK
tCLKTIMER
Duration after which device switches to internal clock in case of invalid external clock
10
25
µs
OUTPUT STAGE
tBBM
Break-before-make time(SN6505A-Q1)
Measured as voltage with RL = 50 Ω to VCC,
Refer to Figure 36
115
ns
Break-before-make time (SN6505B-Q1
and SN6505D-Q1)
Measured as voltage with RL = 50 Ω to VCC,
Refer to Figure 36
90
ns
SOFT-START ENABLED (SN6505A-Q1 AND SN6505B-Q1)
Soft-start time (SN6505A-Q1)
10% to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
1
2.2
8
ms
Soft-start time (SN6505B-Q1)
10% to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
1
4.25
8
ms
Soft-start time delay
From power up to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
3.5
8.5
18
ms
From EN=1 to full drive-current available at D1 and
D2; 2.25 V ≤ VCC < 3 V
75
160
µs
From EN=1 to full drive-current available at D1 and
D2; 3 V ≤ VCC ≤ 5.5 V
60
100
µs
From EN=0 to output MOSFETs off (no current on
D1 and D2)
1
5
µs
tSS
tSSdelay
SOFT-START DISABLED (SN6505D-Q1)
tPWRUP
tPWRDN
6
Power up time
Power down time
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6.7 Typical Characteristics, SN6505A-Q1
6
100
90
80
70
Efficiency (%)
Output Voltage (V)
5
4
3
60
50
40
30
2
20
VCC = 3.3 V
VCC = 5 V
1
25
125
225
VCC = 3.3 V
VCC = 5 V
10
325 425 525 625
Load Current (mA)
725
825
0
25
925
125
SN6505A-Q1 + Wurth 750315240
225
325 425 525 625
Load Current (mA)
725
825
925
D006
SN6505A-Q1 + Wurth 750315240
Figure 1. Output Voltage vs Load Current
Figure 2. Efficiency vs Load Current
7
100
6.5
90
6
80
70
5
Efficiency (%)
Output Voltage (V)
5.5
4.5
4
3.5
3
60
50
40
30
2.5
Load Current (mA)
VCC = 3.3 V
D029
SN6505A-Q1 + Wurth 750316031
Figure 3. Output Voltage vs Load Current
1100
1000
900
800
700
600
500
Load Current (mA)
D028
SN6505A-Q1 + Wurth 750316031
400
300
200
0
1100
1000
900
800
700
600
500
400
300
200
0
100
10
1
0
1.5
100
20
2
VCC = 3.3 V
Figure 4. Efficiency vs Load Current
7
100
6.5
90
6
80
70
5
Efficiency (%)
Output Voltage (V)
5.5
4.5
4
3.5
3
60
50
40
30
2.5
Load Current (mA)
SN6505A-Q1 + Wurth 750316032
D030
VCC = 3.3 V
Figure 5. Output Voltage vs Load Current
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Load Current (mA)
SN6505A-Q1 + Wurth 750316032
1000
900
800
700
600
500
400
300
200
100
1000
900
800
700
600
500
400
300
0
200
1
100
10
0
1.5
0
20
2
D031
VCC = 3.3 V
Figure 6. Efficiency vs Load Current
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Typical Characteristics, SN6505A-Q1 (continued)
7
100
6.5
90
6
80
70
5
Efficiency (%)
Output Voltage (V)
5.5
4.5
4
3.5
3
60
50
40
30
2.5
Load Current (mA)
VCC = 5 V
D033
SN6505A-Q1 + Wurth 750316033
Figure 7. Output Voltage vs Load Current
1100
1000
900
800
700
600
500
400
300
Load Current (mA)
D032
SN6505A-Q1 + Wurth 750316033
VCC = 5 V
Figure 8. Efficiency vs Load Current
1.6
170
VCC = 2.25 V
VCC = 5.5 V
1.4
VCC = 2.25 V
VCC = 5.5 V
1.2
ICC Current (mA)
165
Frequency (kHz)
200
0
1100
1000
900
800
700
600
500
400
300
200
100
0
0
10
1
100
20
2
1.5
160
1
0.8
0.6
0.4
155
0.2
150
-75
-25
25
Temperature (qC)
75
Figure 9. Frequency vs Free-Air Temperature
8
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125
D003
0
100
200
300
400
External Frequency (kHz)
500
600
D001
Figure 10. Current vs External Frequency
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6.8 Typical Characteristics, SN6505B-Q1 or SN6505D-Q1
100
6
90
80
70
Efficiency (%)
Output Voltage (V)
5
4
3
60
50
40
30
20
2
VCC = 3.3 V
VCC = 5 V
1
25
125
225
VCC = 3.3 V
VCC = 5 V
10
325 425 525 625
Load Current (mA)
725
825
0
25
925
125
225
D007
SN6505B/D-Q1 + Wurth 750315371
325 425 525 625
Load Current (mA)
725
825
925
D008
SN6505B/D-Q1 + Wurth 750315371
Figure 11. Output Voltage vs Load Current
Figure 12. Efficiency vs Load Current
100
4
90
80
70
3
Efficiency (%)
Output Voltage (V)
3.5
2.5
2
60
50
40
30
20
1.5
10
0
1
0
20
40
60
80 100 120 140
Load Current (mA)
160
180
0
200
20
SN6505B/D-Q1 + Wurth 760390011
VCC = 3.3 V
60
80 100 120 140
Load Current (mA)
160
180
200
D011
SN6505B/D-Q1 + Wurth 760390011
Figure 13. Output Voltage vs Load Current
VCC = 3.3 V
Figure 14. Efficiency vs Load Current
6
100
5.5
90
5
80
4.5
70
Efficiency (%)
Output Voltage (V)
40
D010
4
3.5
3
60
50
40
2.5
30
2
20
1.5
10
0
1
0
20
40
60
80 100 120 140
Load Current (mA)
SN6505B/D-Q1 + Wurth 760390012
160
180
D012
VCC = 5 V
Figure 15. Output Voltage vs Load Current
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200
0
20
40
60
80 100 120 140
Load Current (mA)
160
180
SN6505B/D-Q1 + Wurth 760390012
200
D013
VCC = 5 V
Figure 16. Efficiency vs Load Current
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6
100
5.5
90
5
80
4.5
70
Efficiency (%)
Output Voltage (V)
Typical Characteristics, SN6505B-Q1 or SN6505D-Q1 (continued)
4
3.5
3
60
50
40
2.5
30
2
20
1.5
10
0
1
0
20
40
60
80 100 120 140
Load Current (mA)
160
180
0
200
20
40
60
D014
SN6505B/D-Q1 + Wurth 760390013
VCC = 3.3 V
80 100 120 140
Load Current (mA)
160
200
D013
SN6505B/D-Q1 + Wurth 760390013
Figure 17. Output Voltage vs Load Current
180
VCC = 3.3 V
Figure 18. Efficiency vs Load Current
100
5
90
4.5
80
70
Efficiency (%)
Output Voltage (V)
4
3.5
3
2.5
60
50
40
30
2
20
1.5
10
0
1
0
20
40
60
80 100 120 140
Load Current (mA)
160
180
0
200
20
SN6505B/D-Q1 + Wurth 760390014
VCC = 3.3 V
60
80 100 120 140
Load Current (mA)
160
180
200
D017
SN6505B/D-Q1 + Wurth 760390014
Figure 19. Output Voltage vs Load Current
VCC = 3.3 V
Figure 20. Efficiency vs Load Current
7
100
6.5
90
6
80
5.5
70
5
Efficiency (%)
Output Voltage (V)
40
D016
4.5
4
3.5
3
60
50
40
30
2.5
20
2
10
1.5
0
1
0
20
40
60
80 100 120 140
Load Current (mA)
SN6505B/D-Q1 + Wurth 760390014
160
180
D018
VCC = 5 V
Figure 21. Output Voltage vs Load Current
10
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200
0
20
40
60
80 100 120 140
Load Current (mA)
160
180
SN6505B/D-Q1 + Wurth 760390014
200
D019
VCC = 5 V
Figure 22. Efficiency vs Load Current
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Typical Characteristics, SN6505B-Q1 or SN6505D-Q1 (continued)
7
100
6.5
90
6
80
70
5
Efficiency (%)
Output Voltage (V)
5.5
4.5
4
3.5
3
60
50
40
30
2.5
20
2
10
1.5
0
1
0
20
40
60
80 100 120 140
Load Current (mA)
160
180
0
200
20
40
60
D020
SN6505B/D-Q1 + Wurth 760390015
VCC = 3.3 V
80 100 120 140
Load Current (mA)
160
200
D021
SN6505B/D-Q1 + Wurth 760390015
Figure 23. Output Voltage vs Load Current
180
VCC = 3.3 V
Figure 24. Efficiency vs Load Current
7
100
6.5
90
6
80
70
5
Efficiency (%)
Output Voltage (V)
5.5
4.5
4
3.5
3
60
50
40
30
2.5
Load Current (mA)
VCC = 3.3 V
D021
SN6505B/D-Q1 + Wurth 750316028
Figure 25. Output Voltage vs Load Current
1100
1000
900
800
700
600
500
400
300
Load Current (mA)
D022
SN6505B/D-Q1 + Wurth 750316028
VCC = 3.3 V
Figure 26. Efficiency vs Load Current
7
100
6.5
90
6
80
5.5
70
5
Efficiency (%)
Output Voltage (V)
200
0
1100
1000
900
800
700
600
500
400
300
200
100
0
0
10
1
100
20
2
1.5
4.5
4
3.5
3
60
50
40
30
2.5
20
2
10
1.5
0
1
0
100
200
300 400 500 600
Load Current (mA)
700
SN6505B/D-Q1 + Wurth 750316029
800
D024
VCC = 3.3 V
Figure 27. Output Voltage vs Load Current
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900
0
100
200
300 400 500 600
Load Current (mA)
700
SN6505B/D-Q1 + Wurth 750316029
800
900
D025
VCC = 3.3 V
Figure 28. Efficiency vs Load Current
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Typical Characteristics, SN6505B-Q1 or SN6505D-Q1 (continued)
100
4.5
90
4
70
Efficiency (%)
Output Voltage (V)
80
3.5
3
2.5
60
50
40
30
2
20
1.5
10
VCC = 5 V
Figure 29. Output Voltage vs Load Current
1100
1000
800
700
600
500
400
900
D027
SN6505B/D-Q1 + Wurth 7503160030
VCC = 5 V
Figure 30. Efficiency vs Load Current
450
3
VCC = 2.25 V
VCC = 5.5 V
2.5
ICC Current (mA)
440
Frequency (kHz)
300
Load Current (mA)
D026
SN6505B/D-Q1 + Wurth 7503160030
430
420
410
400
-75
200
0
1100
1000
900
800
700
600
500
400
300
200
100
0
Load Current (mA)
100
0
1
VCC = 2.25 V
VCC = 5.5 V
2
1.5
1
0.5
-25
25
Temperature (qC)
75
0
100
125
D004
700
1000
External Frequency (kHz)
1300
1600
D002
Figure 32. Current vs External Frequency
Voltage 1 V/div
Figure 31. Frequency vs Free-Air Temperature
400
Time 2.5 ms/div
Figure 33. Scope Capture of SN6505 Switching from External to Internal Clock
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7 Parameter Measurement Information
SN6505
4
Enable
GND
D2
5 EN
VCC 2
Ext Clock 6 CLK
VOUT
3
VCC
D1 1
10µF
0.1µF
10µF
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Measurement Circuit for Unregulated Output (TP1)
Figure 35. Timing Diagram
VCC
SN6505
4
Enable
GND
5 EN
Ext Clock 6 CLK
D2
3
50
VCC 2
D1 1
50
10µF
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Test Circuit for FSW, V(slew), tBBM
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Parameter Measurement Information (continued)
VCC
R(SHUNT
C1
SN6505
VCC
4
V(Current)
3
GND
D2
EN
Vcc
CLK
D1
2
5
6
1
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Figure 37. I(slew) Test Setup
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8 Detailed Description
8.1 Overview
The SN6505x-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters
utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by two . A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. Before either one of the gates can assume logic high, the
BBM logic ensures a short time period during which both signals are low and both transistors are highimpedance. This short period, is required to avoid shorting out both ends of the primary. The resulting output
signals, present the gate-drive signals for the output transistors.
8.2 Functional Block Diagram
EN
VCC
D2
UVLO
TEMP
÷2
MOSFET
Driver
D1
SSC
OSC
CLK
I-LIM
Ext CLK
Detect
GND
GND
8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary
(see Figure 38).
CR1
C
VIN
CR1
VOUT
C
RL
RL
VIN
CR2
Q2
VOUT
Q1
CR2
Q2
Q1
Figure 38. Switching Cycles of a Push-Pull Converter
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative
voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.
Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting
from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance
RL back to the center-tap.
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Feature Description (continued)
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
Figure 39 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H
as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2
conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the
product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON.
B
VIN
A’
VP
H
RDS
VDS
A
VIN = VP + VDS
Figure 39. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from
the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the
transformer slowly creeps toward the saturation region.
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8.4 Device Functional Modes
The functional modes of the device are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When the supply voltage at VCC ramps up to 2.25 V , the internal oscillator starts operating . The output stage
begins switching but the amplitude of the drain signals at D1 and D2 has not reached its full maximum yet.
8.4.1.1 Soft-Start
SN6505A-Q1 and SN6505B-Q1 devices support soft-start feature. Upon power up or when EN pin transitions
from Low to High, the gate drive of the output power-MOSFET is gradually increased over a period of time from
0 V to VCC. Soft-start prevents high inrush current from VCC while charging large secondary side decoupling
capacitors, and also prevents overshoot in secondary voltage during power-up. For applications that need quick
power-up, the SN6505D-Q1, that has soft-start disabled, can be used.
8.4.2 Operating Mode
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations
over supply voltage and operating temperature can vary the switching frequencies at D1 and D2.
8.4.3 Shutdown-Mode
The device has a dedicated enable pin to put the device in very low power mode to save power when not in use.
Enable pin has an internal pull down resistor which keeps device disabled when not driven. When disabled or
when VCC is < 1.7 V , both drain outputs, D1 and D2, are tri-stated.
8.4.4 Spread Spectrum Clocking
Radiated emissions is an important concern in high current switching power supplies. SN6505 addresses this by
modulating its internal clock in such a way that the emitting energy is spread over multiple frequency bins. This
Spread Spectrum clocking feature greatly improves the emissions performance of the entire power supply block
and hence relieves the system designer from one major concern in isolated power supply design.
8.4.5 External Clock Mode
The SN6505x-Q1 has a CLK pin which can be used to synchronize the device with system clock and in turn with
other SN6505x-Q1 devices so that the system can control the exact switching frequency of the device. The
Rising edge of the CLK is used to divide a clock by two and used to drive the gates. Figure 41 shows the timing
diagram for the same. The device also has external clock fail safe feature which automatically switches the
device to the internal clock if a valid input clock is not present for long (tCLKTIMER). The in-built emissions
reduction scheme of Spread Spectrum clocking is disabled when external clock is present.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN6505x-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters
using the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
Vcc
SN6505
Q2 off
Q1 off
D2
OSC
fOSC
S
G2
Freq.
Divider S
BBM
Logic G1
Q2
D1
Q1
Q1 on
GND
GND
tBBM
Q2 on
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Block Diagram and Output Timing With Break-Before-Make Action
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gatedrive signals for the output transistors Q1 and Q2. As shown in Figure 41, before either one of the gates can
assume logic high, there must be a short time period during which both signals are low and both transistors are
high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends
of the primary.
Figure 41. Detailed Output Signal Waveforms
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9.2 Typical Application
VIN = 3.3V
10µF
SN6505
4
3
GND
5
EN
ENABLE
CLOCK
6
CLK
1:2.2
MBR0520L
TPS76350
VOUT
D2
1
2
2
10µF 0.1µF
Vcc
1
3
IN
5
OUT
VOUT-REG = 5V
GND
EN
4
NC
10µF
D1
MBR0520L
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
3.3 V ± 3%
Output voltage
5V
Maximum load current
100 mA
9.2.2 Detailed Design Procedure
The following recommendations on components selection focus on the design of an efficient push-pull converter
with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter
output drops significantly over a wide range in load current. The characteristic curve in Figure 1 and Figure 11 for
example, shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a
transceiver’s supply range. Therefore, in order to provide a stable, load independent supply while maintaining
maximum possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.
The final converter circuit is shown in Figure 47. The measured VOUT and efficiency characteristics for the
regulated and unregulated outputs are shown in Figure 2 and Figure 12.
9.2.2.1 Drive Capability
The transformer driver is designed for low-power push-pull converters with input and output voltages in the range
of 2.25 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken that
higher turns ratios don’t lead to primary currents that exceed the specified current limits of the device.
9.2.2.2 LDO Selection
The minimum requirements for a suitable low dropout regulator are:
• Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore, for a load current of 600 mA, choose a 600 mA to 750 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
• The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain
efficiency. For a low-cost 750 mA LDO, a VDO of 600 mV at 750 mA is common. Be aware; however, that this
lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
• The required minimum input voltage preventing the regulator from dropping out of line regulation is given with:
VI-min = VDO-max + VO-max
(1)
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•
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This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO
and VO specified in the LDO data sheet for rated output current (that is, 600 mA) and add them together. Also
specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than VImin. If it is not, the LDO will lose line-regulation and any variations at the input passes straight through to the
output. Hence, below VI-min the output voltage follows the input and the regulator behaves like a simple
conductor.
The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this
condition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point, the
secondary reaches its maximum voltage of
VS-max = VIN-max × n
(2)
with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. Table 2 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters.
Table 2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTER
LDO
CONFIGURATION
VIN-max [V]
TURNS-RATIO
VS-max [V]
VI-max [V]
3.3 VIN to 3.3 VOUT
3.6
1.5 ± 3%
5.6
6 to 10
3.3 VIN to 5 VOUT
3.6
2.2 ± 3%
8.2
10
5 VIN to 5 VOUT
5.5
1.5 ± 3%
8.5
10
9.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. When used in high-frequency switching applications, such as the SN6505x-Q1 however, the diode
must also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly
recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperatures
of up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA
forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher
DC blocking voltage of 30 V.
Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above
Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier
output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as
RB168MM-40.
1
Forward Current, IF - A
Forward Current, IF - A
1
0°C
TJ = 100°C
75°C
25°C
-25°C
0.1
0.01
75°C
25°C
-40°C
0.1
0.01
0.1
0.2
0.3
0.4
Forward Voltage, VF - V
0.5
Figure 43. Diode Forward Characteristics for MBR0520L
20
TJ = 125°C
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0.2
0.3
0.4
Forward Voltage, VF - V
0.5
Figure 44. Diode Forward Characteristics MBR0530
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9.2.2.4 Capacitor Selection
The capacitors in the converter circuit in Figure 47 are multi-layer ceramic chip (MLCC) capacitors.
As with all high speed CMOS ICs, the device requires a bypass capacitor in the range of 10 nF to 100 nF.
The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast
switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a
dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the
supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a
reference plane or to the primary center-tap.
The bulk capacitor at the rectifier output smooths the output voltage. Make this capacitor 1 μF to 10 μF.
The small capacitor at the regulator input is not necessarily required. However, good analog design practice
suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection.
The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The
choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in
most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied
by the device. The maximum voltage delivered by the device is the nominal converter input plus 10%. The
maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified
input voltage. Therefore, the transformer’s minimum V-t product is determined through:
Vtmin ³ VIN-max ´
Tmax
=
2
VIN-max
2 ´ fmin
(3)
Taking an example of fmin as 138 kHz for SN6505A-Q1 and 363 kHZ for SN6505B-Q1 or SN6505D-Q1 with a 5
V supply, Equation 3 yields the minimum V-t products of:
Vtmin •
Vtmin •
5.5 V
2 x 138 kHz
5.5 V
2 x 363 kHz
= 20 Vµs
for SN6505A-Q1, and
= 7.6 Vµs
for SN6505B/D-Q1 applications.
(4)
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as
little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.
While Vt-wise all of these transformers can be driven by the device, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate
Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the
transformer chosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer web
sites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull
converter to operate flawlessly over the specified current and temperature range. This minimum transformation
ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction
factor that takes the transformer’s typical efficiency of 97% into account:
VP-min = VIN-min - VDS-max
(5)
VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the LDO Selection section, this
minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max
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VF
VI
VDO
VO
VS
VIN
RL
VP
VDS
RDS
Q
Figure 45. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible drainsource voltage of the device, VDS-max, from the minimum converter input voltage VIN-min:
VP-min = VIN-min – VDS-max
(7)
VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the data
sheet:
VDS-max = RDS-max × IDmax
(8)
Then inserting Equation 8 into Equation 7 yields:
VP-min = VIN-min - RDS-max x IDmax
(9)
and inserting Equation 9 and Equation 6 into Equation 5 provides the minimum turns ration with:
V
+ VDO-max + VO-max
nmin = 1.031 ´ F-max
VIN-min - RDS-max ´ ID-max
(10)
Example:
For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO, the data sheet values
taken for a load current of 600 mA and a maximum temperature of 85°C are VF-max = 0.2 V,
VDO-max = 0.5 V, and VO-max = 5.1 V.
Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%
accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at
3.3 V are taken from the data sheet with RDS-max = 0.31 Ω and ID-max = 1 A.
Inserting the values above into Equation 10 yields a minimum turns ratio of:
nmin = 1.031 ´
0.2 V + 0.5 V + 5.1 V
= 2.05
3.234 V - 0.31 Ω ´ 1 A
(11)
Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3
with a common tolerance of ±3%.
22
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SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
9.2.2.5.3 Recommended Transformers
Depending on the application, use the minimum configuration in Figure 46 or standard configuration in Figure 47.
Figure 46. Unregulated Output for Low-Current Loads With Wide Supply Range
Figure 47. Regulated Output for Stable Supplies and High Current Loads
The Wurth Electronics Midcom isolation transformers in Table 3 are optimized designs for the device, providing
high efficiency and small form factor at low-cost.
The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.
These applications operate without LDO, thus achieving further cost-reduction.
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23
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
www.ti.com
Table 3. Recommended Isolation Transformers Optimized for the Device
TURNS
RATIO
1:1.1 ±2%
V×T
(Vμs)
ISOLATION
(VRMS)
DIMENSIONS
(mm)
LDO (1)
APPLICATION
3.3 V → 3.3 V, 100mA, SN6505B/D-Q1
Refer to Figure 13 and Figure 14
7
ORDER NO.
760390011
1:1.1 ±2%
5 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 15 and Figure 16
1:1.7 ±2%
3.3 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 17 and Figure 18
760390013
3.3 V → 3.3 V, 100mA, SN6505B/D-Q1
Refer to Figure 19 and Figure 20
760390014
5 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 21 and Figure 22
760390014
6.73 x 10.05 x 4.19
1:1.3 ±2%
11
1:1.3 ±2%
1:2.1 ±2%
3.3 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 23 and Figure 24
2500
No
Yes
760390012
760390015
1.23:1 ±2%
5 V → 3.3 V, 100mA, SN6505B/D-Q1
750313710
1:1.7 ±2%
3.3 V → 3.3 V, 1A, SN6505B/D-Q1
Refer to Figure 25 and Figure 26
750316028
3.3 V → 5 V, 1A, SN6505B/D-Q1
Refer to Figure 27 and Figure 28
750316029
10.8
5 V → 3.3 V, 1A, SN6505B/D-Q1
Refer to Figure 29 and Figure 30
750316030
8.6
3.3 V → 3.3 V , 1A , SN6505B/D-Q1
5 V → 5 V , 1A , SN6505B/D-Q1
Refer to Figure 11 and Figure 12
8.9
1:2.1 ±2%
8.3 x 12.6 x 4.1
1.3:1 ±2%
1:1.1 ±2%
750315371
3.3 V → 3.3 V, 100mA, SN6505B/D-Q1
750313734
1:1.1 ±2%
5 V → 5 V, 100mA, SN6505B/D-Q1
750313734
1:1.7 ±2%
3.3 V → 5 V, 100mA, SN6505B/D-Q1
750313769
9.14 x 12.7 x 7.37
1:1.3 ±2%
3.3 V → 3.3 V, 100mA, SN6505B/D-Q1
5 V → 5 V, 100mA, SN6505B/D-Q1
1:2.1 ±2%
3.3 V → 5 V, 100mA, SN6505B/D-Q1
1.3:1 ±2%
5 V → 3.3 V, 100mA , SN6505B/D-Q1
No
750313638
3.3 V → 3.3 V, 1A, SN6505A-Q1
Refer to Figure 3 and Figure 4
Yes
750316031
5000
1:1.75 ±2%
41
1:2 ±2%
12.32 x 15.41 x 11.05
1.3:1 ±2%
42
1:1.1 ±2%
23
1:1.3 ±3%
11
1:1.5 ±3%
1:2.2 ±3%
(1)
Wurth Electronics /
Midcom
No
1:1.1 ±2%
11
34.4
21.5
2500
2500
750313626
750316032
No
12.32 x 15.41 x 11.89
3.3 V → 3.3 V, 1A, SN6505A-Q1
5 V → 5 V, 1A , SN6505A-Q1
Refer to Figure 1 and Figure 2
10.4 x 12.2 x 6.1
3.3 V → 3.3 V, 300mA, SN6505B/D-Q1
5 V → 5 V, 300mA , SN6505B/D-Q1
10 x 12.07 x 5.97
3.3 V → 3.3 V, 1A, SN6505A/B/D-Q1
5 V → 5 V, 1A , SN6505A/B/D-Q1
10 x 12.07 x 5.97
750313638
Yes
3.3 V → 5 V, 1A, SN6505A-Q1
Refer to Figure 5 and Figure 6
5.0 V → 3.3 V, 1A, SN6505A-Q1
Refer to Figure 7 and Figure 8
5000
MANUFACTURER
750316033
750315240
No
HCT-SM-1.3-8-2
Bourns
DA2303-AL
Yes
3.3 V → 5 V, 1A, SN6505A/B/D-Q1
Coilcraft
DA2304-AL
For configurations with LDO, a higher voltage than the required output voltage is generated, to allow for LDO drop-out. Figures show the
voltage and efficiency at the LDO input.
9.2.3 Application Curves
See theTypical Characteristics, SN6505A-Q1 and Typical Characteristics, SN6505B-Q1 or SN6505D-Q1 for
application curves with transformers optimized for the device, providing high efficiency and small form factor at
low-cost.
24
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www.ti.com
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
9.2.4 System Examples
9.2.4.1 Higher Output Voltage Designs
The device can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of
up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to
5, requires different rectifier topologies to achieve high output voltages. Figure 48 to Figure 50 show some of
these topologies together with their respective open-circuit output voltages.
n
n
VIN
VOUT = +n·VIN
VOUT = 2n·VIN
VIN
VOUT = -n·VIN
Figure 48. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputs
Figure 49. Bridge Rectifier Without Center-Tapped
Secondary Performs Voltage Doubling
VOUT = 4n·VIN
n
VIN
Figure 50. Half-Wave Rectifier Without Centered Ground and Center-Tapped Secondary Performs Voltage
Doubling Twice, Hence Quadrupling VIN
9.2.4.2 Application Circuits
The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated
microcontroller supply. For 5 V input voltages requiring different turn ratios refer to the transformer manufacturers
and their web sites listed in Table 4.
Table 4. Transformer Manufacturers
MANUFACTURER
MORE INFORMATION
Coilcraft Inc.
http://www.coilcraft.com
Halo-Electronics Inc.
http://www.haloelectronics.com
Murata Power Solutions
http://www.murata-ps.com
Wurth Electronics Midcom Inc
http://www.midcom-inc.com
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25
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
GND
www.ti.com
4
D2
3
SN6505-Q1
3.3 V
EN
1
8
VCC
3
2
7
6
1
5
2
CLK
D1
3.3 V
1
VDD
TXD
MCU
RXD
DGND
2
3
4
Digital
Ground
VCC1
VCC2
TXD
CANH
ISO1042-Q1CANL
OUT
5
EN
TPS76350-Q1
GND
NC
4
8
7
6
RXD
GND1
IN
Optional bus
protection
function
GND2
Galvanic
Isolation Barrier
5
ISO
Ground
Figure 51. Isolated CAN Interface
26
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www.ti.com
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5 V nominal. This input
supply must be regulated within ±10%. If the input supply is located more than a few inches from the device, a
0.1 μF by-pass capacitor should be connected as close as possible to the device VCC pin and a 10 μF capacitor
should be connected close to the transformer center-tap pin.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and
a X5R or X7R dielectric.
The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area
formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 52 for a PCB
layout example.
The connections between the device D1 and D2 pins and the transformer primary endings, and the
connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum
trace inductance.
The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a lowESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The
capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range
to maximize efficiency.
The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and
a X5R or X7R dielectric.
11.2 Layout Example
Figure 52. Layout Example of a 2-Layer Board
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27
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
• Texas Instruments, Small Form-Factor Reinforced Isolated IGBT Gate Drive Reference Design for 3-Phase
Inverter TI Design
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN6505A-Q1
Click here
Click here
Click here
Click here
Click here
SN6505B-Q1
Click here
Click here
Click here
Click here
Click here
SN6505D-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
E2E is a trademark of Texas Instruments.
28
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SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
www.ti.com
SLLSF95C – NOVEMBER 2018 – REVISED AUGUST 2019
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018–2019, Texas Instruments Incorporated
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29
PACKAGE OPTION ADDENDUM
www.ti.com
7-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN6505AQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
65AQ
SN6505AQDBVTQ1
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
65AQ
SN6505BQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
65BQ
SN6505BQDBVTQ1
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
65BQ
SN6505DQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
65DQ
SN6505DQDBVTQ1
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
65DQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Sep-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN6505A-Q1, SN6505B-Q1 :
• Catalog: SN6505A, SN6505B
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
SN6505AQDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN6505AQDBVTQ1
SOT-23
DBV
6
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN6505BQDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN6505BQDBVTQ1
SOT-23
DBV
6
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN6505DQDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN6505DQDBVTQ1
SOT-23
DBV
6
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN6505AQDBVRQ1
SOT-23
DBV
6
3000
213.0
191.0
35.0
SN6505AQDBVTQ1
SOT-23
DBV
6
250
213.0
191.0
35.0
SN6505BQDBVRQ1
SOT-23
DBV
6
3000
213.0
191.0
35.0
SN6505BQDBVTQ1
SOT-23
DBV
6
250
213.0
191.0
35.0
SN6505DQDBVRQ1
SOT-23
DBV
6
3000
213.0
191.0
35.0
SN6505DQDBVTQ1
SOT-23
DBV
6
250
213.0
191.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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