Texas Instruments | SN6501 Transformer Driver for Isolated Power Supplies (Rev. H) | Datasheet | Texas Instruments SN6501 Transformer Driver for Isolated Power Supplies (Rev. H) Datasheet

Texas Instruments SN6501 Transformer Driver for Isolated Power Supplies (Rev. H) Datasheet
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SN6501
SLLSEA0H – FEBRUARY 2012 – REVISED JULY 2019
SN6501 Transformer Driver for Isolated Power Supplies
1 Features
3 Description
•
•
•
The SN6501 is a monolithic oscillator/power-driver,
specifically designed for small form factor, isolated
power supplies in isolated interface applications. The
device drives a low-profile, center-tapped transformer
primary from a 3.3-V or 5-V DC power supply. The
secondary can be wound to provide any isolated
voltage based on transformer turns ratio.
1
•
•
Push-pull driver for small transformers
Single 3.3-V or 5-V supply
High primary-side current drive:
– 5-V Supply: 350 mA (Max)
– 3.3-V Supply: 150 mA (Max)
Low ripple on rectified output permits small output
capacitors
Small 5-Pin SOT-23 Package
2 Applications
•
•
•
•
Isolated interface power supply for CAN, RS-485,
RS-422, RS-232, SPI, I2C, Low-Power LAN
Industrial automation
Process control
Medical equipment
The SN6501 consists of an oscillator followed by a
gate drive circuit that provides the complementary
output signals to drive the ground referenced Nchannel power switches. The internal logic ensures
break-before-make action between the two switches.
The SN6501 is available in a small SOT-23 (5)
package, and is specified for operation at
temperatures from –40°C to 125°C.
Device Information(1)
PART NUMBER
SN6501
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Output Voltage and Efficiency vs Output Current
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN6501
SLLSEA0H – FEBRUARY 2012 – REVISED JULY 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
5
5
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (July 2014) to Revision H
Page
•
Added HCT-SM-1.3-8-2 transformer to Recommended Isolation Transformers Optimized for SN6501Table 4 table ........ 21
•
Added EPC3668G-LF transformer to Recommended Isolation Transformers Optimized for SN6501Table 4 table ........... 21
•
Added DA2303-AL transformer to Recommended Isolation Transformers Optimized for SN6501Table 4 table ................ 21
•
Added DA2304-AL transformer to Recommended Isolation Transformers Optimized for SN6501Table 4 table ................ 21
Changes from Revision F (August 2013) to Revision G
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision E (January 2013) to Revision F
Page
•
Added Figure 13 and Figure 14.............................................................................................................................................. 7
•
Added Figure 17 through Figure 18 ....................................................................................................................................... 7
•
Added Figure 23 through Figure 24 ....................................................................................................................................... 8
•
Changed Table 4 - Recommended Isolation Transformers Optimized for SN6501............................................................. 21
Changes from Revision D (September 2012) to Revision E
•
Page
Changed Figure 23................................................................................................................................................................. 8
Changes from Revision C (March 2012) to Revision D
Page
•
Changed fOSC, Oscillator frequency To: fSW, D1, D2 Switching frequency ............................................................................ 5
•
Added graphs Figure 3 through Figure 4 ............................................................................................................................... 6
•
Changed the title of Figure 30 From: D1, D2 Oscillator Frequency vs Free-Air Temperature To: D1, D2 Switching
2
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Frequency vs Free-Air Temperature ...................................................................................................................................... 9
•
Added section: Recommended Transformers ...................................................................................................................... 20
•
Changed the location and title of Figure 45 ......................................................................................................................... 20
Changes from Revision B (March 2012) to Revision C
Page
•
Changed the fOSC Oscillator frequency values ...................................................................................................................... 5
•
Changed Equation 4............................................................................................................................................................. 19
Changes from Revision A (March 2012) to Revision B
Page
•
Changed Feature From: Small 5-pin DBV Package To: Small 5-pin SOT23 Package.......................................................... 1
•
Changed Figure 45 title ........................................................................................................................................................ 20
Changes from Original (February 2012) to Revision A
Page
•
Changed the device From: Product Preview To: Production ................................................................................................. 1
•
Changed Equation 10........................................................................................................................................................... 20
•
Changed Equation 11........................................................................................................................................................... 20
•
Changed Table 5, From: Wuerth-Elektronik / Midcom To: Wurth Electronics Midcom Inc .................................................. 22
•
Changed Figure 54............................................................................................................................................................... 25
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5 Pin Configuration and Functions
5-Pin SOT-23
DBV Package
Top View
D1
1
VCC
2
D2
3
5
GND
4
GND
Table 1. Pin Functions
PIN
NAME
NUMBER
TYPE
D1
1
OD
VCC
2
P
D2
3
OD
GND
4,5
P
DESCRIPTION
Open Drain output 1. Connect this pin to one end of the transformer primary side.
Supply voltage input. Connect this pin to the center-tap of the transformer primary side. Buffer this
voltage with a 1 μF to 10 μF ceramic capacitor.
Open Drain output 2. Connect this pin to the other end of the transformer primary side.
Device ground. Connect this pin to board ground.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
UNIT
6
V
VCC
Supply voltage
VD1, VD2
Output switch voltage
14
V
ID1P, ID2P
Peak output switch current
500
mA
PTOT
Continuous power dissipation
250
mW
TJ
Junction temperature
170
°C
(1)
–0.3
MAX
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.
6.2 Handling Ratings
Tstg
MIN
MAX
UNIT
–65
150
°C
–4
4
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–1.5
1.5
Machine Model JEDEC JESD22-A115-A
–200
200
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
V(ESD)
(1)
(2)
4
Electrostatic discharge
kV
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
VCC
MIN
TYP MAX
3
5.5
0
11
0
7.2
Supply voltage
VD1, VD2
Output switch voltage
ID1, ID2
D1 and D2 output switch
current – Primary-side
TA
VCC = 5 V ± 10%,
VCC = 3.3 V ± 10%
When connected to Transformer with
primary winding Center-tapped
VCC = 5 V ± 10%
VD1, VD2 Swing ≥ 3.8 V,
see Figure 32 for typical characteristics
350
VCC = 3.3 V ± 10%
VD1, VD2 Swing ≥ 2.5 V,
see Figure 31 for typical characteristics
150
UNIT
V
V
mA
Ambient temperature
–40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
SN6501
DBV 5-PINS
θJA
Junction-to-ambient thermal resistance
208.3
θJCtop
Junction-to-case (top) thermal resistance
87.1
θJB
Junction-to-board thermal resistance
40.4
ψJT
Junction-to-top characterization parameter
5.2
ψJB
Junction-to-board characterization parameter
39.7
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted
PARAMETER
RON
Switch-on resistance
ICC
Average supply current (1)
fST
Startup frequency
fSW
D1, D2 Switching frequency
(1)
TEST CONDITIONS
MIN
TYP
MAX
1
3
VCC = 5 V ± 10%, See Figure 36
0.6
2
VCC = 3.3 V ± 10%, no load
150
400
VCC = 5 V ± 10%, no load
300
700
VCC = 2.4 V, See Figure 36
300
VCC = 3.3 V ± 10%, See Figure 36
UNIT
Ω
µA
kHz
VCC = 3.3 V ± 10%, See Figure 36
250
360
550
VCC = 5 V ± 10%, See Figure 36
300
410
620
MIN
TYP
kHz
Average supply current is the current used by SN6501 only. It does not include load current.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tr-D
D1, D2 output rise time
tf-D
D1, D2 output fall time
tBBM
Break-before-make time
TEST CONDITIONS
VCC = 3.3 V ± 10%, See Figure 36
70
VCC = 5 V ± 10%, See Figure 36
80
VCC = 3.3 V ± 10%, See Figure 36
VCC = 5 V ± 10%, See Figure 36
VCC = 3.3 V ± 10%, See Figure 36
VCC = 5 V ± 10%, See Figure 36
MAX
110
60
150
50
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UNIT
ns
ns
ns
5
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6.7 Typical Characteristics
TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35
(TA = 25°C unless otherwise noted). See Table 4 for Transformer Specifications.
90
80
5
TP1
70
Efficiency - %
VOUT - V
4
TP1
3
2
50
40
30
20
T1 = 760390011 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
1
0
60
0
T1 = 760390011 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
10
0
10 20 30 40 50 60 70 80 90 100
0
ILOAD - mA
ILOAD - mA
Figure 1. Output Voltage vs Load Current
Figure 2. Efficiency vs Load Current
90
6
TP1
80
5
Efficiency - %
70
VOUT - V
4
3
2
0
TP1
60
50
40
30
20
T1 = 760390012 (2.5kV)
VIN = 5V, VOUT = 5V
1
0
T1 = 760390012 (2.5kV)
VIN = 5V, VOUT = 5V
10
0
10 20 30 40 50 60 70 80 90 100
0
ILOAD - mA
Figure 3. Output Voltage vs. Load Current
Figure 4. Efficiency vs Load Current
90
TP1
80
5
Efficiency - %
VOUT - V
TP1
70
4
3
2
60
50
40
30
20
T1 = 760390013 (2.5kV)
VIN = 3.3V, VOUT = 5V
1
0
0
T1 = 760390013 (2.5kV)
VIN = 3.3V, VOUT = 5V
10
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
Figure 5. Output Voltage vs Load Current
6
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
6
0
10 20 30 40 50 60 70 80 90 100
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Figure 6. Efficiency vs Load Current
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Typical Characteristics (continued)
TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35
(TA = 25°C unless otherwise noted). See Table 4 for Transformer Specifications.
90
5
TP1
3
Efficiency - %
VOUT - V
4
TP2
2
0
0
TP1
70
TP2
60
50
40
30
20
T1 = 760390014 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
1
80
T1 = 760390014 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
10
0
10 20 30 40 50 60 70 80 90 100
0
ILOAD - mA
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
Figure 7. Output Voltage vs Load Current
Figure 8. Efficiency vs Load Current
8
90
TP1
80
7
TP1
70
5
Efficiency - %
VOUT - V
6
TP2
4
3
2
50
40
30
20
T1 = 760390014 (2.5kV)
VIN = 5V, VOUT = 5V
1
0
TP2
60
0
T1 = 760390014 (2.5kV)
VIN = 5V, VOUT = 5V
10
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
0
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
Figure 9. Output Voltage vs Load Current
Figure 10. Efficiency vs Load Current
7
TP1
VOUT - V
6
5
TP2
4
3
2
T1 = 760390015 (2.5kV)
VIN = 3.3V, VOUT = 5V
1
0
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
Figure 11. Output Voltage vs Load Current
Figure 12. Efficiency vs Load Current
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Typical Characteristics (continued)
TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35
(TA = 25°C unless otherwise noted). See Table 4 for Transformer Specifications.
90
80
5
TP1
4
TP1
3
TP2
Efficiency - %
VOUT - V
70
2
0
0
50
40
30
20
T1 = 750313710 (2.5kV)
VIN = 5V, VOUT = 3.3V
1
TP2
60
T1 = 750313710 (2.5kV)
VIN = 5V, VOUT = 3.3V
10
0
10 20 30 40 50 60 70 80 90 100
0
ILOAD - mA
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
Figure 13. Output Voltage vs Load Current
Figure 14. Efficiency vs Load Current
90
6
80
5
TP1
70
Efficiency - %
VOUT - V
4
TP1
3
2
T1 = 750313734 (5kV)
VIN = 3.3V, VOUT = 3.3V
1
0
60
50
40
30
20
T1 = 750313734 (5kV)
VIN = 3.3V, VOUT = 3.3V
10
0
10 20 30 40 50 60 70 80 90 100
0
ILOAD - mA
0
Figure 15. Output Voltage vs Load Current
Figure 16. Efficiency vs Load Current
90
6
TP1
80
5
Efficiency - %
70
VOUT - V
4
3
2
40
30
T1 = 750313734 (5kV)
VIN = 5V, VOUT = 5V
10
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
Figure 17. Output Voltage vs Load Current
8
50
0
0
TP1
60
20
T1 = 750313734 (5kV)
VIN = 5V, VOUT = 5V
1
0
10 20 30 40 50 60 70 80 90 100
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Figure 18. Efficiency vs Load Current
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Typical Characteristics (continued)
TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35
(TA = 25°C unless otherwise noted). See Table 4 for Transformer Specifications.
Figure 19. Output Voltage vs Load Current
Figure 20. Efficiency vs Load Current
90
6
Efficiency - %
VOUT - V
TP2
70
TP1
4
3
TP2
2
60
50
40
30
20
1
0
TP1
80
5
T1 = 750313638 (5kV)
VIN = 3.3V, VOUT = 3.3V
0
T1 = 750313638 (5kV)
VIN = 3.3V, VOUT = 3.3V
10
0
10 20 30 40 50 60 70 80 90 100
0
Figure 21. Output Voltage vs Load Current
Figure 22. Efficiency vs Load Current
8
90
80
7
TP1
Efficiency - %
VOUT - V
5
TP1
70
6
TP2
4
3
2
TP2
60
50
40
30
20
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 5V
1
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
0
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 5V
10
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
0
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
Figure 23. Output Voltage vs Load Current
Figure 24. Efficiency vs Load Current
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Typical Characteristics (continued)
TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35
(TA = 25°C unless otherwise noted). See Table 4 for Transformer Specifications.
90
8
80
7
6
VOUT - V
TP2
60
5
TP2
50
4
40
3
30
2
20
T1 = 750313626 (5kV)
VIN = 3.3V, VOUT = 5V
1
0
TP1
70
TP1
0
0
T1 = 750313626 (5kV)
VIN = 3.3V, VOUT = 5V
10
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
Figure 26. Efficiency vs Load Current
Figure 25. Output Voltage vs Load Current
90
6
80
5
TP1
4
TP1
3
TP2
Efficiency - %
VOUT - V
70
2
1
0
50
40
30
20
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 3.3V
0
TP2
60
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 3.3V
10
10 20 30 40 50 60 70 80 90 100
0
ILOAD - mA
0
Figure 28. Efficiency vs Load Current
Figure 27. Output Voltage vs Load Current
460
300
440
VCC = 5V
f - Frequency - kHz
ICC – Supply Current - µA
350
250
200
150
VCC = 3.3V
100
VCC = 5V
420
400
380
VCC = 3.3V
360
340
50
0
-55 -35 -15
10
10 20 30 40 50 60 70 80 90 100
5
25
45
65
85 105 125
320
-55 -35 -15
5
25
45
65
85 105 125
TA - Free Air Temperature - oC
TA - Free Air Temperature - oC
Figure 29. Average Supply Current vs Free-Air Temperature
Figure 30. D1, D2 Switching Frequency vs Free-Air
Temperature
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Typical Characteristics (continued)
TP1 Curves are measured with the Circuit in Figure 33; whereas, TP1 and TP2 Curves are measured with Circuit in Figure 35
(TA = 25°C unless otherwise noted). See Table 4 for Transformer Specifications.
5.00
VD1, VD2 - Voltage Swing - V
VD1, VD2 - Voltage Swing - V
3.30
3.25
VCC = 3.3V
3.20
3.15
3.10
3.05
3.00
0
50
100
150
200
4.95
VCC = 5V
4.90
4.85
4.80
4.75
4.70
4.65
4.60
4.55
0
100
200
300
400
ID1, ID2 - Switching Current - mA
ID1, ID2 - Switching Current - mA
Figure 31. D1, D2 Primary-Side Output Switch Voltage
Swing vs Current
Figure 32. D1, D2 Primary-Side Output Switch Voltage
Swing vs Current
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7 Parameter Measurement Information
VIN
SN6501
4
T1
3
GND
MBR0520L
TP1
D2
VCC
5
1µ F
2
1
GND
D1
0.1µF
MBR0520L
Figure 33. Measurement Circuit for Unregulated Output (TP1)
Figure 34. Timing Diagram
VIN
10µF
SN6501
4
GND
D2
Vcc
5
T1
3
MBR0520L
1
2
10µF 0.1 µF
2
3
1
GND
LDO
TP1
IN
OUT
TP2
GND
EN
VOUT
5
10µF
NC
4
D1
0.1µF
MBR0520L
Figure 35. Measurement Circuit for regulated Output (TP1 and TP2)
12
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Parameter Measurement Information (continued)
VIN
SN6501
4
GND D2
VCC
5
GND D1
3 50W
10µF
2
1 50W
Figure 36. Test Circuit For RON, FSW, FSt, Tr-D, Tf-D, TBBM
8 Detailed Description
8.1 Overview
The SN6501 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing
the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time
between the high-pulses of the two signals. The resulting output signals, present the gate-drive signals for the
output transistors. As shown in the functional block diagram, before either one of the gates can assume logic
high, there must be a short time period during which both signals are low and both transistors are highimpedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of
the primary.
8.2 Functional Block Diagram
SN6501
D1
Q
OSC
VCC
Gate
Drive
D2
Q
GND
GND
8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary
(see Figure 37).
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Feature Description (continued)
CR1
CR1
VOUT
C
C
RL
VIN
RL
VIN
CR2
Q2
VOUT
CR2
Q1
Q2
Q1
Figure 37. Switching Cycles of a Push-Pull Converter
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative
voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.
Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting
from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance
RL back to the center-tap.
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
Figure 38 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H
as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2
conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the
product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON.
B
VIN
A’
VP
H
RDS
VDS
A
VIN = VP + VDS
Figure 38. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from
the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the
transformer slowly creeps toward the saturation region.
14
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Feature Description (continued)
Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the
SN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged
current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher
resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the
difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VP
is gradually reduced and V-t balance restored.
8.4 Device Functional Modes
The functional modes of the SN6501 are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When the supply voltage at Vcc ramps up to 2.4 V typical, the internal oscillator starts operating at a start
frequency of 300 kHz. The output stage begins switching but the amplitude of the drain signals at D1 and D2 has
not reached its full maximum yet.
8.4.2 Operating Mode
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations
over supply voltage and operating temperature can vary the switching frequencies at D1 and D2 between 250
kHz and 550 kHz for VCC = 3.3 V ±10%, and between 300 kHz and 620 kHz for VCC = 5 V ±10%.
8.4.3 Off-Mode
The SN6501 is deactivated by reducing VCC to 0 V. In this state both drain outputs, D1 and D2, are highimpedance.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN6501 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing
the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
Vcc
SN6501
Q2 off
Q1 off
D2
OSC
fOSC
S
G2
Freq.
Divider S
BBM
Logic G1
Q2
D1
Q1
Q1 on
GND
tBBM
Q2 on
GND
Figure 39. SN6501 Block Diagram And Output Timing With Break-Before-Make Action
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gatedrive signals for the output transistors Q1 and Q2. As shown in Figure 40, before either one of the gates can
assume logic high, there must be a short time period during which both signals are low and both transistors are
high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends
of the primary.
fOSC
S
S
G1
G2
Q1
Q2
Figure 40. Detailed Output Signal Waveforms
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9.2 Typical Application
VIN = 3.3V
10µF
SN6501
4
3
GND
1:2.2
MBR0520L
TPS76350
VOUT
D2
1
2
2
10µF 0.1µF
Vcc
3
1
5
GND
IN
OUT
VOUT-REG = 5V
5
GND
EN
NC
10µF
4
D1
MBR0520L
Figure 41. Typical Application Schematic (SN6501)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as design parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
3.3 V ± 3%
Output voltage
5V
Maximum load current
100 mA
9.2.2 Detailed Design Procedure
The following recommendations on components selection focus on the design of an efficient push-pull converter
with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter
output drops significantly over a wide range in load current. The characteristic curve in Figure 11 for example
shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a transceiver’s
supply range. Therefore, in order to provide a stable, load independent supply while maintaining maximum
possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.
The final converter circuit is shown in Figure 45. The measured VOUT and efficiency characteristics for the
regulated and unregulated outputs are shown in Figure 1 to Figure 28.
9.2.2.1 SN6501 Drive Capability
The SN6501 transformer driver is designed for low-power push-pull converters with input and output voltages in
the range of 3 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken
that higher turns ratios don’t lead to primary currents that exceed the SN6501 specified current limits.
9.2.2.2 LDO Selection
The minimum requirements for a suitable low dropout regulator are:
• Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore for a load current of 100 mA, choose a 100 mA to 150 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
• The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain
efficiency. For a low-cost 150 mA LDO, a VDO of 150 mV at 100 mA is common. Be aware however, that this
lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
• The required minimum input voltage preventing the regulator from dropping out of line regulation is given with:
VI-min = VDO-max + VO-max
(1)
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•
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This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO
and VO specified in the LDO data sheet for rated output current (i.e., 100 mA) and add them together. Also
specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than VImin. If it is not, the LDO will lose line-regulation and any variations at the input will pass straight through to the
output. Hence below VI-min the output voltage will follow the input and the regulator behaves like a simple
conductor.
The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this
condition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point the
secondary reaches its maximum voltage of
VS-max = VIN-max × n
(2)
with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. Table 3 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters with 100 mA output drive.
Table 3. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTER
LDO
CONFIGURATION
VIN-max [V]
TURNS-RATIO
VS-max [V]
VI-max [V]
3.3 VIN to 3.3 VOUT
3.6
1.5 ± 3%
5.6
6 to 10
3.3 VIN to 5 VOUT
3.6
2.2 ± 3%
8.2
10
5 VIN to 5 VOUT
5.5
1.5 ± 3%
8.5
10
9.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. When used in high-frequency switching applications, such as the SN6501 however, the diode must
also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly
recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperatures
of up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA
forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher
DC blocking voltage of 30 V.
Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above
Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier
output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as
RB168M-40.
1
Forward Current, IF - A
Forward Current, IF - A
1
0°C
TJ = 100°C
75°C
25°C
-25°C
0.1
0.01
TJ = 125°C
75°C
25°C
-40°C
0.1
0.01
0.1
0.2
0.3
0.4
Forward Voltage, VF - V
0.5
0.2
0.3
0.4
Forward Voltage, VF - V
0.5
Figure 42. Diode Forward Characteristics for MBR0520L (Left) and MBR0530 (Right)
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9.2.2.4 Capacitor Selection
The capacitors in the converter circuit in Figure 45 are multi-layer ceramic chip (MLCC) capacitors.
As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF.
The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast
switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a
dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the
supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a
reference plane or to the primary center-tap.
The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 1 μF to 10 μF.
The small capacitor at the regulator input is not necessarily required. However, good analog design practice
suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection.
The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The
choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in
most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied
by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input plus 10%. The
maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified
input voltage. Therefore, the transformer’s minimum V-t product is determined through:
Vtmin ³ VIN-max ´
Tmax
2
=
VIN-max
2 ´ fmin
(3)
Inserting the numeric values from the data sheet into the equation above yields the minimum V-t products of
Vtmin ³
3.6 V
= 7.2 Vμs
2 ´ 250 kHz
Vtmin ³
5.5 V
= 9.1 Vμs for 5 V applications.
2 ´ 300 kHz
for 3.3 V, and
(4)
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as
little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.
While Vt-wise all of these transformers can be driven by the SN6501, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate
Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the
transformer choosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer
websites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull
converter to operate flawlessly over the specified current and temperature range. This minimum transformation
ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction
factor that takes the transformer’s typical efficiency of 97% into account:
VP-min = VIN-min - VDS-max
(5)
VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the LDO SELECTION section, this
minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max
(6)
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VF
VI
VDO
VO
VS
VIN
RL
VP
VDS
RDS
Q
Figure 43. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible drainsource voltage of the SN6501, VDS-max, from the minimum converter input voltage VIN-min:
VP-min = VIN-min – VDS-max
(7)
VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the SN6501
data sheet:
VDS-max = RDS-max × IDmax
(8)
Then inserting Equation 8 into Equation 7 yields:
VP-min = VIN-min - RDS-max x IDmax
(9)
and inserting Equation 9 and Equation 6 into Equation 5 provides the minimum turns ration with:
V
+ VDO-max + VO-max
nmin = 1.031 ´ F-max
VIN-min - RDS-max ´ ID-max
(10)
Example:
For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO TPS76350, the data
sheet values taken for a load current of 100 mA and a maximum temperature of 85°C are VF-max = 0.2 V,
VDO-max = 0.2 V, and VO-max = 5.175 V.
Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%
accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at
3.3 V are taken from the SN6501 data sheet with RDS-max = 3 Ω and ID-max = 150 mA.
Inserting the values above into Equation 10 yields a minimum turns ratio of:
0.2V + 0.2V + 5.175 V
nmin = 1.031 ´
=2
3.234 V - 3 Ω ´ 150 mA
(11)
Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3
with a common tolerance of ±3%.
9.2.2.5.3 Recommended Transformers
Depending on the application, use the minimum configuration in Figure 44 or standard configuration in Figure 45.
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VIN
VIN
10µF
SN6501
4
T1
3
GND
MBR0520L
TP1
SN6501
4
D2
VCC
5
1µ F
2
D2
Vcc
5
T1
3
LDO
TP1
1
2
10µF 0.1 µF
2
3
IN
TP2
OUT
GND
EN
VOUT
5
10µF
NC
4
D1
0.1µF
D1
0.1µF
MBR0520L
1
GND
1
GND
GND
MBR0520L
MBR0520L
Figure 44. Unregulated Output for Low-Current
Loads With Wide Supply Range
Figure 45. Regulated Output for Stable Supplies
and High Current Loads
The Wurth Electronics Midcom isolation transformers in Table 4 are optimized designs for the SN6501, providing
high efficiency and small form factor at low-cost.
The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.
These applications operate without LDO, thus achieving further cost-reduction.
Table 4. Recommended Isolation Transformers Optimized for SN6501
Turns
Ratio
VxT
(Vμs)
1:1.1 ±2%
7
Isolation
(VRMS)
Dimensions
(mm)
Application
LDO
3.3 V → 3.3 V
Figures
Order No.
Figure 1
Figure 2
760390011
Figure 3
Figure 4
760390012
1:1.1 ±2%
5V→5V
1:1.7 ±2%
3.3 V → 5 V
Figure 5
Figure 6
760390013
3.3 V → 3.3 V
5V→5V
Figure 7
Figure 8
Figure 9
Figure 10
760390014
2500
1:1.3 ±2%
6.73 x 10.05 x 4.19
11
No
Yes
1:2.1 ±2%
3.3 V → 5 V
Figure 11
Figure 12
760390015
1.23:1 ±2%
5 V → 3.3 V
Figure 13
Figure 14
750313710
1:1.1 ±2%
3.3 V → 3.3 V
Figure 15
Figure 16
750313734
1:1.1 ±2%
5V→5V
Figure 17
Figure 18
750313734
1:1.7 ±2%
3.3 V → 5 V
Figure 19
Figure 20
750313769
1:1.3 ±2%
3.3 V → 3.3 V
5V→5V
Figure 21
Figure 22
Figure 23
Figure 24
750313638
1:2.1 ±2%
3.3 V → 5 V
Figure 25
Figure 26
750313626
1.3:1 ±2%
5 V → 3.3 V
Figure 27
Figure 28
750313638
11
5000
9.14 x 12.7 x 7.37
No
Yes
Manufacturer
Wurth
Electronics/
Midcom
1:1.3 ±3%
11
5000
10.4 x 12.2 x 6.1
3.3 V → 3.3 V
5V→5V
No
N/A
HCT-SM-1.3-8-2
Bourns
1:1.1 ±2%
9.2
2500
7.01 x 11 x 4.19
3.3 V → 3.3 V
5V→5V
No
N/A
EPC3668G-LF
PCA Electronics
1:1.5 ±3%
34.4
2500
10 x 12.07 x 5.97
3.3 V → 3.3 V
5V→5V
Yes
N/A
1:2.2 ±3%
21.5
2500
10 x 12.07 x 5.97
3.3 V → 5 V
DA2303-AL
Coilcraft
DA2304-AL
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9.2.3 Application Curve
See Table 4 for application curves.
9.2.4 Higher Output Voltage Designs
The SN6501 can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of
up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to
5, requires different rectifier topologies to achieve high output voltages. Figure 46 to Figure 49 show some of
these topologies together with their respective open-circuit output voltages.
n
n
VOUT+ = n·VIN
VIN
VOUT = 2n·VIN
VIN
VOUT- = n·VIN
Figure 46. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputs
Figure 47. Bridge Rectifier Without Center-Tapped
Secondary Performs Voltage Doubling
VOUT+ = 2n·V IN
n
VIN
VOUT = 4n·VIN
n
VIN
VOUT- = 2n·V IN
Figure 48. Half-Wave Rectifier Without CenterTapped Secondary Performs Voltage Doubling,
Centered Ground Provides Bipolar Outputs
Figure 49. Half-Wave Rectifier Without Centered
Ground and Center-Tapped Secondary Performs
Voltage Doubling Twice, Hence Quadrupling VIN
9.2.5 Application Circuits
The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated
micro-controller supply. For 5 V input voltages requiring different turn ratios refer to the transformer
manufacturers and their websites listed in Table 5.
Table 5. Transformer Manufacturers
22
Coilcraft Inc.
http://www.coilcraft.com
Halo-Electronics Inc.
http://www.haloelectronics.com
Murata Power Solutions
http://www.murata-ps.com
Wurth Electronics Midcom Inc
http://www.midcom-inc.com
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Figure 50. Isolated RS-485 Interface
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Figure 51. Isolated Can Interface
Figure 52. Isolated RS-232 Interface
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Figure 53. Isolated Digital Input Module
Figure 54. Isolated SPI Interface for an Analog Input Module With 16 Inputs
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Figure 55. Isolated I2C Interface for an Analog Data Acquisition System With 4 Inputs and 4 Outputs
VS
3.3 V
0.1 F
2
VCC D2 3
1:1.33
MBR0520L
1
SN6501
10 F
GND D1
0.1 F
IN
OUT
3.3VISO
5
10 F
TPS76333
3
1
EN
GND
2
10 F
MBR0520L
4, 5
0.1 F
ISO-BARRIER
0.1 F
20
LOOP+
0.1 F
0.1 F
15
0.1 F
10
1
8
2
5
6
VCC1
DVCC
XOUT
XIN
MSP430
G2132
8
P3.0 11
12
P3.1
DVSS
4
VCC2
2 OUTA
INA
ISO7421
3 INB
OUTB
GND1
4
GND2
5
7
5
6
4
3
VA
VD
LOW
BASE
ERRLVL
16
0.1 F
DAC161P997
22
DBACK
DIN
C1
14
3 × 22 nF
1 F
C2
13
C3 COMA
12
1
OUT
COMD
9
LOOP±
2
Figure 56. Isolated 4-20 mA Current Loop
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3.3 V and 5 V nominal. This input
supply must be regulated within ±10%. If the input supply is located more than a few inches from the SN6501 a
0.1 μF by-pass capacitor should be connected as possible to the device VCC pin, and a 10 μF capacitor should
be connected close to the transformer center-tap pin.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and
a X5R or X7R dielectric.
The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area
formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 57 for a PCB
layout example.
The connections between the device D1 and D2 pins and the transformer primary endings, and the
connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum
trace inductance.
• The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a lowESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The
capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range
to maximize efficiency.
The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and
a X5R or X7R dielectric.
11.2 Layout Example
Figure 57. Layout Example of a 2-Layer Board (SN6501)
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Copyright © 2012–2019, Texas Instruments Incorporated
Product Folder Links: SN6501
27
SN6501
SLLSEA0H – FEBRUARY 2012 – REVISED JULY 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 2012–2019, Texas Instruments Incorporated
Product Folder Links: SN6501
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN6501DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
6501
SN6501DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
6501
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2019
OTHER QUALIFIED VERSIONS OF SN6501 :
• Automotive: SN6501-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
SN6501DBVR
SOT-23
DBV
5
3000
178.0
9.0
SN6501DBVT
SOT-23
DBV
5
250
178.0
9.0
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.3
3.2
1.4
4.0
8.0
Q3
3.3
3.2
1.4
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN6501DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN6501DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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