Texas Instruments | ISO776x-Q1 High-speed, robust EMC, reinforced six-channel digital isolators (Rev. A) | Datasheet | Texas Instruments ISO776x-Q1 High-speed, robust EMC, reinforced six-channel digital isolators (Rev. A) Datasheet

Texas Instruments ISO776x-Q1 High-speed, robust EMC, reinforced six-channel digital isolators (Rev. A) Datasheet
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ISO7760-Q1, ISO7761-Q1
ISO7762-Q1, ISO7763-Q1
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ISO776x-Q1 High-speed, robust EMC, reinforced six-channel digital isolators
1 Features
3 Description
•
•
The ISO776x-Q1 devices are high-performance, sixchannel digital isolators with 5000-VRMS (DW
package) and 3000-VRMS (DBQ package) isolation
ratings per UL 1577. This family of devices is also
certified according to VDE, CSA, TUV and CQC.
1
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient temperature range
– Device HBM ESD classification level 3A
– Device CDM ESD classification level C6
100 Mbps data rate
Robust isolation barrier:
– >100-Year projected lifetime
– Up to 5000 VRMS isolation rating
– Up to 12.8 kV surge capability
– ±100 kV/μs Typical CMTI
Wide supply range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level translation
Default output high (ISO776x) and low
(ISO776xF) Options
Low power consumption, typical 1.4 mA per
channel at 1 Mbps
Low propagation delay: 11 ns typical at 5 V
Robust Electromagnetic Compatibility (EMC):
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 Contact discharge
protection across isolation barrier
– Low emissions
Wide-SOIC (DW-16) and SSOP (DBQ-16)
package options
Safety-related certifications:
– Reinforced insulation per DIN V VDE V 088411:2017-01
– UL 1577 component recognition program
– CSA Certification per IEC 60950-1, IEC 623681, and IEC 60601-1
– CQC Certification per GB4943.1-2011
– TUV Certification according to EN 60950-1 and
EN 61010-1
The ISO776x-Q1 family of devices provides highelectromagnetic immunity and low emissions at lowpower consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic-input and logic-output buffer separated by a
double capacitive silicon dioxide (SiO2) insulation
barrier. The ISO776x-Q1 family of devices is
available in all possible pin configurations such that
all six channels are in the same direction, or one,
two, or three channels are in reverse direction while
the remaining channels are in forward direction. If the
input power or signal is lost, the default output is high
for devices without suffix F and low for devices with
suffix F. See the Device Functional Modes section for
further details.
Used in conjunction with isolated power supplies, this
family of devices helps prevent noise currents on
data buses, such as CAN and LIN, or other circuits
from entering the local ground and interfering with or
damaging sensitive circuitry. Through innovative chip
design and layout techniques, electromagnetic
compatibility of the ISO776x-Q1 family of devices has
been significantly enhanced to ease system-level
ESD, EFT, surge, and emissions compliance. The
ISO776x-Q1 family of devices is available in 16-pin
SOIC and SSOP packages.
Device Information(1)
PART NUMBER
ISO7760-Q1
ISO7761-Q1
ISO7762-Q1
IOS7763-Q1
Hybrid, electric and power train system (EV/HEV)
– Battery management system (BMS)
– On-board charger
– Traction inverter
– DC/DC converter
– Starter/generator
BODY SIZE (NOM)
10.30 mm × 7.50 mm
SSOP (16)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
2 Applications
•
PACKAGE
SOIC (16)
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input VCC, VCCO=Output VCC
GNDI=Input ground, GNDO=Output ground
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7760-Q1, ISO7761-Q1
ISO7762-Q1, ISO7763-Q1
SLLSEU7A – NOVEMBER 2018 – REVISED MARCH 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics—5-V Supply ..................... 9
Supply Current Characteristics—5-V Supply ........ 10
Electrical Characteristics—3.3-V Supply .............. 11
Supply Current Characteristics—3.3-V Supply ..... 12
Electrical Characteristics—2.5-V Supply .............. 13
Supply Current Characteristics—2.5-V Supply ..... 14
Switching Characteristics—5-V Supply................. 15
Switching Characteristics—3.3-V Supply.............. 15
Switching Characteristics—2.5-V Supply.............. 16
Insulation Characteristics Curves ......................... 17
6.19 Typical Characteristics .......................................... 18
7
8
Parameter Measurement Information ................ 21
Detailed Description ............................................ 22
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
22
22
23
24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2018) to Revision A
•
2
Page
Changed CPG parameter description From: "External clearance" To: "External creepage" in Insulation
Specifications table ................................................................................................................................................................ 7
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5 Pin Configuration and Functions
ISO7760-Q1 DW and DBQ Packages
16-Pin SOIC and SSOP
Top View
ISO7761-Q1 DW and DBQ Packages
16-Pin SOIC and SSOP
Top View
16 VCC2
VCC1
1
16 VCC2
INA
2
15 OUTA
INA
2
15 OUTA
INB
3
14 OUTB
INB
3
14 OUTB
INC
4
13 OUTC
INC
4
IND
5
12 OUTD
IND
5
INE
6
11 OUTE
INE
6
INF
7
10 OUTF
OUTF 7
GND1 8
9 GND2
GND1 8
ISO7762-Q1 DW and DBQ Packages
16-Pin SOIC and SSOP
Top View
ISOLATION
1
ISOLATION
VCC1
13 OUTC
12 OUTD
11 OUTE
10
INF
9 GND2
ISO7763-Q1 DW and DBQ Packages
16-Pin SOIC and SSOP
Top View
16 VCC2
VCC1
1
16 VCC2
INA
2
15 OUTA
INA
2
15 OUTA
INB
3
14 OUTB
INB
3
14 OUTB
INC
4
13 OUTC
INC
4
IND
5
12 OUTD
OUTD 5
OUTE 6
11
INE
OUTF 7
10
INF
GND1 8
9 GND2
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ISOLATION
1
ISOLATION
VCC1
13 OUTC
12
IND
OUTE 6
11
INE
OUTF 7
10
INF
GND1 8
9 GND2
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Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ISO7760-Q1
ISO7761-Q1
ISO7762-Q1
ISO7763-Q1
GND1
8
8
8
8
—
Ground connection for VCC1
GND2
9
9
9
9
—
Ground connection for VCC2
INA
2
2
2
2
I
Input, channel A
INB
3
3
3
3
I
Input, channel B
INC
4
4
4
4
I
Input, channel C
IND
5
5
5
12
I
Input, channel D
INE
6
6
11
11
I
Input, channel E
INF
7
10
10
10
I
Input, channel F
OUTA
15
15
15
15
O
Output, channel A
OUTB
14
14
14
14
O
Output, channel B
OUTC
13
13
13
13
O
Output, channel C
OUTD
12
12
12
5
O
Output, channel D
OUTE
11
11
6
6
O
Output, channel E
OUTF
10
7
7
7
O
Output, channel F
VCC1
1
1
1
1
—
Power supply, side 1
VCC2
16
16
16
16
—
Power supply, side 2
4
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
VCC1,
VCC2
Supply voltage (2)
MIN
MAX
–0.5
6
V
Voltage at INx, OUTx
–0.5
IO
Output current
–15
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
V
VCCX + 0.5
–65
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
(1)
UNIT
±6000
Charged-device model (CDM), per AEC Q100-011
±1500
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test (2) (3)
±8000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2 Supply voltage
NOM
2.25
UNIT
5.5
V
2.25
V
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
High-level output current
IOL
Low-level output current
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
mA
(1)
VCCI
Low-level input voltage
0
0.3 × VCCI
Data rate
0
100
Mbps
125
°C
VIH
High-level input voltage
VIL
DR (2)
TA
Ambient temperature
(1)
(2)
2
MAX
0.7 × VCCI
-40
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
100 Mbps is the maximum specified data rate, although higher data rates are possible.
Copyright © 2018–2019, Texas Instruments Incorporated
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6.4 Thermal Information
ISO776x-Q1
THERMAL METRIC (1)
DW (SOIC)
DBQ (SSOP)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
60.3
86.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
24.0
26.9
°C/W
RθJB
Junction-to-board thermal resistance
29.3
36.6
°C/W
ψJT
Junction-to-top characterization parameter
3.3
1.7
°C/W
ψJB
Junction-to-board characterization parameter
28.7
36.1
°C/W
n/a
n/a
°C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7760-Q1
PD
Maximum power dissipation (both sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
292
mW
PD1
Maximum power dissipation (side 1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
50
mW
PD2
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
242
mW
ISO7761-Q1
PD
Maximum power dissipation (both sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
292
mW
PD1
Maximum power dissipation (side 1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
83
mW
PD2
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
209
mW
ISO7762-Q1
PD
Maximum power dissipation (both sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
292
mW
PD1
Maximum power dissipation (side 1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
116
mW
PD2
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
176
mW
ISO7763-Q1
PD
Maximum power dissipation (both sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
292
mW
PD1
Maximum power dissipation (side 1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
146
mW
PD2
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
146
mW
6
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6.6 Insulation Specifications
VALUE
PARAMETER
TEST CONDITIONS
DW-16
DBQ16
UNIT
>8
>3.7
mm
Shortest terminal-to-terminal distance across the package surface
>8
>3.7
mm
Minimum internal gap (internal clearance)
>21
>21
μm
>600
>600
V
CLR
External clearance (1)
CPG
External creepage
(1)
DTI
Distance through the insulation
CTI
Tracking resistance (comparative
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
tracking index)
Shortest terminal-to-terminal distance through air
Material group
According to IEC 60664-1
Overvoltage category per IEC
60664-1
I
I
Rated mains voltage ≤ 150 VRMS
I–IV
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Rated mains voltage ≤ 600 VRMS
I–IV
n/a
Rated mains voltage ≤ 1000 VRMS
I–III
n/a
AC voltage (bipolar)
2121
566
VPK
AC voltage; Time dependent dielectric breakdown (TDDB) test; see
Figure 30
1500
400
VRMS
DIN V VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
DC voltage
2121
566
VDC
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM , t = 60 s (qualification)
VTEST = 1.2 x VIOTM, t = 1 s (100% production)
8000
4242
VPK
VIOSM
Maximum surge isolation
voltage (3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
4000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
Method b1; At routine test (100% production) and preconditioning
(type test)
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
≤5
VIO = 0.4 × sin (2πft), f = 1 MHz
~1.1
~0.9
VIO = 500 V, TA = 25°C
>1012
>1012
11
>1011
9
>10
>109
Pollution degree
2
2
Climatic category
55/125/
21
55/125/
21
5000
3000
Apparent charge (4)
qpd
Barrier capacitance, input to
output (5)
CIO
RIO
Isolation resistance
(5)
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>10
VIO = 500 V, TS = 150°C
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
Certified according to
DIN V VDE V 088411:2017-01
Certified according to IEC
60950-1, IEC 62368-1 and
IEC 60601-1
Reinforced Insulation;
Maximum transient
isolation voltage, 8000
VPK (DW-16) and 4242
VPK (DBQ-16);
Maximum repetitive
peak isolation voltage,
2121 VPK (DW-16) and
566 VPK (DBQ-16);
Maximum surge
isolation voltage, 8000
VPK (DW-16) and 4000
VPK (DBQ-16)
Reinforced insulation per
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2, CSA 62368-114 and IEC 62368-1:2014
800 VRMS (DW-16) and 370
VRMS (DBQ-16) maximum
working voltage (pollution
degree 2, material group I);
DW-16: 2 MOPP (Means of
Patient Protection) per CSA
60601-1:14 and IEC 60601-1
Ed. 3.1, 250 VRMS maximum
working voltage
Certificate number:
40040142
Master contract number:
220991
CQC
Recognized under UL 1577
Certified according to GB
Component Recognition
4943.1-2011
Program
TUV
Certified according to
EN 61010-1:2010 (3rd
Ed) and EN 609501:2006/A2:2013
DW-16: Single protection,
5000 VRMS ;
DBQ-16: Single protection,
3000 VRMS
DW-16: Reinforced
Insulation, Altitude ≤ 5000
m, Tropical Climate, 400
VRMS maximum working
voltage;
DBQ-16: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
5000 VRMS Reinforced
insulation per EN 610101:2010 (3rd Ed) up to
working voltage of 600
VRMS (DW-16) and 300
VRMS (DBQ-16)
5000 VRMS Reinforced
insulation per EN 609501:2006/A2:2013 up to
working voltage of 800
VRMS (DW-16) and 370
VRMS (DBQ-16)
File number: E181974
Certificate number:
CQC15001121716 (DW)
Certificate number:
CQC18001199097 (DBQ)
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DW-16 PACKAGE
IS
Safety input, output, or supply
current (1)
PS
Safety input, output, or total power
TS
Maximum safety temperature (1)
(1)
RθJA = 60.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 1
377
RθJA = 60.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 1
576
RθJA = 60.3 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see Figure 1
754
RθJA = 60.3 °C/W, TJ = 150°C, TA = 25°C, see Figure 3
2073
mW
150
°C
mA
DBQ-16 PACKAGE
IS
Safety input, output, or supply
current (1)
PS
Safety input, output, or total power (1)
TS
Maximum safety temperature (1)
(1)
RθJA = 86.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 2
263
RθJA = 86.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 2
401
RθJA = 86.5 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see Figure 2
525
RθJA = 86.5 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
1445
mW
150
°C
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
8
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –4 mA; see Figure 18
VOL
Low-level output voltage
IOL = 4 mA; see Figure 18
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
VI(HYS)
Input threshold voltage
hysteresis
(1)
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see
Figure 20
CI
Input capacitance (2)
VI = VCC / 2 + 0.4 × sin (2πft), f = 1
MHz, VCC = 5 V
(1)
(2)
VCCO
(1)
MIN
TYP
– 0.4
4.8
MAX
UNIT
V
0.2
0.4
V
0.6 x VCCI
0.7 x VCCI
V
0.3 x VCCI
0.4 x VCCI
V
0.1 × VCCI
0.2 x VCCI
V
10
at INx
–10
85
μA
μA
100
2
kV/μs
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
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6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7760-Q1
Supply current - DC
signal
VI = VCC1 (ISO7760-Q1);
VI = 0 V (ISO7760-Q1 with F suffix)
ICC1
1.6
2.3
ICC2
3
4.9
VI = 0 V (ISO7760-Q1);
VI = VCC1 (ISO7760-Q1 with F suffix)
ICC1
8
11.3
ICC2
3.3
5.3
ICC1
5
6.4
ICC2
3.5
5.6
ICC1
5.2
6.7
ICC2
6.4
9
ICC1
7
9
ICC2
35
44
VI = VCCI (1)(ISO7761-Q1);
VI = 0 V (ISO7761-Q1 with F suffix)
ICC1
1.9
2.7
ICC2
2.9
4.7
VI = 0 V (ISO7761-Q1);
VI = VCCI (ISO7761-Q1 with F suffix)
ICC1
7.3
10.6
ICC2
4.2
6.6
ICC1
4.7
6.4
ICC2
3.8
5.9
ICC1
5.3
7.2
ICC2
6.3
8.8
ICC1
11.5
15
ICC2
30.5
38
VI = VCCI (ISO7762-Q1);
VI = 0 V (ISO7762-Q1 with F suffix)
ICC1
2.1
3.2
ICC2
2.6
4.2
VI = 0 V (ISO7762-Q1);
VI = VCCI (ISO7762-Q1 with F suffix)
ICC1
6.5
9.3
ICC2
5
7.5
ICC1
4.5
6.3
ICC2
4
6.1
ICC1
5.6
7.6
ICC2
6
8.4
ICC1
16.5
21
ICC2
25.7
32
VI = VCCI (ISO7763-Q1);
VI = 0 V (ISO7763-Q1 with F suffix)
ICC1, ICC2
2.4
3.7
VI = 0 V (ISO7763-Q1);
VI = VCCI (ISO7763-Q1 with F suffix)
ICC1, ICC2
5.7
8.6
1 Mbps
ICC1, ICC2
4.2
6.1
10 Mbps
ICC1, ICC2
5.8
8
100 Mbps
ICC1, ICC2
21
26.5
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7761-Q1
Supply current - DC
signal
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7762-Q1
Supply current - DC
signal
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7763-Q1
Supply current - DC
signal
Supply current - AC
signal
(1)
10
All channels switching with square wave
clock input; CL = 15 pF
mA
mA
VCCI = Input-side VCC
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –2 mA; see Figure 18
VOL
Low-level output voltage
IOL = 2 mA; see Figure 18
VCCO
(1)
MIN
TYP
– 0.3
3.2
UNIT
V
0.1
0.3
V
0.6 x VCCI
0.7 x
VCCI
V
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 x VCCI
IIH
High-level input current
VCCIIH = V (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see
Figure 20
(1)
MAX
V
V
10
μA
–10
85
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7760-Q1
Supply current - DC
signal
VI = VCC1 (ISO7760-Q1);
VI = 0 V (ISO7760-Q1 with F suffix)
ICC1
1.6
2.2
ICC2
3
4.8
VI = 0 V (ISO7760-Q1);
VI = VCC1 (ISO7760-Q1 with F suffix)
ICC1
8
11.4
ICC2
3.3
5.3
ICC1
4.9
6.6
ICC2
3.4
5.3
ICC1
5
6.7
ICC2
5.5
7.8
ICC1
6.3
8.2
ICC2
26
33
VI = VCCI (1) (ISO7761-Q1);
VI = 0 V (ISO7761-Q1 with F suffix)
ICC1
1.8
2.7
ICC2
2.9
4.7
VI = 0 V (ISO7761-Q1);
VI = VCCI (ISO7761-Q1 with F suffix)
ICC1
7.2
10.3
ICC2
4.2
6.6
ICC1
4.6
6.5
ICC2
3.7
5.7
ICC1
5.1
7
ICC2
5.5
7.8
ICC1
9.4
12
ICC2
22.8
29
VI = VCCI (ISO7762-Q1);
VI = 0 V (ISO7762-Q1 with F suffix)
ICC1
2.1
3.2
ICC2
2.5
4.2
VI = 0 V (ISO7762-Q1);
VI = VCCI (ISO7762-Q1 with F suffix)
ICC1
6.5
9.4
ICC2
5
7.5
ICC1
4.4
6.2
ICC2
3.9
5.8
ICC1
5.2
7.1
ICC2
5.4
7.5
ICC1
12.9
16.5
ICC2
19.5
25
VI = VCCI (ISO7763-Q1);
VI = 0 V (ISO7763-Q1 with F suffix)
ICC1, ICC2
2.4
3.7
VI = 0 V (ISO7763-Q1);
VI = VCCI (ISO7763-Q1 with F suffix)
ICC1, ICC2
5.7
8.4
1 Mbps
ICC1, ICC2
4.2
6.2
10 Mbps
ICC1, ICC2
5.2
7.5
100 Mbps
ICC1, ICC2
16
20.5
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7761-Q1
Supply current - DC
signal
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7762-Q1
Supply current - DC
signal
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7763-Q1
Supply current - DC
signal
Supply current - AC
signal
(1)
12
All channels switching with square wave
clock input; CL = 15 pF
mA
mA
VCCI = Input-side VCC
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA; see Figure 18
VOL
Low-level output voltage
IOL = 1 mA; see Figure 18
VCCO
(1)
MIN
TYP
– 0.2
2.45
UNIT
V
0.05
0.2
V
0.6 x VCCI
0.7 x
VCCI
V
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 x VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
VI = VCCI or 0 V, VCM = 1200 V;
Common-mode transient immunity
see Figure 20
(1)
MAX
V
V
10
μA
–10
85
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7760-Q1
Supply current - DC
signal
VI = VCC1 (ISO7760-Q1);
VI = 0 V (ISO7760-Q1 with F suffix)
ICC1
1.6
2.2
ICC2
3
4.8
VI = 0 V (ISO7760-Q1);
VI = VCC1 (ISO7760-Q1 with F suffix)
ICC1
8
11.6
ICC2
3.3
5.3
ICC1
4.9
6.8
ICC2
3.4
5.3
ICC1
5
7
ICC2
4.9
7.2
ICC1
6
8
ICC2
20.3
26
VI = VCCI (1) (ISO7761-Q1);
VI = 0 V (ISO7761-Q1 with F suffix)
ICC1
1.8
2.7
ICC2
2.9
4.6
VI = 0 V (ISO7761-Q1);
VI = VCCI (ISO7761-Q1 with F suffix)
ICC1
7.2
10.3
ICC2
4.2
6.5
ICC1
4.6
6.7
ICC2
3.7
5.8
ICC1
4.9
7.1
ICC2
5
7.3
ICC1
8.3
10.7
ICC2
18.1
24
VI = VCCI (ISO7762-Q1);
VI = 0 V (ISO7762-Q1 with F suffix)
ICC1
2.1
3.2
ICC2
2.6
4.1
VI = 0 V (ISO7762-Q1);
VI = VCCI (ISO7762-Q1 with F suffix)
ICC1
6.5
9.6
ICC2
4.9
7.5
ICC1
4.4
6.4
ICC2
3.9
5.8
ICC1
5
7.1
ICC2
5
7.1
ICC1
10.9
14.1
ICC2
15.6
20.1
VI = VCCI (ISO7763-Q1);
VI = 0 V (ISO7763-Q1 with F suffix)
ICC1, ICC2
2.3
3.7
VI = 0 V (ISO7763-Q1);
VI = VCCI (ISO7763-Q1 with F suffix)
ICC1, ICC2
5.7
8.4
1 Mbps
ICC1, ICC2
4.1
6.1
10 Mbps
ICC1, ICC2
4.9
7.1
100 Mbps
ICC1, ICC2
13
17
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7761-Q1
Supply current - DC
signal
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7762-Q1
Supply current - DC
signal
1 Mbps
Supply current - AC
signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
mA
ISO7763-Q1
Supply current - DC
signal
Supply current - AC
signal
(1)
14
All channels switching with square wave
clock input; CL = 15 pF
mA
mA
VCCI = Input-side VCC
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
TEST CONDITIONS
MAX
See Figure 18
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
UNIT
11
16
ns
0.4
4.9
ns
4
ns
4.5
ns
1.1
3.9
ns
1.4
3.9
ns
0.2
0.3
μs
1.3
Same-direction channels
tDO
(3)
TYP
6
See Figure 18
Measured from the time VCC goes
below 1.7 V. See Figure 19
(1)
(2)
MIN
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
TEST CONDITIONS
Propagation delay time
(1)
PWD
Pulse width distortion
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tDO
Measured from the time VCC
Default output delay time from input power loss
goes below 1.7 V. See Figure 19
tie
Time interval error
(1)
(2)
(3)
|tPHL – tPLH|
See Figure 18
MIN
TYP
MAX
6
12
16
ns
0.5
5
ns
4.1
ns
4.5
ns
1
3
ns
1
3
ns
0.2
0.3
μs
Same-direction channels
See Figure 18
216 – 1 PRBS data at 100 Mbps
UNIT
1.3
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tDO
Measured from the time VCC
Default output delay time from input power loss
goes below 1.7 V. See Figure 19
tie
Time interval error
(1)
(2)
(3)
16
7.5
See Figure 18
TYP
MAX
UNIT
13
18.5
ns
0.6
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
0.1
0.3
μs
Same-direction channels
See Figure 18
216 – 1 PRBS data at 100 Mbps
1.3
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SLLSEU7A – NOVEMBER 2018 – REVISED MARCH 2019
6.18 Insulation Characteristics Curves
600
800
Safety Liming Current (mA)
700
Safety Liming Current (mA)
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
600
500
400
300
200
100
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
0
0
50
100
150
Ambient Temperature (qC)
200
0
50
D008
Figure 1. Thermal Derating Curve for Limiting Current per
VDE for DW-16 Package
100
150
Ambient Temperature (qC)
200
D009
Figure 2. Thermal Derating Curve for Limiting Current per
VDE for DBQ-16 Package
2500
1600
Safety Limiting Power (mW)
Safety Limiting Power (mW)
1400
2000
1500
1000
500
1200
1000
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
D010
Figure 3. Thermal Derating Curve for Limiting Power per
VDE for DW-16 Package
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0
50
100
150
Ambient Temperature (qC)
200
D011
Figure 4. Thermal Derating Curve for Limiting Power per
VDE for DBQ-16 Package
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6.19 Typical Characteristics
14
48
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
Supply Current (mA)
40
36
32
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
Supply Current (mA)
44
28
24
20
16
12
8
10
8
6
4
2
4
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
0
CL = 15 pF
TA = 25°C
Figure 5. ISO7760-Q1 Supply Current vs Data Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D002
CL = No Load
Figure 6. ISO7760-Q1 Supply Current vs Data Rate
(With No Load)
14
48
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
40
36
32
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
Supply Current (mA)
44
Supply Current (mA)
25
D001
28
24
20
16
12
8
10
8
6
4
2
4
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
0
CL = 15 pF
TA = 25°C
Figure 7. ISO7761-Q1 Supply Current vs Data Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D013
CL = No Load
Figure 8. ISO7761-Q1 Supply Current vs Data Rate
(With No Load)
14
48
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
40
36
32
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
Supply Current (mA)
44
Supply Current (mA)
25
D012
28
24
20
16
12
8
10
8
6
4
2
4
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
CL = 15 pF
Figure 9. ISO7762-Q1 Supply Current vs Data Rate
(With 15-pF Load)
18
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0
25
D014
TA = 25°C
50
Data Rate (Mbps)
75
100
D015
CL = No Load
Figure 10. ISO7762-Q1 Supply Current vs Data Rate
(With No Load)
Copyright © 2018–2019, Texas Instruments Incorporated
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Typical Characteristics (continued)
14
48
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
40
Supply Current (mA)
36
32
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
Supply Current (mA)
44
28
24
20
16
12
8
10
8
6
4
2
4
0
0
0
25
50
Data Rate (Mbps)
TA = 25°C
75
100
0
CL = 15 pF
75
100
D017
CL = No Load
Figure 12. ISO7763-Q1 Supply Current vs Data Rate
(With No Load)
1
6
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
0.9
5
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
50
Data Rate (Mbps)
TA = 25°C
Figure 11. ISO7763-Q1 Supply Current vs Data Rate
(With 15-pF Load)
4
3
2
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-15
-10
-5
High-Level Output Current (mA)
0
0
14
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
Propagation Delay Time (ns)
2.1
2.05
2
1.95
1.9
1.85
1.8
13
12
11
10
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
1.75
1.7
-60
D004
Figure 14. Low-Level Output Voltage vs Low-Level Output
Current
2.25
2.15
15
TA = 25°C
Figure 13. High-Level Output Voltage vs High-Level Output
Current
2.2
5
10
Low-Level Output Current (mA)
D003
TA = 25°C
Power-Supply UVLO Threshold (V)
25
D016
-30
0
30
60
Free-Air Temperature (qC)
90
9
-55
120
D005
Figure 15. Power Supply Undervoltage Threshold vs FreeAir Temperature
Copyright © 2018–2019, Texas Instruments Incorporated
-10
35
80
Free-Air Temperature (qC)
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
125
D006
Figure 16. Propagation Delay Time vs Free-Air Temperature
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Typical Characteristics (continued)
Peak-to-Peak Output Jitter (ps)
1600
Rising Edge Jitter at 2.5 V
Falling Edge Jitter at 2.5 V
Rising Edge Jitter at 3.3 V
Falling Edge Jitter at 3.3 V
Rising Edge Jitter at 5 V
Falling Edge Jitter at 5 V
1400
1200
1000
800
600
0
25
50
Data Rate (Mbps)
75
100
D007
TA = 25°C
Figure 17. Peak-to-Peak Output Jitter vs Data Rate
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
50
VI
OUT
50%
50%
0V
tPLH
tPHL
CL
See Note B
VO
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate Input Generator signal. It is not needed
in actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 18. Switching Characteristics Test Circuit and Voltage Waveforms
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power-supply ramp rate = 10 mV/ns
Figure 19. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
Isolation Barrier
S1
C = 0.1 µF ±1%
IN
OUT
+
VOH or VOL
CL
See Note A
GNDI
A.
+
VCM ±
±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 20. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO776x-Q1 family of devices uses an ON-OFF keying (OOK) modulation scheme to transmit the digital
data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the
barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The
ISO776x-Q1 family of devices also incorporates advanced circuit techniques to maximize the CMTI performance
and minimize the radiated emissions because of the high-frequency carrier and IO buffer switching. The
conceptual block diagram of a digital capacitive isolator, Figure 21, shows a functional block diagram of a typical
channel. Figure 22 shows a conceptual detail of how the ON-OFF keying scheme works.
8.2 Functional Block Diagram
Transmitter
TX IN
Receiver
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Conceptual Block Diagram of a Digital Capacitive Isolator
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 22. ON-OFF Keying (OOK) Based Modulation Scheme
22
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8.3 Feature Description
Table 1 lists the device features.
Table 1. Device Features
PART NUMBER
ISO7760-Q1
ISO7760-Q1 with F suffix
CHANNEL DIRECTION
MAXIMUM
DATA RATE
DEFAULT
OUTPUT
6 Forward,
0 Reverse
100 Mbps
High
6 Forward,
0 Reverse
100 Mbps
Low
ISO7761-Q1
5 Forward,
1 Reverse
100 Mbps
High
ISO7761-Q1 with F suffix
5 Forward,
1 Reverse
100 Mbps
Low
ISO7762-Q1
4 Forward,
2 Reverse
100 Mbps
High
ISO7762-Q1 with F suffix
4 Forward,
2 Reverse
100 Mbps
Low
ISO7763-Q1
3 Forward,
3 Reverse
100 Mbps
High
ISO7763-Q1 with F suffix
3 Forward,
3 Reverse
100 Mbps
Low
(1)
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
See Safety-Related Certifications for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO776xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO776x-Q1.
Table 2. Function Table (1)
VCCI
VCCO
PU
(1)
(2)
(3)
INPUT
(INx) (2)
OUTPUT
(OUTx)
H
H
L
L
Open
Default
Default mode: When INx is open, the corresponding channel output goes to its
default logic state. Default is High for ISO776x-Q1 and Low for ISO776x-Q1
with F suffix.
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. Default is High for ISO776x-Q1 and
Low for ISO776x-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output assumes
the selected default state.
COMMENTS
Normal Operation:
A channel output assumes the logic state of the input.
PU
PD
PU
X
Default
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
VCCO
~20
OUTx
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Device I/O Schematics
24
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO776x-Q1 family of devices is a high-performance, six-channel digital isolators. The ISO776x-Q1 family of
devices uses single-ended CMOS-logic switching technology. The voltage range is from 2.25 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
Figure 24 shows the isolated serial-peripheral interface (SPI) and controller-area network (CAN) interface
implementation.
VS
10 F
3.3 V
2
Vcc
MBR0520L
1:1.33
3
D2
1
SN6501-Q1
10 F 0.1 F
1
D1
GND
4
3
IN
OUT
5
ISO 3.3V
TPS76333-Q1 10 F
2
EN
GND
2
1 µF
4
MBR0520L
GND
6
22 µF
GND
0.1 µF
0.1 F
0.1 F
2
SPISTEA
44
SPICLKA
SPISIMOA
SPISOMIA
TMS320F28035Q
CANRXA
CANTXA
VSS
3
33
4
36
6
34
5
25
6, 28
31
32
INA
OUTA
OUTB
INB
INC
ISO7762-Q1
15
33
14
34
OUTC
INE
OUTF
INF
36
5
4
CS
CH0
SCLK
28
16 Analog
Inputs
ADS7953-Q1
SDI
SDO
CH15
27
13
AGND
11
REFM
30
1, 22
11
0.1 F
10
IND
OUTD 12
GND1
GND2
8
7
AINP MXO +VBD +VA REFP
BDGND
OUTE
7
26
8
16
VCC2
1
VCC1
0.1 F
VDDIO
VOUT
5
ISO Barrier
29, 57
VIN
REF5025A-Q1
3
4
9
1
VCC
R
RS 8
10
CANH
SN65HVD231Q-Q1
D
CANL
GND
(optional)
CAN Bus
7
6 10
(optional)
Vref 5
SM712
2
4.7 nF /
2 kV
Copyright © 2016, Texas Instruments Incorporated
NOTE: Multiple pins and discrete components omitted for clarity purpose.
Figure 24. Isolated SPI and CAN Interface
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO776x-Q1 family of devices only requires two external bypass capacitors to operate.
0.1 µF
0.1 µF
VCC1
1
16
VCC2
INA
2
15
OUTA
INB
3
14
OUTB
INC
4
13
OUTC
IND
5
12
OUTD
INE
6
11
OUTE
OUTF
7
10
INF
8
9
GND2
GND1
Figure 25. Typical ISO7761-Q1 Circuit Hook-up
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9.2.3 Application Curves
The typical eye diagram of the ISO776x-Q1 family of devices indicates low jitter and a wide open eye at the
maximum data rate of 100 Mbps.
Figure 26. Eye Diagram at 100 Mbps PRBS 216 – 1 Data,
5 V and 25°C
Figure 27. Eye Diagram at 100 Mbps PRBS 216 – 1 Data,
3.3 V and 25°C
Figure 28. Eye Diagram at 100 Mbps PRBS 216 – 1 Data,
2.5 V and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 29 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 30 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS and DBQ-16 package up to 400
VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 29. Test Setup for Insulation Lifetime Measurement
Figure 30. Insulation Lifetime Projection Data
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505. For such applications, detailed power supply design and transformer selection recommendations are
available in the SN6501 Transformer Driver for Isolated Power Supplies data sheet or the SN6505 Low-Noise 1A Transformer Drivers for Isolated Power Supplies data sheet.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 31). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide application report.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 31. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide application report
• Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
• Texas Instruments, Isolation Glossary
• Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
• Texas Instruments, ADS7953-Q1 Automotive 12-Bit, 1MSPS, 16-Channel Single-Ended Micropower, Serial
Interface ADC data sheet
• Texas Instruments, REF50xxA-Q1 Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN65HVD231Q-Q1 3.3-V CAN Transceiver data sheet
• Texas Instruments, TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7760-Q1
Click here
Click here
Click here
Click here
Click here
ISO7761-Q1
Click here
Click here
Click here
Click here
Click here
ISO7762-Q1
Click here
Click here
Click here
Click here
Click here
ISO7763-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
30
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
ISO7760-Q1, ISO7761-Q1
ISO7762-Q1, ISO7763-Q1
www.ti.com
SLLSEU7A – NOVEMBER 2018 – REVISED MARCH 2019
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
31
ISO7760-Q1, ISO7761-Q1
ISO7762-Q1, ISO7763-Q1
SLLSEU7A – NOVEMBER 2018 – REVISED MARCH 2019
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
32
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
ISO7760-Q1, ISO7761-Q1
ISO7762-Q1, ISO7763-Q1
www.ti.com
SLLSEU7A – NOVEMBER 2018 – REVISED MARCH 2019
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
33
ISO7760-Q1, ISO7761-Q1
ISO7762-Q1, ISO7763-Q1
SLLSEU7A – NOVEMBER 2018 – REVISED MARCH 2019
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
34
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7760FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7760FQ
ISO7760FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7760FQ
ISO7760FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7760FQ
ISO7760FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7760FQ
ISO7760QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7760Q
ISO7760QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7760Q
ISO7760QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7760Q
ISO7760QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7760Q
ISO7761FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7761FQ
ISO7761FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7761FQ
ISO7761FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7761FQ
ISO7761FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7761FQ
ISO7761QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7761Q
ISO7761QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7761Q
ISO7761QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7761Q
ISO7761QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7761Q
ISO7762FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7762FQ
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
4-May-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7762FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7762FQ
ISO7762FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7762FQ
ISO7762FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7762FQ
ISO7762QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7762Q
ISO7762QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7762Q
ISO7762QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7762Q
ISO7762QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7762Q
ISO7763FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7763FQ
ISO7763FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7763FQ
ISO7763FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7763FQ
ISO7763FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7763FQ
ISO7763QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7763Q
ISO7763QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7763Q
ISO7763QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7763Q
ISO7763QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7763Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2019
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1 :
• Catalog: ISO7760, ISO7761, ISO7762, ISO7763
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO7760FQDBQRQ1
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7760FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7760QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7760QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7761FQDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7761FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7761QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7761QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7762FQDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7762FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7762QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7762QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7763FQDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7763FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7763QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7763QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7760FQDBQRQ1
SSOP
DBQ
16
2500
350.0
350.0
43.0
ISO7760FQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7760QDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7760QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7761FQDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7761FQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7761QDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7761QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7762FQDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7762FQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7762QDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7762QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7763FQDBQRQ1
SSOP
DBQ
16
2500
350.0
350.0
43.0
ISO7763FQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7763QDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7763QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
.150-.157
[3.81-3.98]
NOTE 4
16X .008-.012
[0.21-0.30]
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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