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Texas Instruments Low-power dual digital isolators (Rev. C) Datasheet
ISO7421E-Q1
SLLSEA5C – MARCH 2012 – REVISED MARCH 2019
Low-power dual digital isolators
1 Features
3 Description
•
•
The ISO7421E-Q1 provides double galvanic isolation
of up to 2.5 KVrms for 1 minute per UL. This digital
isolator has two isolation channels in a bi-directional
configuration. Each isolation channel has a logic input
and output buffer separated by a silicon oxide (SiO2)
insulation barrier. Used in conjunction with isolated
power supplies, these devices prevent noise currents
on a data bus or other circuits from entering the local
ground and interfering with or damaging sensitive
circuitry.
1
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 Qualified with the following results:
– Device temperature grade 1: -40°C to +125°C
ambient operating temperature range
– Device HBM ESD classification level H3A
– Device CDM ESD classification level C4
Propagation delay less than 20 ns
Low power consumption
Safety and regulatory approvals
– 4242 VPK Isolation per VDE, 2.5 kVrms
isolation per UL 1577, CSA approved per IEC
60950-1 and IEC 61010-1 End Equipment
Standards
50 kV/µs Transient immunity typical
Operates from 3.3 V or 5 V Supply and logic
levels
2 Applications
•
Opto-coupler replacement in:
– Servo control interface
– Motor control
– Power supply
– Battery packs
The devices have TTL input thresholds and require
two supply voltages, 3.3 V or 5 V, or any
combination. All inputs are 5-V tolerant when supplied
from a 3.3-V supply.
Note: The ISO7421E-Q1 is specified for signaling
rates up to 50 Mbps. Due to their fast response time,
under most cases, these devices will also transmit
data with much shorter pulse widths. Designers
should add external filtering to remove spurious
signals with input pulse duration < 20 ns if desired.
Simplified Schematic
VCCI
VCCO
Isolation
Capacitor
INx
OUTx
GNDI
GNDO
(1)
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
(2)
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7421E-Q1
SLLSEA5C – MARCH 2012 – REVISED MARCH 2019
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4 Pin Configuration and Functions
16-Pin SSOP
Top View
ISO7421E-Q1
GND1
NC
VCC1
OUTA
INB
NC
GND1
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND2
NC
VCC2
INA
OUTB
NC
NC
GND2
NC = No Internal Connection
Table 1. Pin Functions
PIN
NAME
I/O
ISO7421E-Q1
DESCRIPTION
INA
13
I
Input, channel A
INB
5
–
Input, channel B
GND1
1, 7
–
Ground connection for VCC1
GND2
9, 16
O
Ground connection for VCC2
OUTA
4
O
Output, channel A
OUTB
12
–
Output, channel B
VCC1
14
–
Power supply, VCC1
VCC2
14
-
Power supply, VCC2
NC
2, 6, 8, 10, 11, 15
No Connect Pin
4.1 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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4.1 Device Function Table
INPUT SIDE VCC (VCCI) (1)
OUTPUT SIDE VCC (VCCO) (1)
PU
PU
PD
PU
(1)
INPUT (IN) (1)
OUTPUT (OUT) (1)
H
H
L
L
Open
H
X
H
PU = Powered Up (VCC ≥ 3.15V); PD = Powered Down (VCC ≤ 2.4V); X = Irrelevant; H = High Level; L = Low Level
4.2 Available Options
PRODUCT
RATED TA
MARKED AS
ORDERING NUMBER
ISO7421E-Q1
–40°C to 125°C
ISO7421EQ
ISO7421EQDWRQ1
Absolute Maximum Ratings (1)
5
VALUE
MIN
UNIT
MAX
VCC
Supply voltage (2), VCC1, VCC2
–0.5
6
V
VI
Voltage at IN, OUT
–0.5
VCC +
0.5 (3)
V
IO
Output Current
±15
mA
4
kV
1
kV
150
°C
Human Body Model
AEC-Q100 Classification Level H3A
Charged Device Model
AEC-Q100 Classification Level C4
ESD
Electrostatic
discharge
TJ
Maximum junction temperature
(1)
(2)
(3)
All pins
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V. A strongly driven input signal can weakly power the floating VCC via an internal protection diode
and cause undetermined output.
6 Thermal Information
ISO7421E-Q1
THERMAL METRIC (1)
DW (16 Pins)
θJA
Junction-to-ambient thermal resistance
79.9
θJCtop
Junction-to-case (top) thermal resistance
44.6
θJB
Junction-to-board thermal resistance
51.2
ψJT
Junction-to-top characterization parameter
18.0
ψJB
Junction-to-board characterization parameter
42.2
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
PD
Device power dissipation, Vcc1 = Vcc2 = 5.25 V, TJ = 150°C, CL = 15 pF, Input a 0.5
MHz 50% duty cycle square wave
42
(1)
UNITS
°C/W
mW
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
spacer
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Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC1, VCC2
MIN
TYP
MAX
UNIT
Supply voltage - 3.3V Operation
3.15
3.3
3.45
V
Supply voltage - 5V Operation
4.75
5
5.25
IOH
High-level output current
IOL
Low-level output current
VIH
High-level output voltage
2
VCC
V
VIL
Low-level output voltage
0
0.8
V
TA
Ambient Temperature
-40
125
°C
TJ (1)
Junction temperature
–40
136
°C
1/tui
Signaling rate
0
50
Mbps
tui
Input pulse duration
1
(1)
4
–4
mA
4
mA
µs
To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the Icc Equations section
of this data sheet
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Electrical Characteristics
VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
TEST CONDITIONS
MIN
TYP
IOH = –4 mA; See Figure 1
VCC –0.8
4.6
IOH = –20 µA; See Figure 1
VCC –0.1
5
MAX
UNIT
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
V
400
mV
10
INx at 0 V or VCC
µA
–10
VI = VCC or 0 V; See Figure 3
25
µA
50
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
2.3
3.6
AC Input: CL = 15 pF
2.3
3.6
2.9
4.5
2.9
4.5
4.3
6
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
9
4.3
6
6
9.1
6
9.1
TYP
MAX
mA
Switching Characteristics
VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
See Figure 1
See Figure 1
See Figure 2
MIN
UNIT
9
14
ns
0.3
3.7
ns
4.9
ns
3.6
ns
1
ns
1
ns
6
µs
Also known as pulse skew.
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Electrical Characteristics
VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
TEST CONDITIONS
MIN
TYP
5-V side
VCC –0.8
4.6
3.3-V side
VCC –0.4
3
IOH = –20 µA; See Figure 1
VCC –0.1
VCC
IOH = –4 mA;
See Figure 1
MAX
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
400
–10
VI = VCC or 0 V; See Figure 3
25
V
mV
10
INx at 0 V or VCC
UNIT
µA
µA
40
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
2.3
3.6
AC Input: CL = 15 pF
1.8
2.8
2.9
4.5
2.2
3.2
4.3
6
2.8
4.1
6
9.1
3.8
5.8
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
11
mA
Switching Characteristics
VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
6
See Figure 1
See Figure 1
See Figure 2
MIN
TYP
MAX
10
17
UNIT
ns
0.5
5.6
ns
6.3
ns
4
ns
2
ns
2
ns
6
µs
Also known as pulse skew.
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Electrical Characteristics
VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
TEST CONDITIONS
MIN
TYP
5-V side
VCC –0.8
4.6
3.3-V side
VCC –0.4
3
IOH = –20 µA; See Figure 1
VCC –0.1
VCC
IOH = –4 mA;
See Figure 1
MAX
UNIT
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
V
400
mV
10
INx at 0 V or VCC
µA
–10
VI = VCC or 0 V; See Figure 3
25
µA
40
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
1.8
2.8
AC Input: CL = 15 pF
2.3
3.6
2.2
3.2
2.9
4.5
2.8
4.1
4.3
6
3.8
5.8
6
9.1
TYP
MAX
10
17
ns
0.5
4
ns
8.5
ns
4
ns
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
13
mA
Switching Characteristics
VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
See Figure 1
See Figure 1
See Figure 2
MIN
UNIT
2
ns
2
ns
6
µs
Also known as pulse skew.
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Electrical Characteristics
VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
TEST CONDITIONS
MIN
TYP
IOH = –4 mA; See Figure 1
VCC –0.4
3
IOH = –20 µA; See Figure 1
VCC –0.1
3.3
MAX
UNIT
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
400
V
mV
µA
INx at 0 V or VCC
–10
VI = VCC or 0 V; See Figure 3
25
µA
40
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
1.8
2.8
AC Input: CL = 15 pF
1.8
2.8
2.2
3.2
2.2
3.2
2.8
4.1
2.8
4.1
3.8
5.8
3.8
5.8
TYP
MAX
12
20
ns
1
5
ns
6.8
ns
5.5
ns
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
15
mA
Switching Characteristics
VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
8
See Figure 1
See Figure 1
See Figure 2
MIN
2
UNIT
ns
2
ns
6
µs
Also known as pulse skew.
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Isolation Barrier
16 Parameter Measurement Information
IN
Input
Generator
50 W
VI
(1)
VCCI
VI
OUT
1.4 V
1.4 V
0V
VO
CL
tPLH
(2)
tPHL
90%
10%
50%
VO
50%
VOH
VOL
tr
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤
3ns, tf ≤ 3ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCCI
VCCI
A.
Isolation Barrier
IN = 0 V
VI
2.7 V
0V
OUT
tfs
VO
VOH
CL
50%
VO
(1)
Fail-Safe HIGH
VOL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
S1
IN
C = 0.1 μ F ±1%
Isolation Barrier
VCCI
VCCO
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
(1)
GNDI
GNDO
VOH or VOL
–
+ VCM –
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
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17 Device Information
17.1 Package Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
L(I01)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal to terminal distance through air
7.6
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal to terminal distance across the
package surface
7.6
mm
CTI
Tracking resistance (Comparative Tracking
DIN EN 60112 (VDE 0303-11)
Index)
≥400
V
Minimum internal gap (Internal Clearance)
Distance through the insulation
0.014
mm
RIO
Isolation resistance, input to output (1)
Input to output, VIO = 500 V, all pins on each side
of the barrier tied together creating a two-terminal
device
CIO
Barrier capacitance input to output (1)
CI
Input capacitance to ground (2)
(1)
(2)
>1012
Ω
VIO = 0.4 sin(2πft), f = 1 MHz
2
pF
VI = VCC/2 + 0.4 sin(2πft), f = 1 MHz, VCC = 5 V
2
pF
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
empty para for space above the NOTE
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed circuit board do not reduce this distance
Creepage and clearance on a printed circuit board become equal according to the
measurement techniques shown in the Isolation Glossary. Techniques such as inserting
grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
17.2 IEC 60664-1 Ratings Table
PARAMETER
Basic Isolation Group
Installation Classification
10
TEST CONDITIONS
Material Group
SPECIFICATION
II
Rated mains voltages <= 150 Vrms
I - IV
Rated mains voltages <= 300 Vrms
I - IV
Rated mains voltages <= 400 Vrms
I - III
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17.3 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
SPECIFICATION
UNIT
1414
Vpeak
Maximum working insulation voltage
Input to output test voltage
VIOTM
Transient overvoltage
VISO
Isolation voltage per UL
RS
Insulation resistance
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial discharge < 5 pC
2262
After Input/Output Safety Test Subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
1697
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
2651
t = 60 sec (qualification)
4242
VTEST = VISO, t = 60 sec (qualification)
2500
VTEST = 1.2 x VISO, t = 1 sec (100% production)
3000
VTEST = 500 V at TS = 150°C
>109
Pollution degree
Vpeak
Vpeak
Vrms
Ω
2
17.4 Regulatory Information
VDE
CSA
UL
Certified according to DIN VDE V
0884-11:2017-01
Approved according to IEC 60950-1 and IEC
61010-1
Recognized under UL 1577 Component
Recognition Program
Certificate Number: 40047657
Master Contract Number: 220991
File Number: E181974
17.5 IEC Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
Is
Safety input, output, or supply current
Ts
Maximum Case Temperature
TEST CONDITIONS
MIN
TYP
MAX
θJA =212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
112
θJA =212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
171
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed on a High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
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Safety Limiting Current - mA
500
VCC1 and VCC2 at 3.45 V
400
300
VCC1 and VCC2 at 5.25 V
200
100
0
0
50
100
150
200
250
Case Temperature - °C
Figure 4. DW-16 Theta-JC Thermal Derating Curve per IEC 60747-5-2
GND1
NC
0.1? F
2 mm max. from VCC1
GND2
1
2
3
4
5
6
7
8
VCC1
OUTA
INB
NC
GND1
NC
16
15
14
13
12
11
10
9
NC
0.1? F
2 mm max. from VCC2
VCC2
INA
OUTB
NC
NC
GND2
ISO7421E-Q1
Figure 5. Typical ISO7421E-Q1 Application Circuit
17.6 Equivalent Input And Output Schematic Diagrams
Input
VCCI
VCCI
VCCI
Output
VCCO
1M
8
500
IN
OUT
13
Figure 6. I/O Schematic
12
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18 Typical Characteristics
2.62
VIT+, 5 V
1.5
Fail-Safe Voltage Threshold − V
Input Voltage Switching Threshold − V
1.6
1.4
VIT+, 3.3 V
1.3
1.2
1.1
VIT−, 5 V
1.0
VIT−, 3.3 V
0.9
0.8
−55
−35
−15
5
25
45
65
85
105
TA − Free-Air Temperature − °C
2.61
2.59
2.58
2.57
2.56
2.55
FS−
2.54
2.53
2.52
−55
125
−35
−15
5
25
45
65
85
105
125
TA − Free-Air Temperature − °C
G005
Figure 7. Input Voltage Switching Threshold Vs Free-air
Temperature
G006
Figure 8. Fail-safe Voltage Threshold Vs Free-air
Temperature
0
80
IOL − Low-Level Output Current − mA
IOH − High-Level Output Current − mA
FS+
2.60
TA = 25°C
−10
−20
−30
−40
VCC1, VCC2 at 3.3 V
−50
−60
−70
VCC1, VCC2 at 5 V
−80
−90
TA = 25°C
70
60
VCC1, VCC2 at 5 V
50
40
VCC1, VCC2 at 3.3 V
30
20
10
0
0
1
2
3
4
5
VOH − High-Level Output Voltage − V
6
0
2
3
4
5
VOL − Low-Level Output Voltage − V
G007
Figure 9. High-level Output Current Vs High-level Output
Voltage
1
6
G008
Figure 10. Low-level Output Current Vs Low-level Output
Voltage
Submit Documentation Feedback
Copyright © 2012–2019, Texas Instruments Incorporated
Product Folder Links: ISO7421E-Q1
13
ISO7421E-Q1
SLLSEA5C – MARCH 2012 – REVISED MARCH 2019
www.ti.com
19 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2012) to Revision C
Page
•
Deleted FEATURES bullet "Wide Ambient Temperature: –40°C to 125°C" since it was a duplicate entry. .......................... 1
•
Changed FEATURES bullet From: "4 kV peak Maximum Isolation, 2.5 kVrms per UL 1577, IEC/VDE and CSA
Approved, IEC 60950-1, IEC 61010-1 End Equipment Standards Approved. All Approvals Pending." To: "4242 VPK
Isolation per VDE, 2.5 kVrms Isolation per UL 1577, CSA Approved per IEC 60950-1 and IEC 61010-1 End
Equipment Standards" ............................................................................................................................................................ 1
•
Changed From:"The ISO7421E-Q1 provides double galvanic isolation..." To:"The ISO7421E-Q1 provides galvanic
isolation..." in Description section. .......................................................................................................................................... 1
•
Added Simplified Schematic of the device ............................................................................................................................ 1
•
Changed column titles From:"INPUT SIDE (VCC)" To:"INPUT SIDE VCC (VCCI)" and From:"OUTPUT SIDE (VCC)"
To:"OUTPUT SIDE VCC (VCCO)" in Device Function Table..................................................................................................... 3
•
Changed MAX VALUE for VI From: "6 V" To: "VCC + 0.5 V" ................................................................................................. 3
•
Added : "Maximum voltage must not exceed 6 V. A strongly driven input signal can weakly power the floating VCC
via an internal protection diode and cause undetermined output." ........................................................................................ 3
•
Deleted Supply Current parameters with VCC1 and VCC2 at 5 V ± 5% for ISO7420x in Electrical Characteristics table
since ISO7420x is not included in the data sheet. ................................................................................................................ 5
•
Deleted Supply Current parameters with VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5% for ISO7420x in Electrical
Characteristics table since ISO7420x is not included in the data sheet. ............................................................................... 6
•
Deleted Supply Current parameters with VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5% for ISO7420x in Electrical
Characteristics table since ISO7420x is not included in the data sheet. ............................................................................... 7
•
Deleted Supply Current parameters with VCC1 and VCC2 at 3.3 V ± 5% for ISO7420x in Electrical Characteristics
table since ISO7420x is not included in the data sheet. ....................................................................................................... 8
•
Changed VCC1 to VCCI and Vcc/2 to 50% in Figure 1 ............................................................................................................ 9
•
Changed Vcc1 to VCCI and IN From:"0V or VCC1" To:"0 V" in Figure 2 ................................................................................. 9
•
Corrected 'Ground' symbols on both sides of the Isolation Barrier in Figure 3 ..................................................................... 9
•
Changed MIN specification for Clearance or L(I01) From: "8.34 mm" To:"7.6 mm" in Package Characteristics table. ...... 10
•
Changed MIN specification for Creepage or L(I02) From: "8.1 mm" To:"7.6 mm" in Package Characteristics table. ........ 10
•
Changed CTI TEST CONDITIONS From: " DIN IEC 60112 / VDE 0303 Part 1" To: "DIN EN 60112 (VDE 0303-11)" ...... 10
•
Added "VTEST = 1.2 x VISO" to VISO parameter TEST CONDITIONS in Insulation Characteristics table ............................. 11
•
Changed VDE standard name From: "IEC 60747-5-2" To:"DIN VDE V 0884-11:2017-01" and document reference
From:"File Number: Pending" To:"Certificate Number: 40047657" respectively in Regulatory Information table................ 11
•
Changed CSA standard reference From:"Approved under CSA Component Acceptance Notice" To:"Approved
according to IEC 60950-1 and IEC 61010-1" and document reference From: "File Number: pending" To:"Master
Contract Number: 220991" respectively in Regulatory Information table............................................................................. 11
•
Changed UL standard reference From:"1577" To:"UL 1577" in Regulatory Information table. ........................................... 11
•
Changed ground symbol of 'Output' to differentiate it from 'Input' in Figure 6 .................................................................... 12
Changes from Revision A (March 2012) to Revision B
Page
•
Changed signaling rate info from 1 to 50 Mbps. .................................................................................................................... 1
•
Changed Signaling rate max value from 1 to 50 Mbps, centered 0 in the min column. ........................................................ 4
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 8.5 max
value to 9.1. ............................................................................................................................................................................ 5
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 8.5 max
value to 9.1 and changed 5.5 max value to 5.8. .................................................................................................................... 6
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 5.5 max
value to 5.8 and changed 8.5 max value to 9.1. .................................................................................................................... 7
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 5.5 max
14
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Copyright © 2012–2019, Texas Instruments Incorporated
Product Folder Links: ISO7421E-Q1
ISO7421E-Q1
www.ti.com
SLLSEA5C – MARCH 2012 – REVISED MARCH 2019
value to 5.8. ............................................................................................................................................................................ 8
Submit Documentation Feedback
Copyright © 2012–2019, Texas Instruments Incorporated
Product Folder Links: ISO7421E-Q1
15
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
ISO7421EQDWRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
DW
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
ISO7421EQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7421E-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2019
• Catalog: ISO7421E
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO7421EQDWRQ1
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7421EQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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