Texas Instruments | AMC1302 Precision, Reinforced Isolated Amplifier With High CMTI, Input Voltage Range of ±50 mV, and High Bandwidth of 280 kHz (Rev. B) | Datasheet | Texas Instruments AMC1302 Precision, Reinforced Isolated Amplifier With High CMTI, Input Voltage Range of ±50 mV, and High Bandwidth of 280 kHz (Rev. B) Datasheet

Texas Instruments AMC1302 Precision, Reinforced Isolated Amplifier With High CMTI, Input Voltage Range of ±50 mV, and High Bandwidth of 280 kHz (Rev. B) Datasheet
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AMC1302
SBAS812C – JUNE 2018 – REVISED JANUARY 2020
AMC1302 Precision, Reinforced Isolated Amplifier With High CMTI,
Input Voltage Range of ±50 mV, and High Bandwidth of 280 kHz
1 Features
3 Description
•
The AMC1302 is a precision isolated amplifier with a
capacitive isolation barrier that has high immunity to
magnetic interference. This barrier provides
reinforced isolation of 5 kVRMS (maximum) with a very
long lifetime and low power dissipation. When used
with isolated power supplies, this device isolates
components that operate on different common-mode
voltage levels. Furthermore, the AMC1302 also
protects lower-voltage devices from damage.
1
•
•
•
•
•
•
•
•
±50-mV input voltage range for low dissipation,
shunt-resistor-based current measurement
Fixed gain with low drift: 41 ± 0.3%, ±50 ppm/°C
Low input offset and drift: ±100 µV, ±0.8 µV/°C
Low nonlinearity and drift: ±0.03%, ±1 ppm/°C
Very low isolated high-side power dissipation
when operated from a 3.3-V supply
System-level diagnostic features
Safety-related certifications:
– 7071-VPK reinforced isolation per
DIN VDE V 0884-11: 2017-01
– 5000-VRMS isolation for 1 minute per UL1577
Extended industrial temperature range:
–55°C to +125°C
High CMTI: 80 kV/µs (typ), 55 kV/µs (min)
2 Applications
Shunt-resistor-based current sensing in:
• Motor drives
• Avionics
• Power delivery
• Industrial transport
• Appliances
• Grid infrastructure
The input of the AMC1302 is optimized for direct
connection to shunt resistors or other low voltagelevel signal sources. The ±50-mV input voltage range
allows significant reduction of the power dissipation
through the shunt. Additionally, the low high-side
supply current and voltage of the AMC1302 allow use
of low-cost isolated power-supply solutions. The
performance of the device supports accurate current
control resulting in system-level power savings and in
low torque ripple that is particularly important in motor
control applications. The integrated input commonmode overvoltage and missing high-side supply
voltage detection features of the AMC1302 simplify
system-level diagnostics.
Device Information(1)
PART NUMBER
AMC1302
PACKAGE
SOIC (8)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Floating
Power Supply
HV+
AMC1302
VDD1
GND1
RSHUNT
RFLT
INN
to Load
RFLT
CFLT
INP
VDD2
Reinforced Isolation
3.3 V or 5.0 V
3.3 V, or 5.0 V
GND2
OUTP
OUTN
ADS7263
14-Bit ADC
Diagnostics
HV-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1302
SBAS812C – JUNE 2018 – REVISED JANUARY 2020
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics........................................... 7
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
8.3 What to Do and What Not to Do ............................. 24
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2018) to Revision C
Page
•
Changed VDE certificate in Safety-related certifications Features bullet from DIN V VDE V 0884-11 (VDE V 088411) to DIN VDE V 0884-11 ..................................................................................................................................................... 1
•
Changed VDE certificate format from DIN V VDE V 0884-11 (VDE V 0884-11) to DIN VDE V 0884-11 in DIN VDE V
0884-11: 2017-01 header row of Insulation Specifications table ........................................................................................... 6
•
Changed VDE certificate details in Safety-Related Certifications table ................................................................................. 7
Changes from Revision A (September 2018) to Revision B
Page
•
Changed High CMTI specification from 140 kV/µs (typ), 70 kV/µs (min) to 80 kV/µs (typ), 55 kV/µs (min) in Features
section .................................................................................................................................................................................... 1
•
Changed PSRR specifications in Electrical Characteristics table ......................................................................................... 8
•
Changed footnote 3 in PSRR parameter from output referred to input referred .................................................................... 8
•
Changed Power-Supply Rejection Ratio vs Ripple Frequency figure .................................................................................. 16
•
Changed CMTI value in Table 1 from 140 kV/µs (typical) to 80 kV/µs (typical)................................................................... 23
Changes from Original (June 2018) to Revision A
•
2
Page
Changed device status from Advance Information to Production Data ................................................................................. 1
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SBAS812C – JUNE 2018 – REVISED JANUARY 2020
5 Pin Configuration and Functions
DWV Package
8-Pin SOIC
Top View
VDD1
1
8
VDD2
INP
2
7
OUTP
INN
3
6
OUTN
GND1
4
5
GND2
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
VDD1
—
2
INP
I
Noninverting analog input
3
INN
I
Inverting analog input
4
GND1
—
High-side analog ground
5
GND2
—
Low-side analog ground
6
OUTN
O
Inverting analog output
7
OUTP
O
Noninverting analog output
8
VDD2
—
Low-side power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for power-supply decoupling recommendations.
High-side power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see
(1)
Power-supply voltage
MIN
MAX
VDD1 to GND1
–0.3
6.5
VDD2 to GND2
–0.3
6.5
GND1 – 6
VDD1 + 0.5
V
GND2 – 0.5
VDD2 + 0.5
V
10
mA
Input voltage
INP, INN
Output voltage
OUTP, OUTN
Input current
Continuous, any pin except power-supply pins
Temperature
(1)
–10
Junction, TJ
UNIT
V
150
Storage, Tstg
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
High-side power supply
VDD1 to GND1
3.0
5
5.5
V
Low-side power supply
VDD2 to GND2
3.0
3.3
5.5
V
ANALOG INPUTS
VClipping Differential input voltage before clipping output
VIN = VINP – VINN
VFSR
VIN = VINP – VINN
Specified linear differential input full-scale
Absolute common-mode input voltage
VCM
(1)
Operating common-mode input voltage
±64
–50
mV
50
mV
(VINP + VINN) / 2 to GND1
–2
VDD1
V
(VINP + VINN) / 2 to GND1
–0.032
VDD1 – 2.2
V
–55
125
°C
TEMPERATURE RANGE
TA
(1)
4
Specified ambient temperature
Steady-state voltage supported by the device in case of a system failure. See the specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
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6.4 Thermal Information
AMC1302
THERMAL METRIC (1)
DWV (SOIC)
UNIT
8 PINS
RθJA
85.4
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
26.8
°C/W
RθJB
Junction-to-board thermal resistance
43.5
°C/W
ψJT
Junction-to-top characterization parameter
4.8
°C/W
ψJB
Junction-to-board characterization parameter
41.2
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (high-side supply)
PD2
Maximum power dissipation (low-side supply)
VALUE
VDD1 = VDD2 = 5.5 V
98.45
VDD1 = VDD2 = 3.6 V
56.52
VDD1 = 5.5 V
53.90
VDD1 = 3.6 V
30.60
VDD2 = 5.5 V
44.55
VDD2 = 3.6 V
25.92
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UNIT
mW
mW
mW
5
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SBAS812C – JUNE 2018 – REVISED JANUARY 2020
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest pin-to-pin distance through air
≥ 8.5
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
≥ 8.5
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double insulation
(2 × 0.0105 mm)
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
DIN VDE V 0884-11: 2017-01
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
At AC voltage
2121
VPK
Maximum-rated isolation
working voltage
At AC voltage (sine wave); see Figure 4
1500
VRMS
At DC voltage
2121
VDC
VIOTM
Maximum transient
isolation voltage
VTEST = VIOTM, t = 60 s (qualification test)
7071
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8485
VIOSM
Maximum surge
isolation voltage (3)
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Apparent charge (4)
qpd
CIO
Barrier capacitance,
input to output (5)
RIO
Insulation resistance,
input to output (5)
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1
VPK
VPK
pC
pF
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
Ω
9
VIO = 500 V at TS = 150°C
> 10
Pollution degree
2
Climatic category
55/125/21
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11: 2017-01, DIN EN 62368-1:
2016-05, EN 62368-1: 2014, and IEC 62368-1: 2014
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
Safety input, output,
or supply current
IS
PS
Safety input, output,
or total power (1)
TS
Maximum safety temperature
(1)
MIN
TYP
MAX
RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see Figure 2
266
RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 3.6 V, see Figure 2
406
UNIT
mA
RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C, see Figure 3
1463
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDD1max + IS × VDD2max, where VDD1max is the maximum high-side voltage and VDD2max is the maximum low-side supply
voltage.
6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –50 mV to +50 mV, and INN = GND1 = 0 V; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
VCMov
Common-mode overvoltage
detection level
(VINP + VINN) / 2 to GND1
VDD1 – 2.1
Hysteresis of common-mode
overvoltage detection level
(1)
V
60
VOS
Input offset voltage
TCVOS
Input offset drift (1)
CMRR
Common-mode rejection
ratio
CIN
Single-ended input
capacitance (2)
INN = GND1, fIN = 300 kHz
4
pF
CIND
Differential input
capacitance (2)
fIN = 300 kHz
2
pF
RIN
Single-ended input
resistance (2)
INN = GND1
4.75
kΩ
RIND
Differential input
resistance (2)
4.9
kΩ
IIB
Input bias current
TCIIB
Input bias current drift
IIO
Input offset current
(1)
(2)
initial, at TA = 25°C, VINP = VINN = GND1
mV
–100
±10
100
μV
–0.8
±0.15
0.8
µV/°C
fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max
–100
fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max
INP = INN = GND1; IIB = (IIBP + IIBN) / 2
IIO = IIBP – IIBN
dB
–98
–48.5
–36
–28.5
μA
±1.5
nA/°C
±10
nA
The typical value includes one sigma statistical variation.
See Figure 47.
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –50 mV to +50 mV, and INN = GND1 = 0 V; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
Nominal gain
(1)
EG
Gain error
TCEG
Gain error drift (1)
41
initial, at TA = 25°C
Nonlinearity (1)
–0.3%
±0.05%
–50
±15
50
–0.03%
±0.01%
0.03%
Nonlinearity drift
THD
SNR
±1
ppm/°C
ppm/°C
Total harmonic distortion
VIN = 100 mVPP, fIN = 10 kHz, BW = 100 kHz
–85
dB
Output noise
VINP = VINN = GND1, BW = 100 kHz
260
μVRMS
Signal-to-noise ratio
PSRR
Power-supply rejection
ratio (3)
VCMout
Common-mode output
voltage
VFAILSAFE
Failsafe differential output
voltage
BW
Output bandwidth
ROUT
Output resistance
VIN = 100 mVPP, fIN = 1 kHz, BW = 10 kHz
80
VIN = 100 mVPP, fIN = 10 kHz, BW = 100 kHz
PSRR vs VDD1, at DC
–113
PSRR vs VDD1, 100-mV and 10-kHz ripple
–108
PSRR vs VDD2, at DC
–116
dB
dB
–87
1.39
VCM > VCMov or VDD1 ≤ VDD1UV
220
On OUTP or OUTN
1.44
1.49
V
–2.6
–2.5
V
280
kHz
< 0.2
Output short-circuit current
Common-mode transient
immunity
84
70
PSRR vs VDD2, 100-mV and 10-kHz ripple
CMTI
0.3%
Ω
±14
mA
55
80
kV/µs
1.75
2.15
2.7
3.0 V ≤ VDD1 ≤ 3.6 V
6.2
8.5
4.5 V ≤ VDD1 ≤ 5.5 V
7.2
9.8
3.0 V ≤ VDD2 ≤ 3.6 V
5.3
7.2
4.5 V ≤ VDD2 ≤ 5.5 V
5.9
8.1
|GND1 – GND2| = 1 kV
POWER SUPPLY
VDD1POR
VDD1 power on reset
threshold voltage
IDD1
High-side supply current
IDD2
Low-side supply current
(3)
8
VDD1 falling
V
mA
mA
This parameter is input referred.
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Rise time of OUTP, OUTN
See Figure 1
1.3
µs
tf
Fall time of OUTP, OUTN
See Figure 1
1.3
µs
INP, INN to OUTP, OUTN signal
delay (50% – 10%)
Unfiltered output, see Figure 1
1.0
1.5
µs
INP, INN to OUTP, OUTN signal
delay (50% – 50%)
Unfiltered output, see Figure 1
1.6
2.1
µs
INP, INN to OUTP, OUTN signal
delay (50% – 90%)
Unfiltered output, see Figure 1
2.5
3.0
µs
Analog startup time
VDD1 step to 3.0 V with VDD2 ≥ 3.0 V,
to OUTP, OUTN valid, 0.1% settling
500
tAS
µs
0.05 V
VINP - VINN
50%
0V
50% - 50%
50% - 90%
50% - 10%
VOUTP
50%
10%
90%
VCMout
VOUTN
tr
tf
Figure 1. Rise, Fall, and Delay Time Waveforms
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6.11 Insulation Characteristics Curves
450
1600
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
400
1400
350
1200
PS (mW)
IS (mA)
300
250
200
1000
800
600
150
400
100
200
50
0
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
D001
Figure 2. Thermal Derating Curve for Safety-Limiting
Current per VDE
1.E+11
1.E+10
87.5%
75
TA (°C)
100
125
150
D002
Figure 3. Thermal Derating Curve for Safety-Limiting
Power per VDE
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+9
Time to Fail (s)
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500
1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 4. Reinforced Isolation Capacitor Lifetime Projection
10
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6.12 Typical Characteristics
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
3.8
3.3
3.4
3.25
3.2
VCMov (V)
VCMov (V)
3
2.6
2.2
1.8
3.1
3.05
3
1.4
2.95
1
3
3.25
3.5
3.75
4
4.25 4.5
VDD1 (V)
4.75
5
5.25
2.9
-55 -40 -25 -10
5.5
50
40
40
Devices (%)
50
30
20
80
95 110 125
D004
30
20
0
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
10
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
10
D005
VOS (PV)
20 35 50 65
Temperature (qC)
Figure 6. Common-Mode Overvoltage Detection Level
vs Temperature
D006
VOS (PV)
VDD1 = 3.3 V
VDD1 = 5 V
Figure 7. Input Offset Voltage Histogram
Figure 8. Input Offset Voltage Histogram
100
100
vs VDD1
vs VDD2
75
50
50
25
25
0
0
-25
-25
-50
-50
-75
-75
-100
3
3.25
3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
Device 1
Device 2
Device 3
75
VOS (PV)
VOS (PV)
5
D003
Figure 5. Common-Mode Overvoltage Detection Level
vs High-Side Supply Voltage
Devices (%)
3.15
5.5
-100
-55 -40 -25 -10
D007
Figure 9. Input Offset Voltage vs Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95 110 125
D009
Figure 10. Input Offset Voltage vs Temperature
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Typical Characteristics (continued)
80
70
70
60
60
50
50
D010
TCVOS (PV/qC)
D011
TCVOS (PV/qC)
VDD1 = 3.3 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
0.1
-0.1
-0.2
-0.3
-0.8
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
0.1
-0.1
-0.2
0
-0.3
0
-0.4
10
-0.5
10
-0.6
20
-0.7
20
-0.4
30
-0.5
30
40
-0.6
40
-0.7
Devices (%)
80
-0.8
Devices (%)
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
VDD1 = 5 V
Figure 11. Input Offset Drift Histogram
Figure 12. Input Offset Drift Histogram
-75
0
-80
-20
-85
CMRR (dB)
CMRR (dB)
-40
-60
-80
-90
-95
-100
-105
-100
-110
-120
0.001
0.01
0.1
1
fIN (kHz)
10
100
-115
-55 -40 -25 -10
1000
5
D012
Figure 13. Common-Mode Rejection Ratio
vs Input Frequency
20 35 50 65
Temperature (°C)
80
95 110 125
D013
Figure 14. Common-Mode Rejection Ratio
vs Temperature
60
-27
-29
40
-31
-33
0
IIB (PA)
IIB (PA)
20
-20
-35
-37
-39
-40
-41
-60
-80
-0.5
-43
-45
0
0.5
1
1.5
VCM (V)
2
2.5
3
3.5
3
3.25
D014
Figure 15. Input Bias Current
vs Common-Mode Input Voltage
12
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3.5
3.75
4
4.25 4.5
VDD1 (V)
4.75
5
5.25
5.5
D015
Figure 16. Input Bias Current
vs High-Side Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
50
-27
-29
40
-31
Devices (%)
IIB (PA)
-33
-35
-37
30
20
-39
10
-41
-43
0.3
0.25
0.2
0.15
0.1
0
0.05
-0.1
-0.05
95 110 125
-0.15
80
-0.25
20 35 50 65
Temperature (°C)
-0.2
0
5
-0.3
-45
-55 -40 -25 -10
D017
EG (%)
D016
VDD2 = 3.3 V
Figure 18. Gain Error Histogram
0.3
40
0.2
0.1
30
EG (%)
Devices (%)
Figure 17. Input Bias Current vs Temperature
50
20
0
-0.1
10
-0.2
EG (%)
vs VDD1
vs VDD2
-0.3
0.3
0.25
0.2
0.15
0.1
0
0.05
-0.1
-0.05
-0.15
-0.2
-0.25
-0.3
0
3
3.25
3.5
3.75
4
D018
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D019
VDD2 = 5 V
Figure 19. Gain Error Histogram
Figure 20. Gain Error vs Supply Voltage
40
0.3
35
0.2
30
Devices (%)
EG (%)
0.1
0
25
20
15
-0.1
10
Device 1
Device 2
Device 3
D020
45
40
35
30
25
20
15
10
5
-5
-10
-15
-20
95 110 125
-25
80
-30
20 35 50 65
Temperature (°C)
-35
5
0
-40
-0.3
-55 -40 -25 -10
5
-45
-0.2
TCEG (ppm/qC)
D021
VDD1 = 3.3 V
Figure 21. Gain Error vs Temperature
Figure 22. Gain Error Drift Histogram
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Typical Characteristics (continued)
40
5
35
0
30
-5
Normalized Gain (dB)
Devices (%)
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
25
20
15
10
-10
-15
-20
-25
-30
5
-35
-40
0.01
40
35
30
25
20
15
5
10
-5
-10
-15
-20
-25
-30
-35
-40
-45
0
0.1
1
D022
TCEG (ppm/qC)
10
100
1000
fIN (kHz)
D023
VDD1 = 5 V
Figure 23. Gain Error Drift Histogram
Figure 24. Normalized Gain vs Input Frequency
0°
5
-45°
4.5
VOUTN
VOUTP
4
-90°
-135°
VOUT (V)
Output Phase
3.5
-180°
-225°
3
2.5
2
1.5
-270°
1
-315°
0.5
-360°
0.01
0.1
1
10
100
0
-70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70
Differential Input Voltage (mV)
D025
1000
fIN (kHz)
D024
Figure 25. Output Phase vs Input Frequency
Figure 26. Output Voltage vs Input Voltage
0.03
0.02
0.02
0.01
0.01
Nonlinearity (%)
Nonlinearity (%)
0.03
0
-0.01
-0.02
-0.03
-50
vs VDD1
vs VDD2
0
-0.01
-0.02
-0.03
-40
-30
-20 -10
0
10
20
30
Differential Input Voltage (mV)
40
50
3
3.25
D026
Figure 27. Nonlinearity vs Input Voltage
14
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3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D027
Figure 28. Nonlinearity vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
-70
0.02
-75
0.01
-80
THD (dB)
Nonlinearity (%)
0.03
0
vs VDD1
vs VDD2
-85
-90
-0.01
Device 1
Device 2
Device 3
-0.02
-0.03
-55 -40 -25 -10
-95
-100
5
20 35 50 65
Temperature (°C)
80
95 110 125
3
3.25
3.5
3.75
4
D028
Figure 29. Nonlinearity vs Temperature
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D029
Figure 30. Total Harmonic Distortion vs Supply Voltage
-70
10
Noise Density (PV/—Hz)
-75
THD (dB)
-80
-85
-90
1
Device 1
Device 2
Device 3
-95
-100
-55 -40 -25 -10
5
20 35 50 65
Temperature (°C)
80
0.1
0.1
95 110 125
Figure 31. Total Harmonic Distortion vs Temperature
10
Frequency (kHz)
100
1000
D031
Figure 32. Output Noise Density vs Frequency
75
75
70
74
65
73
vs VDD1
vs VDD2
72
SNR (dB)
60
SNR (dB)
1
D030
55
50
45
71
70
69
68
40
67
35
66
30
65
0
5
10
15
20 25 30 35
|VINP - VINN| (mV)
40
45
50
55
3
3.25
D032
Figure 33. Signal-to-Noise Ratio vs Input Voltage
3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D033
Figure 34. Signal-to-Noise Ratio vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
20
75
74
vs VDD2
vs VDD1
0
73
-20
PSRR (dB)
SNR (dB)
72
71
70
69
68
-40
-60
-80
67
Device 1
Device 2
Device 3
66
65
-55 -40 -25 -10
5
20 35 50 65
Temperature (°C)
80
-100
-120
0.001
95 110 125
0.01
D034
1.49
1.49
1.48
1.48
1.47
1.47
1.46
1.46
1.45
1.45
1.44
1.43
D035
1.43
1.42
1.41
1.41
1.4
1.4
3
3.25
3.5
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
1.39
-55 -40 -25 -10
5.5
310
310
300
300
290
290
BW (kHz)
320
280
270
250
250
240
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
95 110 125
D037
270
260
3.5
80
280
260
3.25
20 35 50 65
Temperature (°C)
Figure 38. Output Common-Mode Voltage vs Temperature
320
3
5
D036
Figure 37. Output Common-Mode Voltage
vs Low-Side Supply Voltage
BW (kHz)
1000
1.44
1.42
1.39
5.5
240
-55 -40 -25 -10
D038
Figure 39. Output Bandwidth vs Low-Side Supply Voltage
16
100
Figure 36. Power-Supply Rejection Ratio
vs Ripple Frequency
VCMout (V)
VCMout (V)
Figure 35. Signal-to-Noise Ratio vs Temperature
0.1
1
10
Ripple Frequency (kHz)
5
20 35 50 65
Temperature (°C)
80
95 110 125
D039
Figure 40. Output Bandwidth vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VINP = –50 mV to 50 mV, VINN = GND1, and fIN = 10 kHz (unless otherwise
noted)
8.5
8
8
7.5
7.5
7
7
6.5
6.5
IDDx (mA)
IDDx (mA)
8.5
6
5.5
6
5.5
5
5
4.5
4.5
IDD1 vs VDD1
IDD2 vs VDD2
4
4
3.5
-55 -40 -25 -10
3.5
3
3.25
3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
3.4
3.4
3
3
2.6
2.6
tr/tf (Ps)
tr / tf (Ps)
3.8
2.2
1.8
1
1
0.6
0.6
0.2
0.2
-55 -40 -25 -10
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
95 110 125
D041
1.8
1.4
3.5
80
2.2
1.4
3.25
20 35 50 65
Temperature (°C)
Figure 42. Supply Current vs Temperature
3.8
3
5
D040
Figure 41. Supply Current vs Supply Voltage
5.5
5
D042
Figure 43. Output Rise and Fall Time
vs Low-Side Supply Voltage
20 35 50 65
Temperature (°C)
80
95 110 125
D043
Figure 44. Output Rise and Fall Time vs Temperature
3.8
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
2.6
2.2
1.8
1.4
1
1
0.6
0.6
0.2
3
3.25
3.5
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
50% - 90%
50% - 50%
50% - 10%
3.4
Signal Delay (Ps)
3
Signal Delay (Ps)
IDD1 at VDD1 = 5 V
IDD1 at VDD1 = 3.3 V
IDD2 at VDD2 = 5 V
IDD2 at VDD2 = 3.3 V
5.5
0.2
-55 -40 -25 -10
D044
Figure 45. VIN to VOUT Signal Delay
vs Low-Side Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95 110 125
D045
Figure 46. VIN to VOUT Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1302 is a fully-differential, precision, isolated amplifier. The input stage of the device consists of a fullydifferential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator uses the internal
voltage reference and clock generator to convert the analog input signal to a digital bitstream. The drivers (called
TX in the Functional Block Diagram) transfer the output of the modulator across the isolation barrier that
separates the high-side and low-side voltage domains. The received bitstream and clock are synchronized and
processed by a fourth-order analog filter on the low-side and presented as a differential output of the device.
The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as described
in ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the AMC1302 (see also the
Isolation Channel Signal Transmission section for more details) and the isolation barrier characteristics result in
high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
VDD2
VDD1
VDD1
Detection
Reinforced
Isolation
Barrier
Bandgap
Reference
Bandgap
Reference
INP
OUTP
û -Modulator
Data
TX
RX
Retiming and
4th order
active
low-pass filter
OUTN
INN
VCM
Diagnostic
CLK
RX
TX
Oscillator
AMC1302
GND1
18
GND2
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7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC1302 feeds a second-order, switched-capacitor, feed-forward ΔΣ
modulator. The modulator converts the analog signal into a bitstream that is transferred over the isolation barrier,
as described in the Isolation Channel Signal Transmission section.
Figure 47 depicts the equivalent input structure of the AMC1302 with the relevant components. The total gain of
the device results from a combination of the gain of the fully-differential input amplifier and the gain of the active
output filter.
INP
2.5 NŸ
4 pF
VDD1
GND1
VDD1
100 NŸ
GND1
16 pF
4 pF
to VCM
Overvoltage
monitor
50 NŸ
VCMop = 2 V
100 NŸ
VDD1
2.5 k
50 k
INN
Figure 47. Equivalent Analog Input Circuit
There are two restrictions on the analog input signals (INP and INN). First, if the input voltage exceeds the range
GND1 – 6 V to VDD1 + 0.5 V, the input current must be limited to 10 mA because the device input electrostatic
discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only
when the analog input voltage remains within the specified linear full-scale range (VFSR) and within the specified
common-mode input voltage range (VCM); see the Recommended Operating Conditions table for detailed
specifications.
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Feature Description (continued)
7.3.2 Isolation Channel Signal Transmission
The AMC1302 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream
across the SiO2-based isolation barrier. As shown in Figure 48, the transmitter modulates the bitstream at TX IN
with an internally-generated, high-frequency carrier across the isolation barrier to represent a digital one and
does not send a signal to represent the digital zero. The nominal frequency of the carrier used inside the
AMC1302 is 480 MHz.
The receiver demodulates the signal after advanced signal conditioning and produces the output. The AMC1302
also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions caused by the high-frequency carrier and IO buffer switching.
Transmitter
Receiver
OOK
Modulation
TX IN
TX Signal
Conditioning
SiO2-Based
Capacitive
Reinforced
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Oscillator
Figure 48. Block Diagram of an Isolation Channel
Figure 49 shows the concept of the OOK scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
Figure 49. OOK-Based Modulation Scheme
20
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Feature Description (continued)
7.3.3 Fail-Safe Output
The AMC1302 offers a fail-safe output that simplifies diagnostics on a system level. The fail-safe output is active
in two cases:
• When the high-side supply VDD1 of the AMC1302 is missing, or
• When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the minimum common-mode
overvoltage detection level VCMov of VDD1 – 2 V
Figure 50 and Figure 51 show the fail-safe output of the AMC1302 as a negative differential output voltage value
that does not occur under normal device operation. Use the VFAILSAFE voltage specified in the Electrical
Characteristics table as a reference value for the fail-safe detection on a system level.
Figure 50. Typical Negative Clipping Output of the
AMC1302
Figure 51. Typical Failsafe Output of the AMC1302
7.4 Device Functional Modes
The AMC1302 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table. The device does not require any specific power-supply sequence.
Consider the analog startup time tAS as defined in the Switching Characteristics table when the high-side power
supply VDD1 powers up with the low-side power supply VDD2 already operating in the specified range.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low input voltage range, very low nonlinearity, and temperature drift make the AMC1302 a high-performance
solution for industrial applications where low-power dissipation, shunt-based current sensing with high commonmode voltage levels is required.
8.2 Typical Application
Isolated amplifiers are widely used in frequency inverters that are critical parts of industrial motor drives,
photovoltaic inverters, uninterruptible power supplies, and other industrial applications. The input structure of the
AMC1302 is optimized for use with very low-value shunt resistors in current-sensing applications.
Figure 52 shows a typical operation of the AMC1302 for current sensing in a frequency inverter application.
Phase current measurement is accomplished through the shunt resistors, RSHUNT (in this case, a two-pin shunt).
The differential input and the high common-mode transient immunity of the AMC1302 ensure reliable and
accurate operation even in high-noise environments (such as the power stage of the motor drive). The highimpedance input and wide input voltage range make the AMC1311 suitable for DC bus voltage sensing.
+VBUS
Motor
RSHUNT
L1
RSHUNT
L2
RSHUNT
L3
3.3 V
RFLT
CFLT
RFLT
AMC1302
VDD1
3.3 V
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
Analog
Filter
to ADC
-VBUS
3.3 V
RFLT
CFLT
RFLT
3.3 V
RFLT
CFLT
RFLT
3.3 V
RFLT
CFLT
AMC1311B
VDD1
VDD1
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
3.3 V
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
Analog
Filter
to ADC
3.3 V
Analog
Filter
to ADC
3.3 V
VDD2
VIN
VOUTP
SHTDN
VOUTN
GND1
AMC1302
AMC1302
VDD1
Analog
Filter
to ADC
GND2
Figure 52. Using the AMC1302 for Current Sensing in Frequency Inverters
22
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 lists the parameters for this typical application.
Table 1. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
Voltage drop across the shunt for a linear response
±50 mV (maximum)
Signal delay (90% settling)
3 µs (maximum)
High common-mode transient immunity (CMTI)
80 kV/µs (typical)
8.2.2 Detailed Design Procedure
The high-side power supply (VDD1) for the AMC1302 is derived from the power supply of the upper gate driver.
Further details are provided in the Power Supply Recommendations section.
The floating ground reference (GND1) is derived from one of the ends of the shunt resistor that is connected to
the negative input of the AMC1302 (INN). If a four-pin shunt is used, the inputs of the AMC1302 device are
connected to the inner leads and GND1 is connected to one of the outer shunt leads.
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions to choose the proper value of the shunt resistor RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range: VSHUNT ≤ ± 50 mV
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: VSHUNT ≤ VClipping
For systems using single-ended input ADCs, Figure 53 shows an example of a TLV6001-based signal
conversion and filter circuit as used on the AMC1302EVM, where VCMADC is the common-mode input voltage of
the ADC. Tailor the bandwidth of this filter stage to the bandwidth requirement of the system and use NP0-type
capacitors for best performance.
AMC1302
VCMADC
VDD1
VDD2
INP
OUTP
+
INN
OUTN
±
GND1
GND2
TLV6001
To ADC
GND2
Figure 53. Connecting the AMC1302 Output to Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see 18Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data Acquisition
Block (DAQ) Optimized for Lowest Power, available for download at www.ti.com.
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8.2.3 Application Curves
In frequency inverter applications, the power switches must be protected in case of an overcurrent condition. To
allow for fast powering off of the system, a low delay caused by the isolated amplifier is required. Figure 54
shows the typical full-scale step response of the AMC1302. Consider the delay of the required window
comparator and the MCU to calculate the overall response time of the system.
VOUTN
VIN
VOUTP
Figure 54. Step Response of the AMC1302
The high linearity and low temperature drift of the offset and gain errors of the AMC1302 (see the Typical
Characteristics section) allows design of motor drives with low torque ripple.
0.03
Nonlinearity (%)
0.02
0.01
0
-0.01
-0.02
-0.03
-50
-40
-30
-20 -10
0
10
20
30
Differential Input Voltage (mV)
40
50
D026
Figure 55. Typical Nonlinearity of the AMC1302
8.3 What to Do and What Not to Do
Do not leave the inputs of the AMC1302 unconnected (floating) when the device is powered up. If both device
inputs are left floating, the input bias current drives these inputs to the output common-mode of the analog frontend of approximately 2 V. If the high-side supply voltage VDD1 is below 4 V, the internal common-mode
overvoltage detector turns on and the output functions as described in the Fail-Safe Output section, which may
lead to an undesired reaction on the system level.
24
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9 Power Supply Recommendations
In a typical frequency inverter application, the high-side power supply (VDD1) for the device is derived from the
floating power supply of the upper gate driver. For lowest system-level cost, a Zener diode can be used to limit
the voltage to 5 V or 3.3 V ± 10%. Alternatively, a low-cost low-dropout (LDO) regulator (for example, the LM317N) may be used to minimize noise on the power supply. TI recommends a low-ESR decoupling capacitor of
0.1 µF to filter this power-supply path. Place this capacitor (C1 in Figure 56) as close as possible to the VDD1
pin of the AMC1302 for best performance. Use an additional 2.2-µF decoupling capacitor (C2) for filtering lowerfrequency noise. The floating ground reference (GND1) is derived from the end of the shunt resistor, which is
connected to the negative input (INN) of the device. If a four-pin shunt is used, the device inputs are connected
to the inner leads, and GND1 is connected to one of the outer leads of the shunt.
To decouple the digital power supply on the controller side, use a 0.1-µF capacitor (C3) placed as close to the
VDD2 pin of the AMC1302 as possible, followed by an additional capacitor from 1 µF to 10 µF (C4).
R1
800
Gate Driver
Z1
1N751A
C2
2.2 F
AMC1302
5.1 V
GND1
RSHUNT
RFLT
INN
to Load
RFLT
VDD2
VDD1
C1
0.1 F
CFLT
INP
Reinforced Isolation
HV+
Floating
Power Supply
15 V
C3
0.1 F
C4
2.2 F
3.3 V or
5.0 V
GND2
OUTP
OUTN
ADS7263
14-Bit ADC
Gate Driver
HV-
Figure 56. Zener-Diode-Based, High-Side Power Supply
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10 Layout
10.1 Layout Guidelines
Figure 57 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1302 supply pins) and placement of the other components required by the device. For best
performance, place the shunt resistor close to the INP and INN inputs of the AMC1302 and keep the layout of
both connections symmetrical.
10.2 Layout Example
Clearance area,
to be kept free of any
conductive materials.
Shunt Resistor
To Floating
Power
Supply
RFLT
RFLT
SMD
0603
SMD
0603
2.2 µF
0.1 µF
0.1 µF
2.2 µF
SMD
0603
SMD
0603
SMD
0603
SMD
0603
CFLT
SMD
0603
VDD1
VDD2
INP
OUTP
To Filter
or ADC
AMC1302
INN
OUTN
GND1
GND2
LEGEND
Copper Pour and Traces
High-Side Area
Low-Side Area
Via to Ground Plane
Via to Supply Plane
Figure 57. Recommended Layout of the AMC1302
26
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Texas Instruments, Isolation Glossary application report
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 channel, simultaneous sampling analog-todigital converter data sheet
• Texas Instruments, Semiconductor and IC package thermal metrics application report
• Texas Instruments, ISO72x Digital isolator magnetic-field immunity application report
• Texas Instruments, AMC1311x High-impedance, 2-V input, reinforced isolated amplifier data sheet
• Texas Instruments, TLV600x Low-power, rail-to-rail in/out, 1-MHz operational amplifier for cost-sensitive
systems data sheet
• Texas Instruments, LM117, LM317-N Wide temperature three-pin adjustable regulator data sheet
• Texas Instruments, AMC130x Evaluation module user's guide
• Texas Instruments, 18-Bit, 1-MSPS data acquisition block (DAQ) optimized for lowest distortion and noise
user's guide
• Texas Instruments, 18-Bit, 1-MSPS data acquisition block (DAQ) optimized for lowest power user's guide
• Texas Instruments, SN6501 Transformer driver for isolated power supplies data sheet
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AMC1302DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
AMC1302
AMC1302DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
AMC1302
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2019
OTHER QUALIFIED VERSIONS OF AMC1302 :
• Automotive: AMC1302-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
AMC1302DWVR
Package Package Pins
Type Drawing
SOIC
DWV
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
12.05
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.15
3.3
16.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1302DWVR
SOIC
DWV
8
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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