Texas Instruments | ISO1042 Isolated CAN Transceiver With 70-V Bus Fault Protection and Flexible Data Rate (Rev. D) | Datasheet | Texas Instruments ISO1042 Isolated CAN Transceiver With 70-V Bus Fault Protection and Flexible Data Rate (Rev. D) Datasheet

Texas Instruments ISO1042 Isolated CAN Transceiver With 70-V Bus Fault Protection and Flexible Data Rate (Rev. D) Datasheet
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ISO1042
SLLSF09E – DECEMBER 2017 – REVISED JANUARY 2020
ISO1042 Isolated CAN Transceiver With 70-V Bus Fault Protection and Flexible Data Rate
1 Features
3 Description
•
The ISO1042 device is a galvanically-isolated
controller area network (CAN) transceiver that meets
the specifications of the ISO11898-2 (2016) standard.
The ISO1042 device offers ±70-V DC bus fault
protection and ±30-V common-mode voltage range.
The device supports up to 5-Mbps data rate in CAN
FD mode allowing much faster transfer of payload
compared to classic CAN. This device uses a silicon
dioxide (SiO2) insulation barrier with a withstand
voltage of 5000 VRMS and a working voltage of 1060
VRMS. Electromagnetic compatibility has been
significantly enhanced to enable system-level ESD,
EFT, surge, and emissions compliance. Used in
conjunction with isolated power supplies, the device
protects against high voltage, and prevents noise
currents from the bus from entering the local ground.
The ISO1042 device is available for both basic and
reinforced isolation (see Reinforced and Basic
Isolation Options). The ISO1042 device supports a
wide ambient temperature range of –40°C to +125°C.
The device is available in the SOIC-16 (DW) package
and a smaller SOIC-8 (DWV) package.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Meets the ISO 11898-2:2016 physical layer
standard
Supports classic CAN up to 1 Mbps and FD
(Flexible Data Rate) up to 5 Mbps
Low loop delay: 152 ns
Protection features
– DC bus fault protection voltage: ±70 V
– HBM ESD tolerance on bus pins: ±16 kV
– Driver Dominant Time Out (TXD DTO)
– Undervoltage protection on VCC1 and VCC2
Common-Mode Voltage Range: ±30 V
Ideal passive, high impedance bus terminals when
unpowered
High CMTI: 100 kV/µs
VCC1 voltage range: 1.71 V to 5.5 V
– Supports 1.8-V, 2.5-V, 3.3-V and 5.0-V logic
interface to the CAN controller
VCC2 Voltage Range: 4.5 V to 5.5 V
Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– Low emissions
Ambient Temperature Range: –40°C to +125°C
16-SOIC and 8-SOIC package options
Automotive version available: ISO1042-Q1
Safety-related certifications:
– 7071-VPK VIOTM and 1500-VPK VIORM
(Reinforced and Basic Options) per DIN VDE
V 0884-11:2017-01
– 5000-VRMS Isolation for 1 Minute per UL 1577
– IEC 60950-1, IEC 60601-1 and EN 61010-1
certifications
– CQC, TUV and CSA certifications
Device Information(1)
PART NUMBER
PACKAGE
ISO1042
BODY SIZE (NOM)
SOIC (8)
5.85 mm × 7.50 mm
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Reinforced and Basic Isolation Options
FEATURE
ISO1042x
ISO1042Bx
Protection Level
Reinforced
Basic
Surge Test Voltage
10000 VPK
6000 VPK
Isolation Rating
5000 VRMS
5000 VRMS
Working Voltage
1060 VRMS /
1500 VPK
1060 VRMS /
1500 VPK
Application Diagram
2 Applications
•
•
•
•
•
•
AC and servo drives
Solar inverters
PLC and DCS communication modules
Elevators and escalators
Industrial power supplies
Battery charging and management
VCC1
1
VDD
TXD
MCU
RXD
DGND
2
3
4
Digital
Ground
VCC1
TXD
VCC2
ISO1042
CANH
CANL
8
VCC2
7
6
CAN Bus
RXD
GND1
GND2
Galvanic
Isolation Barrier
5
ISO
Ground
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1042
SLLSF09E – DECEMBER 2017 – REVISED JANUARY 2020
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Transient Immunity.................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics - DC Specification........... 9
Switching Characteristics ...................................... 11
Insulation Characteristics Curves ......................... 12
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 15
7.1 Test Circuits ............................................................ 15
8
Detailed Description ............................................ 19
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
19
23
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
9.3 DeviceNet Application ............................................. 27
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2019) to Revision E
•
Changed new safety certification............................................................................................................................................ 1
Changes from Revision C (October 2018) to Revision D
•
2
Page
Increased the size of the GND2 plane and changed the NC pin to GND2 in the 16-DW Layout Example......................... 30
Changes from Original (December 2017) to Revision A
•
Page
Initial Release ........................................................................................................................................................................ 1
Changes from Revision A (May 2018) to Revision B
•
Page
Added ISO1042-Q1 link.......................................................................................................................................................... 1
Changes from Revision B (July 2018) to Revision C
•
Page
Page
Changed pin 10 from NC to GND2......................................................................................................................................... 3
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SLLSF09E – DECEMBER 2017 – REVISED JANUARY 2020
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
1
16
VCC2
GND1
2
15
GND2
TXD
3
14
NC
NC
4
13
CANH
RXD
5
12
CANL
NC
6
11
VCC2
NC
7
10
GND2
GND1
8
9
GND2
ISOLATION
VCC1
Not to scale
Pin Functions—16 Pins
PIN
NO.
NAME
I/O
DESCRIPTION
1
VCC1
—
Digital-side supply voltage, Side 1
2
GND1
—
Digital-side ground connection, Side 1
3
TXD
I
4
NC
—
Not connected
5
RXD
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
6
NC
—
Not connected
7
NC
—
Not connected
8
GND1
—
Digital-side ground connection, Side 1
GND2
—
Transceiver-side ground connection, Side 2
9
10
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
11
VCC2
—
Transceiver-side supply voltage, Side 2. Must be externally connected to pin 16.
12
CANL
I/O
Low-level CAN bus line
13
CANH
I/O
High-level CAN bus line
14
NC
—
Not connected
15
GND2
—
Transceiver-side ground connection, Side 2
16
VCC2
—
Transceiver-side supply voltage, Side 2. Must be externally connected to pin 11.
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ISO1042
SLLSF09E – DECEMBER 2017 – REVISED JANUARY 2020
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VCC1
1
TXD
2
RXD
3
GND1
4
ISOLATION
DWV Package
8-Pin SOIC
Top View
8
VCC2
7
CANH
6
CANL
5
GND2
Not to scale
Pin Functions—8 Pins
PIN
NO.
NAME
I/O
DESCRIPTION
1
VCC1
—
2
TXD
I
Digital-side supply voltage, Side 1
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
3
RXD
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
4
GND1
—
Digital-side ground connection, Side 1
5
GND2
—
Transceiver-side ground connection, Side 2
6
CANL
I/O
Low-level CAN bus line
7
CANH
I/O
High-level CAN bus line
8
VCC2
—
Transceiver-side supply voltage, Side 2
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VCC1
Supply voltage, side 1
-0.5
6
V
VCC2
Supply voltage, side 2
-0.5
6
V
VIO
Logic input and output voltage range (TXD and
RXD)
-0.5
(3)
V
IO
Output current on RXD pin
-15
15
mA
VBUS
Voltage on bus pins (CANH, CANL)
-70
70
V
VBUS_DIFF
Differential voltage on bus pins (CANH-CANL)
-70
70
V
TJ
Junction temperature
-40
150
℃
TSTG
Storage temperature
-65
150
℃
(1)
(2)
(3)
VCC1+0.5
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
All pins
(1)
CANH and CANL to GND2
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
(1)
VALUE
UNIT
±6000
V
±16000
V
All pins (2)
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Transient Immunity
PARAMETER
VPULSE
TEST CONDITIONS
ISO7637-2 Transients according to GIFT - ICT
CAN EMC test specification
VALUE
UNIT
Pulse 1; CAN bus terminals (CANH, CANL) to
GND2
-100
V
Pulse 2; CAN bus terminals (CANH, CANL) to
GND2
75
V
Pulse 3a; CAN bus terminals (CANH, CANL) to
GND2
-150
V
Pulse 3b; CAN bus terminals (CANH, CANL) to
GND2
100
V
6.4 Recommended Operating Conditions
VCC1
MIN
MAX
UNIT
Supply Voltage, Side 1, 1.8-V operation
1.71
1.89
V
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
V
2.25
5.5
VCC2
Supply Voltage, Side 2
4.5
5.5
V
TA
Operating ambient temperature
-40
125
°C
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6.5 Thermal Information
ISO1042
THERMAL METRIC (1)
DW (SOIC)
DWV (SOIC)
16 PINS
8 PINS
UNIT
RΘJA
Junction-to-ambient thermal resistance
69.9
100
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
31.8
40.8
°C/W
RΘJB
Junction-to-board thermal resistance
29.0
51.8
°C/W
ΨJT
Junction-to-top characterization parameter
13.2
16.8
°C/W
ΨJB
Junction-to-board characterization parameter
28.6
49.8
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
-
-
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Maximum power dissipation (both sides)
See Figure 17, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, A repetitive pattern on
TXD with 1 ms time period, 990 µs LOW
time, and 10 µs HIGH time.
385
mW
PD1
Maximum power dissipation (side-1)
See Figure 19, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, Input a 2-V pk-pk 2.5MHz 50% duty cycle differential square
wave on CANH-CANL
25
mW
PD2
Maximum power dissipation (side-2)
See Figure 17, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, A repetitive pattern on
TXD with 1 ms time period, 990 µs LOW
time, and 10 µs HIGH time.
360
mW
6
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6.7 Insulation Specifications
PARAMETER
SPECIFICATIONS
TEST CONDITIONS
DW-16
DWV-8
UNIT
IEC 60664-1
CLR
External clearance (1)
Side 1 to side 2 distance through air
>8
>8.5
mm
CPG
External Creepage (1)
Side 1 to side 2 distance across package
surface
>8
>8.5
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
>17
µm
CTI
Comparative tracking index
IEC 60112; UL 746A
>600
>600
V
Material Group
According to IEC 60664-1
I
I
Rated mains voltage ≤ 600 VRMS
I-IV
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I-III
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
1500
VPK
Maximum isolation working voltage
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
1060
1060
VRMS
DC voltage
1500
1500
VDC
Maximum transient isolation voltage
VTEST = VIOTM, t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
7071
7071
VPK
Maximum surge isolation voltage
ISO1042 (3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 10000 VPK
(qualification)
6250
6250
VPK
Maximum surge isolation voltage
ISO1042B (3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6000 VPK
(qualification)
4615
4615
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM,
tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup
1, Vini = VIOTM, tini = 60 s;
≤5
ISO1042: Vpd(m) = 1.6 × VIORM, tm = 10 s
ISO1042B: Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM,
tini = 1 s;
ISO1042: Vpd(m) = 1.875 × VIORM, tm = 1 s
ISO1042B: Vpd(m) = 1.5 × VIORM, tm = 1 s
≤5
≤5
VIO = 0.4 × sin (2 πft), f = 1 MHz
1
1
VIO = 500 V, TA = 25°C
> 1012
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 150°C
> 1011
> 1011
Overvoltage category
DIN VDE V 0884-11:2017-01 (2)
VIORM
VIOWM
VIOTM
VIOSM
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Insulation resistance, input to output (5)
RIO
pC
9
VIO = 500 V at TS = 150°C
pF
Ω
9
> 10
> 10
Pollution degree
2
2
Climatic category
40/125/
21
40/125/
21
5000
5000
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO , t = 60 s (qualification); VTEST =
1.2 × VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
ISO1042 is suitable for safe electrical insulation and ISO1042B is suitable for basic electrical insulation only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.8 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to
GB4943.1-2011
Certified according to EN
61010-1:2010/A1:2019,
EN 609501:2006/A2:2013 and EN
62368-1:2014
Maximum transient
isolation voltage,
7071 VPK;
Maximum repetitive peak
isolation voltage,
1500 VPK;
Maximum surge isolation
voltage,
ISO1042: 6250 VPK
(Reinforced)
ISO1042B: 4615 VPK
(Basic)
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2 and IEC
62368-1 2nd Ed., for
pollution degree 2,
material group I
ISO1042: 800 VRMS
reinforced isolation
ISO1042B: 1060 VRMS
Single protection,
basic isolation
5000 VRMS
---------------CSA 60601- 1:14 and IEC
60601-1 Ed. 3.1+A1,
ISO1042: 2 MOPP
(Means of Patient
Protection) 250 VRMS (354
VPK) maximum working
voltage
Reinforced insulation,
Altitude ≤ 5000 m, Tropical
Climate,
700 VRMS maximum working
voltage
EN 61010-1:2010
/A1:2019
ISO1042: 600 VRMS
reinforced isolation
ISO1042B: 1000 VRMS
basic isolation
---------------EN 609501:2006/A2:2013 and EN
62368-1:2014
ISO1042-: 800 VRMS
reinforced isolation
ISO1042B: 1060 VRMS
basic isolation
Certificates:
Reinforced: 40040142
Basic: 40047657
Master contract number:
220991
Certificate:
CQC15001121716 (DW-16)
CQC18001199096 (DWV-8)
Client ID number: 77311
Certified according to DIN
VDE V 0884-11:2017- 01
Certified according to IEC
60950-1, IEC 62368-1
and IEC 60601-1
Recognized under UL
1577 Component
Recognition Program
File number: E181974
6.9 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
DW-16 PACKAGE
RθJA = 69.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
IS
325
Safety input, output, or supply RθJA = 69.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
current
RθJA = 69.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1
496
RθJA = 69.9°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see Figure 1
946
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 69.9°C/W, TJ = 150°C, TA = 25°C, see Figure 3
650
mA
1788
mW
150
°C
DWV-8 PACKAGE
RθJA = 100°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2
227
IS
Safety input, output, or supply RθJA = 100°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2
current
RθJA = 100°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2
347
RθJA = 100°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see Figure 2
661
PS
Safety input, output, or total
power
TS
Maximum safety temperature
(1)
8
RθJA = 100°C/W, TJ = 150°C, TA = 25°C, see Figure 4
454
mA
1250
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.10 Electrical Characteristics - DC Specification
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1 =1.71 V to 1.89 V, TXD = 0 V, bus
dominant
2.3
3.5
mA
VCC1 = 2.25 V to 5.5 V, TXD = 0 V, bus
dominant
2.4
3.5
mA
VCC1 = 1.71 V to 1.89 V, TXD = VCC1,
bus recessive
1.2
2.1
mA
VCC1 = 2.25 V to 5.5 V, TXD = VCC1, bus
recessive
1.3
2.1
mA
TXD = 0 V, bus dominant, RL = 60 Ω
43
73.4
mA
TXD = VCC1, bus recessive, RL = 60 Ω
2.8
4.1
mA
1.7
V
SUPPLY CHARACTERISTICS
ICC1
Supply current Side 1
ICC2
Supply current Side 2
UVVCC1
Rising under voltage detection, Side 1
UVVCC1
Falling under voltage detection, Side 1
1.0
VHYS(UVC Hysterisis voltage on VCC1 undervoltage
lock-out
C1)
UVVCC2
Rising under voltage detection, side 2
UVVCC2
Falling under voltage detection, side 2
75
3.8
VHYS(UVC Hysterisis voltage on VCC2 undervoltage
lock-out
C2)
V
125
mV
4.2
4.45
V
4.0
4.25
V
200
mV
TXD TERMINAL
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input leakage current
TXD = VCC1
IIL
Low level input leakage current
TXD = 0V
Input capacitance
VIN = 0.4 x sin(2 x π x 1E+6 x t) + 2.5 V,
VCC1 = 5 V
CI
0.7×VCC1
V
0.3×VCC1
V
1
uA
-20
uA
3
pF
RXD TERMINAL
VOH VCC1
VOL
High level output voltage
Low level output voltage
See Figure 18, IO = -4 mA for 4.5 V ≤
VCC1 ≤ 5.5 V
-0.4
-0.2
V
See Figure 18, IO = -2 mA for 3.0 V ≤
VCC1 ≤ 3.6 V
-0.2
-0.07
V
See Figure 18, IO = -1 mA for 2.25 V ≤
VCC1 ≤ 2.75 V
-0.1
-0.04
V
See Figure 18, IO = -1 mA for 1.71 V ≤
VCC1 ≤ 1.89 V
-0.1
-0.045
V
See Figure 18, IO = 4 mA for 4.5 V ≤
VCC1 ≤ 5.5 V
0.2
0.4
V
See Figure 18, IO = 2 mA for 3.0 V ≤
VCC1 ≤ 3.6 V
0.07
0.2
V
See Figure 18, IO = 1 mA for 2.25 V ≤
VCC1 ≤ 2.75 V
0.035
0.1
V
See Figure 18, IO = 1 mA for 1.71 V ≤
VCC1 ≤ 1.89 V
0.04
0.1
V
DRIVER ELECTRICAL CHARACTERISTICS
Bus output voltage(Dominant), CANH
See Figure 15 and Figure 16, TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
2.75
4.5
V
Bus output voltage(Dominant), CANL
See Figure 15 and Figure 16, TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
0.5
2.25
V
Bus output voltage(recessive), CANH
and CANL
See Figure 15 and Figure 16, TXD =
VCC1, RL = open
2.0
3.0
V
VO(DOM)
VO(REC)
0.5 x
VCC2
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Electrical Characteristics - DC Specification (continued)
Over recommended operating conditions (unless otherwise noted)
PARAMETER
VOD(DOM)
VOD(REC)
VSYM_DC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential output voltage, CANH-CANL
(dominant)
See Figure 15 and Figure 16, TXD = 0
V, 45 Ω ≤ RL ≤ 50 Ω, CL = open
1.4
3.0
V
Differential output voltage, CANH-CANL
(dominant)
See Figure 15 and Figure 16, TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
1.5
3.0
V
Differential output voltage, CANH-CANL
(dominant)
See Figure 15 and Figure 16, TXD = 0
V, RL = 2240 Ω, CL = open
1.5
5.0
V
Differential output voltage, CANH-CANL
(recessive)
See Figure 15 and Figure 16, TXD =
VCC1, RL = 60 Ω, CL = open
-120.0
12.0
mV
Differential output voltage, CANH-CANL
(recessive)
See Figure 15 and Figure 16, TXD =
VCC1, RL = open, CL = open
-50.0
50.0
mV
DC Output symmetry (VCC2 - VO(CANH) VO(CANL))
See Figure 15 and Figure 16, RL = 60 Ω,
CL = open, TXD = VCC1 or 0 V
-400.0
400.0
mV
See Figure 23, VCANH = -5 V to 40 V,
CANL = open, TXD = 0 V
-100.0
ISO(SS_DO Short circuit current steady state output
current, dominant
M)
ISO(SS_RE Short circuit current steady state output
current, recessive
C)
mA
See Figure 23, VCANL = -5 V to 40 V,
CANH = open, TXD = 0 V
See Figure 23, -27 V ≤ VBUS ≤ 32 V,
VBUS = CANH = CANL, TXD = VCC1
100.0
mA
-5.0
5.0
mA
RECEIVER ELECTRICAL CHARACTERISTICS
Differential input threshold voltage
See Figure 18 and Table 1, |VCM| ≤ 20
V
500.0
900.0
Differential input threshold voltage
See Figure 18 and Table 1, 20 V ≤
|VCM| ≤ 30 V
400.0
1000.0
VHYS
Hysteresis voltage for differential input
threshold
See Figure 18 and Table 1
VCM
Input common mode range
See Figure 18 and Table 1
IOFF(LKG)
Power-off bus input leakage current
CANH = CANL = 5 V, VCC2 to GND via 0
Ω and 47 kΩ resistor
CI
Input capacitance to ground (CANH or
CANL)
TXD = VCC1
CID
Differential input capacitance (CANHCANL)
TXD = VCC1
RID
Differential input resistance
TXD = VCC1 ; -30 V ≤ VCM ≤ +30 V
RIN
Input resistance (CANH or CANL)
RIN(M)
Input resistance matching: (1 RIN(CANH)/RIN(CANL)) x 100%
VIT
mV
120
-30.0
30.0
V
4.8
uA
24.0
30
pF
12.0
15
pF
30.0
80.0
kΩ
TXD = VCC1 ; -30 V ≤ VCM ≤ +30 V
15.0
40.0
kΩ
VCANH = VCANL = 5 V
-2.0
2.0
%
THERMAL SHUTDOWN
TTSD
Thermal shutdown temperature
TTSD_HYS
Thermal shutdown hysteresis
170
℃
5
℃
T
10
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6.11 Switching Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤
VCC1 ≤ 1.89 V
70
125
198.0
ns
See Figure 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤
VCC1 ≤ 5.5 V
70
122
192.0
ns
See Figure 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤
1.89 V
70
155
215.0
ns
See Figure 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤
VCC1 ≤ 5.5 V
70
152
215.0
ns
300.0
µs
DEVICE SWITCHING CHARACTERISTICS
tPROP(LO
OP1)
tPROP(LO
OP2)
tUV_RE_E
Total loop delay, driver input TXD to
receiver RXD, recessive to dominant
Total loop delay, driver input TXD to
receiver RXD, dominant to recessive
Re-enable time after Undervoltage event
Time for device to return to normal
operation from VCC1 or VCC2 under
voltage event
Common mode transient immunity
VCM = 1200 VPK, See Figure 24
NABLE
CMTI
85
100
kV/µs
DRIVER SWITCHING CHARACTERISTICS
tpHR
Propagation delay time, HIGH TXD to
driver recessive
tpLD
Propagation delay time, LOW TXD to
driver dominant
tsk(p)
Pulse skew (|tpHR - tpLD|)
tR
Differential output signal rise time
tF
Differential output signal fall time
See Figure 17, RL = 60 Ω and CL = 100
pF; input rise/fall time (10% to 90%) on
TXD =1 ns
76
120
61
120
ns
14
45
45
VSYM
Output symmetry (dominant or
recessive) (VO(CANH) + VO(CANL)) / VCC2
See Figure 17 and Figure 31 , RTERM =
60 Ω, CSPLIT = 4.7 nF, CL = open, RL =
open, TXD = 250 kHz, 1 MHz
tTXD_DTO
Dominant time out
See Figure 22, RL = 60 Ω and CL = open
0.9
1.1
V/V
1.2
3.8
ms
75
130
ns
63
130
ns
RECEIVER SWITCHING CHARACTERISTICS
tpRH
Propagation delay time, bus recessive
input to RXD high output
tpDL
Propogation delay time, bus dominant
input to RXD low output
tR
Output signal rise time(RXD)
1.4
ns
tF
Output signal fall time(RXD)
1.8
ns
See Figure 19, CL(RXD) = 15 pF
FD TIMING PARAMETERS
Bit time on CAN bus output pins with
tBIT(TXD) = 500 ns
See Figure 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
435.0
530.0
ns
Bit time on CAN bus output pins with
tBIT(TXD) = 200 ns
See Figure 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
155.0
210.0
ns
See Figure 21, RL = 60 Ω, CL = 100 pF,
Bit time on RXD output pins with tBIT(TXD)
CL(RXD) = 15 pF; input rise/fall time (10%
= 500 ns
to 90%) on TXD =1 ns
400
550.0
ns
See Figure 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
120.0
220.0
ns
tBIT(BUS)
tBIT(RXD)
Bit time on RXD output pins with tBIT(TXD)
= 200 ns
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Switching Characteristics (continued)
Over recommended operating conditions (unless otherwise noted)
PARAMETER
∆tREC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 21, RL = 60 Ω, CL = 100 pF,
Receiver timing symmetry with tBIT(TXD) = CL(RXD) = 15 pF; input rise/fall time (10%
500 ns
to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD)
- tBIT(BUS)
-65.0
40.0
ns
See Figure 21, RL = 60 Ω, CL = 100 pF,
Receiver timing symmetry with tBIT(TXD) = CL(RXD) = 15 pF; input rise/fall time (10%
200 ns
to 90%) on TXD =1 ns; ΔtREC =
tBIT(RXD) - tBIT(BUS)
-45.0
15.0
ns
6.12 Insulation Characteristics Curves
700
1000
VCC1 =1.89 V
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
800
700
600
500
400
300
200
400
300
200
0
0
0
50
100
150
Ambient Temperature (qC)
0
200
50
D003
Figure 1. Thermal Derating Curve for Limiting Current per
VDE for DW-16 Package
100
150
Ambient Temperature (qC)
200
D001
Figure 2. Thermal Derating Curve for Limiting Current per
VDE for DWV-8 Package
1400
2000
1800
1200
1600
Safety Limiting Power (mW)
Safety Limiting Power (mW)
500
100
100
1400
1200
1000
800
600
400
1000
800
600
400
200
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
0
D004
Figure 3. Thermal Derating Curve for Limiting Power per
VDE for DW-16 Package
12
VCC1 = 1.89 V
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
600
Safety Limiting Current (mA)
Safety Limiting Current (mA)
900
50
100
150
Ambient Temperature (qC)
200
D002
Figure 4. Thermal Derating Curve for Limiting Power per
VDE for DWV-8 Package
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6.13 Typical Characteristics
50
45
40
30
ICC1 (mA)
ICC2 (mA)
35
25
20
Recessive
Dominant
500 kbps
1 Mbps
15
10
2 Mbps
5 Mbps
5
0
4.5
4.6
4.7
4.8
VCC1 = 5 V
Temp = 25°C
4.9
5
5.1
VCC2 (V)
5.2
RL = 60 Ω
5.3
5.4
2.3
2.25
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
5.5
VCC1=1.71 V
VCC1=1.8 V
VCC1=2.5 V
0
0.5
1
CL(RXD) = 15 pF
4
4.5
5
D002
RL = 60 Ω
CL(RXD) = 15 pF
Figure 6. ICC1 vs Datarate
3
40
2.75
35
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
2.5
ICC1 (mA)
30
ICC2 (mA)
2
2.5
3
3.5
Data Rate (Mbps)
VCC2 = 5 V
Temp = 25°C
45
25
20
Recessive
Dominant
500 kbps
15
10
1 Mbps
2 Mbps
5 Mbps
2.25
2
1.75
1.5
1.25
5
-40
-20
0
VCC1 = VCC2 = 5 V
20
40
60
80
Temperature (qC)
RL = 60 Ω
100
120
1
-60
140
-40
-20
0
20
40
60
Temperature (qC)
D003
CL(RXD) = 15 pF
VCC1 = VCC2 = 5 V
Temp = 25°C
Figure 7. ICC2 vs Ambient Temperature for Recessive,
Dominant and Different CAN Datarates
80
100
120
140
D004
RL = 60 Ω
CL(RXD) = 15 pF
Figure 8. : ICC1 vs Ambient Temperature for Recessive,
Dominant and Different CAN Datarates.
180
170
1.5
D001
Figure 5. ICC2 vs VCC2 for Recessive, Dominant and Different
CAN Datarates
0
-60
VCC1=3.3 V
VCC1=5 V
VCC1=5.5 V
3
tPROP(LOOP1)
tPROP(LOOP2)
2.5
VOD(DOM) (V)
Loop Delay (ns)
160
150
140
130
2
1.5
1
120
0.5
110
100
-60
-40
-20
VCC1 = VCC2 = 5 V
0
20
40
60
80
Temperature (qC)
RL = 60 Ω
100
120
140
0
-55
-35
-15
D005
CL(RXD) = 15 pF
Figure 9. Loop Delay vs Ambient Temperature
VCC = 5 V
CL = Open
5
25
45
65
Temperature (°C)
85
105
VCC1 = 5 V
125
D001
RL = 60 Ω
Figure 10. VOD(DOM) Over Temperature
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Typical Characteristics (continued)
3
VOD(DOM) (V)
2.5
2
1.5
1
0.5
0
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
VCC (V)
5.4
5.5
VCC1 = VCC2 = 5 V
CL(RXD) = 15 pF
RL = 60 Ω
CL = 100 pF
D002
VCC1 = 5 V
CL = Open
RL = 60 Ω
Temp = 25°C
Figure 12. Typical TXD, RXD, CANH and CANL Waveforms
at 1 Mbps
Figure 11. VOD(DOM) Over VCC
TXD = VCC1
RL = 60 Ω
VCC1 = VCC2 = 5 V
Figure 13. Glitch Free Power Up on VCC1 – CAN Bus
Remains Recessive
14
TXD = VCC1
RL = 60 Ω
VCC1 = VCC2 = 5 V
Figure 14. Glitch Free Power Up on VCC2 – CAN Bus
Remains Recessive
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7 Parameter Measurement Information
7.1 Test Circuits
IO(CANH)
CANH
II
0 or
Vcc 1
TXD
VOD
CANL
GND1
RL
VO(CANH) + VO(CANL )
2
IO(CANL )
GND2
VI
VOC
VO(CANL ) VO(CANH)
GND1
GND2
Figure 15. Driver Voltage, Current and Test Definitions
Dominant
VO (CANH)
» 3.5 V
Recessive
» 2.5 V
VO (CANL)
» 1.5 V
Figure 16. Bus Logic State Voltage Definitions
Vcc
VI
CANH
TXD
RL
VO
Vcc /2
0V
CL
CANL
VI
t PLH
t PHL
0.5V
10%
tr
A.
VO(D)
90%
0.9V
VO
(SEE NOTE A)
Vcc /2
tf
VO(R)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 17. Driver Test Circuit and Voltage Waveforms
CANH
VIC
=
VI(CANH) + VI(CANL)
2
RXD
VID
IO
CANL
VI(CANH)
VO
VI(CANL)
GND2
GND1
Figure 18. Receiver Voltage and Current Definitions
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Test Circuits (continued)
CANH
IO
3.5 V
RXD
V
I
2.4 V
2 V
CANL
1.5 V
t pHL
t pLH
VO
VI
(SEE NOTE A )
C L(RXD)
1 .5 V
V OH
90 %
0.7 Vcc 1
0.3 Vcc 1
V
O
10 %
GND 2
A.
V OL
tf
tr
GND 1
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 19. Receiver Test Circuit and Voltage Waveforms
Table 1. Receiver Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
-29.5 V
-30.5 V
1000 mV
L
RXD
30.5 V
29.5 V
1000 mV
L
-19.55 V
-20.45 V
900 mV
L
20.45 V
19.55 V
900 mV
L
-19.75 V
-20.25 V
500 mV
H
20.25 V
19.75 V
500 mV
H
-29.8 V
-30.2 V
400 mV
H
30.2 V
29.8 V
400 mV
H
Open
Open
X
H
VOL
VOH
CANH
VI
TXD
RL
CANL
CL
TXD Input
Vcc
50%
t loop2
VOH
RXD
RXD Output
+
50%
50%
VOL
C L(RXD)
VO
_
0V
t loop 1
GND1
Figure 20. tLOOP Test Circuit and Voltage Waveforms
16
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VI
70%
TXD
CANH
TXD
VI
0V
tBIT(TXD)
5 x tBIT
CL
RL
30%
30%
CANL
tBIT(BUS)
900 mV
VDIFF
RXD
500 mV
CL(RXD)
VO
VOH
GND1
70%
RXD
tBIT(RXD)
30%
VOL
Figure 21. CAN FD Timing Parameter Measurement
Vcc
VI
CANH
TXD
RL
0V
VOD
CL
V OD (D)
V I (see Note A )
CANH
VOD
900 mV
t TXD_DTO
500 mV
GND 1
A.
0V
The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 22. Dominant Time-out Test Circuit and Voltage Waveforms
IOS
CANH
200 s
IOS
TXD
VBUS
IOS
+
VBUS
CANL
VBUS
0V
±
GND2
or
0V
VBUS
VBUS
Figure 23. Driver Short-Circuit Current Test Circuit and Waveforms
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C = 0.1 mF
± 1%
VCC 1
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VCC 1
VCC2
CANH
C = 0.1 mF ±1%
+
GND1
GND2
TXD
60 W
S1
VOH or VOL
CANL
0V
RXD
VOH or VOL
1kW
GND 1
GND 2
CL = 15 pF
(includes probe and
jig capacitance )
V CM
Figure 24. Common-Mode Transient Immunity Test Circuit
18
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8 Detailed Description
8.1 Overview
The ISO1042 device is a digitally isolated CAN transceiver that offers ±70-V DC bus fault protection and ±30-V
common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much
faster transfer of payload compared to classic CAN. The ISO1042 device has an isolation withstand voltage of
5000 VRMS and is available in basic and reinforced isolation with a surge test voltage of 6 kVPK and 10 kVPK
respectively. The device can operate from 1.8-V, 2.5-V, 3.3-V, and 5-V supplies on side 1 and a 5-V supply on
side 2. This supply range is of particular advantage for applications operating in harsh industrial environments
because the low voltage on side 1 enables the connection to low-voltage microcontrollers for power
conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the bus signals.
8.2 Functional Block Diagram
VCC2
VCC1
TXD
+
GALVANIC ISOLATION
RXD
±
CANH
CANL
GND2
GND1
8.3 Feature Description
8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node uses the TXD pin to drive the bus and receives data from the
bus on the RXD pin. See Figure 25 and Figure 26.
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Feature Description (continued)
Typical Bus Voltage (V)
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time (t)
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Figure 25. Bus States (Physical Bit Representation)
GALVANIC
ISOLATION
CANH
VCC / 2
RXD
CANL
Figure 26. Simplified Recessive Common Mode Bias and Receiver
8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,
and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.
NOTE
The TXD pin is very weakly internally pulled up to VCC1. An external pullup resistor should
be used to make sure that the TXD pin is biased to recessive (high) level to avoid issues
on the bus if the microprocessor does not control the pin and the TXD pin floats. The TXD
pullup strength and CAN bit timing require special consideration when the device is used
with an open-drain TXD output on the CAN controller of the microprocessor. An adequate
external pullup resistor must be used to make sure that the TXD output of the
microprocessor maintains adequate bit timing input to the input on the transceiver.
20
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Feature Description (continued)
8.3.3 Protection Features
8.3.3.1 TXD Dominant Timeout (DTO)
The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware
or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit
timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge
occurs before the timeout period expires, which frees the bus for communication between other nodes on the
network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD
DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased
to the recessive level during a TXD dominant timeout.
TXD fault stuck dominant
Example: PCB failure or bad software
TXD
(driver)
tTXD_DTO
Fault is repaired and transmission
capability is restored
Driver disabled freeing bus for other nodes
Bus would be stuck dominant, blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the tTXD_DTO time.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
repaired nodes
Communication from
other bus nodes
RXD
(receiver)
Communication from
local node
Communication from
other bus nodes
Communication from
repaired nodes
Figure 27. Example Timing Diagram for TXD DTO
NOTE
The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the
minimum possible transmitted data rate of the device. The CAN protocol allows a
maximum of eleven successive dominant bits (on TXD) for the worst case, where five
successive dominant bits are followed immediately by an error frame. This, along with the
tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data
rate with Equation 1.
Minimum Data Rate = 11 / tTXD_DTO
(1)
8.3.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits, blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYST) below the thermal shutdown temperature (TTSD) of the device.
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Feature Description (continued)
8.3.3.3 Undervoltage Lockout and Default State
The supply pins have undervoltage detection that places the device in protected or default mode which protects
the bus during an undervoltage event on the VCC1 or VCC2 supply pins. If the bus-side power supply, VCC2, is less
than about 4 V, the power shutdown circuits in the ISO1042 device disable the transceiver to prevent false
transmissions because of an unstable supply. If the VCC1 supply is still active when this occurs, the receiver
output (RXD) goes to a default HIGH (recessive) value. Table 2 summarizes the undervoltage lockout and failsafe behavior.
Table 2. Undervoltage Lockout and Default State
VCC1
VCC2
DEVICE STATE
BUS OUTPUT
RXD
> UVVCC1
> UVVCC2
Functional
Per Device State and TXD
Mirrors Bus
<UVVCC1
> UVVCC2
Protected
Recessive
Undetermined
>UVVCC1
< UVVCC2
Protected
High Impedance
Recessive (Default High)
NOTE
After an undervoltage condition is cleared and the supplies have returned to valid levels,
the device typically resumes normal operation in 300 µs.
8.3.3.4 Floating Pins
Pullup and pulldown resistors should be used on critical pins to place the device into known states if the pins
float. The TXD pin should be pulled up through a resistor to the VCC1 pin to force a recessive input level if the
microprocessor output to the pin floats.
8.3.3.5 Unpowered Device
The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which
is critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
8.3.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit
fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the
second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant
state during a system fault. During CAN communication the bus switches between dominant and recessive
states, therefore the short circuit current may be viewed either as the instantaneous current during each bus
state or as an average current of the two states. For system current (power supply) and power considerations in
the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the
ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and
PHY that force either recessive or dominant at certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high
percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant
bits and their respective short circuit currents. Use Equation 2 to calculate the average short circuit current.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]
where
•
•
•
22
IOS(AVG) is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
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•
•
•
•
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short circuit current
IOS(SS)_DOM is the dominant steady state short circuit current
(2)
NOTE
Consider the short circuit current and possible fault cases of the network when sizing the
power ratings of the termination resistance and other network components.
8.4 Device Functional Modes
Table 3 and Table 4 list the driver and receiver functions. Table 5 lists the functional modes for the ISO1042
device.
Table 3. Driver Function Table
INPUT
(1)
OUTPUTS
DRIVEN BUS STATE
TXD (1)
CANH (1)
CANL (1)
L
H
L
Dominant
H
Z
Z
Recessive
H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See Figure 25 and
Figure 26 for bus state and common mode bias information.
Table 4. Receiver Function Table
DEVICE MODE
Normal
(1)
(2)
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL (1)
BUS STATE
RXD PIN (2)
L
VID ≥ VIT(MAX)
Dominant
VIT(MIN) < VID < VIT(MAX)
?
?
VID ≤ VIT(MIN)
Recessive
H
Open (VID ≈ 0 V)
Open
H
See Receiver Electrical Characteristics section for input thresholds.
H = high level, L = low level, ? = indeterminate.
Table 5. Function Table (1)
DRIVER
INPUTS
(1)
(2)
(3)
OUTPUTS
TXD
CANH
CANL
L (3)
H
L
H
Z
Z
Open
Z
Z
X
Z
Z
RECEIVER
DIFFERENTIAL INPUTS
VID = CANH–CANL (2)
OUTPUT
RXD
BUS STATE
DOMINANT
VID ≥ VIT(MAX)
L
DOMINANT
RECESSIVE
VIT(MIN) < VID < VIT(MAX)
?
?
RECESSIVE
VID ≤ VIT(MIN)
H
RECESSIVE
RECESSIVE
Open (VID ≈ 0 V)
H
RECESSIVE
BUS STATE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
See Receiver Electrical Characteristics section for input thresholds.
Logic low pulses to prevent dominant time-out.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO1042 device can be used with other components from Texas Instruments such as a microcontroller, a
transformer driver, and a linear voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
GND
4
D2
EN
VCC
CLK
D1
1
3
SN6505
3.3 V
8
3
2
7
6
1
5
2
1
2
VDD
TXD
RXD
3.3V
GND
TXD
TXD
CANH
CANH
Protective Chasis
Earth
Ground
Digital
Ground
4
RXD
RXD
CANL
13
12
Optional bus
protection
function
7 NC
NC
8
NC
NC 14
ISO1042
NC
6 NC
0V
5
11,16
DGND
N PSU
PE
5
VCC2
OUT
EN
TPS76350
GND1
GND1
4 NC
NC
MCU
L1
3
V
VCC1
CC1
IN
9,10,15
GND1
GND2
Galvanic
Isolation Barrier
ISO
Ground
Figure 28. Application Circuit With ISO1042 in 16-SOIC Package
24
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Typical Application (continued)
GND
EN
VCC
CLK
D1
1
3
SN6505
3.3 V
8
4
D2
3
2
7
6
1
5
2
3.3 V
1
VDD
TXD
MCU
RXD
DGND
2
3
4
Digital
Ground
VCC1
VCC2
TXD
CANH
ISO1042 CANL
OUT
5
EN
TPS76350
GND
NC
4
8
7
6
RXD
GND1
IN
Optional bus
protection
function
GND2
Galvanic
Isolation Barrier
5
ISO
Ground
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Application Circuit With ISO1042 in 8-SOIC Package
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1042 device only requires external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A large number of nodes requires transceivers with high input impedance such as the ISO1042 transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable
length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen,
DeviceNet, and NMEA2000.
The ISO1042 device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst case
including parallel transceivers. The differential input resistance of the ISO1042 device is a minimum of 30 kΩ. If
100 ISO1042 transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω differential load
worst case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading of 50 Ω.
Therefore, the ISO1042 device theoretically supports up to 100 transceivers on a single bus segment. However,
for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity, therefore a practical maximum number of nodes is
typically much lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by
careful system design and data-rate tradeoffs. For example, CANopen network design guidelines allow the
network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes, and a
significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the
responsibility of good network design and balancing these tradeoffs.
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Typical Application (continued)
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed
from the bus.
Node 1
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
Figure 30. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used.
(See Figure 31). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM / 2
CAN
Transceiver
RTERM
CAN
Transceiver
CSPLIT
RTERM / 2
CANL
CANL
Figure 31. CAN Bus Termination Concepts
26
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Typical Application (continued)
9.2.3 Application Curve
Figure 32. Typical TXD, RXD, CANH and CANL Waveforms at 1 Mbps
9.3 DeviceNet Application
VCC1
VCC1
ISO1211D
VDD
24 V
Sense
SENSE
OUT
IN
GND1
ISO1042
1
TXD
CANH
RXD
CANL
GND1
GND2
DGND
4
8
TPS7B82-Q1
VCC2 = 5 V
LDO
VOUT
Digital
Ground
24 V
VIN
GND
3
RXD
ISO
Ground
VCC2
VCC1
2
TXD
560
FGND
VCC1
MCU
2.25 k
VCC1
7
CANH
6
CANL
5
24RET
ISO Ground
VCC2 = 5V
BSS123
VCC1
VIN
VOUT
LDO
24 V
D2
GND
VCC
SN6505 EN
GND
D1
1:4
CLK
BSS123
Figure 33. ISO1042, ISO1211 and SN6505 Used in a DeviceNet Application
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DeviceNet Application (continued)
Figure 33 shows an application circuit for using ISO1042, ISO1211 and SN6505 in a DeviceNet application.
ISO1042 is used to isolate the CAN interface. The ISO1211 24-V digital input receiver is used to detect the
absence or presence of the 24-V field supply. The SN6505 push-pull transformer driver, is used to create an
auxiliary isolated power supply for the micro-controller side using the 24-V field supply.
10 Power Supply Recommendations
To make sure operation is reliable at all data rates and supply voltages, a 0.1-µF bypass capacitor is
recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to
the supply pins as possible. In addition, a bulk capacitance, typically 4.7 μF, should be placed near the VCC2
supply pin. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6505B. For such
applications, detailed power supply design, and transformer selection recommendations are available in the
SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.
28
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Suggested placement and routing of ISO1042 bypass capacitors and optional TVS diodes is shown in Figure 35
and Figure 36. In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as
possible, and complete the connection to the VCC2 and GND2 pins without using vias. Note that the SOIC-16
variant needs two VCC2 bypass capacitor, one on each VCC2 pin.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over lowercost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater
strength and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this space
free from planes,
traces, pads, and
vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 34. Recommended Layer Stack
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Layout Example (continued)
Minimize
distance to
VCC
VCC1
0.1 µF
GND1
TXD
NC
MCU
RXD
x
NC
NC
GND1
GND1
Isolation Capacitor
x
0.1 µF
VCC2
VCC1
C
C
GND2
NC
C1
CANH
CANL
VCC2
D1
0.1 µF
CAN
BUS
C2
C
GND2
GND2
PLANE
GND1
GND2
PLANE
PLANE
VCC2
Figure 35. 16-DW Layout Example
Minimize
distance to VCC
C
VCC1
TXD
RXD
MCU
GND1
GND1
PLANE
C
VCC2
Isolation
Capacitor
VCC1
VCC2
C1
CANH
D1
CANL
CAN
BUS
C2
GND2
GND2
PLANE
Figure 36. 8-DWV Layout Example
30
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, ISO1042DW Isolated CAN Transceiver Evaluation Module User's Guide
• Texas Instruments, Isolate your CAN systems without compromising on performance or space TI TechNote
• Texas Instruments, Isolation Glossary
• Texas Instruments, High-voltage reinforced isolation: Definitions and test methodologies
• Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
• Texas Instruments, How to Design Isolated CAN Systems With Correct Bus Protection Application Report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO1042BDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042B
ISO1042BDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042B
ISO1042BDWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042B
ISO1042BDWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042B
ISO1042DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042
ISO1042DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042
ISO1042DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042
ISO1042DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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OTHER QUALIFIED VERSIONS OF ISO1042 :
• Automotive: ISO1042-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ISO1042BDWR
SOIC
DW
ISO1042BDWVR
SOIC
ISO1042DWR
SOIC
ISO1042DWVR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO1042BDWR
SOIC
DW
16
2000
350.0
350.0
43.0
ISO1042BDWVR
SOIC
DWV
8
1000
350.0
350.0
43.0
ISO1042DWR
SOIC
DW
16
2000
350.0
350.0
43.0
ISO1042DWVR
SOIC
DWV
8
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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