Texas Instruments | ISO7731B High-Speed, Basic Insulation Triple-Channel Digital Isolator (Rev. A) | Datasheet | Texas Instruments ISO7731B High-Speed, Basic Insulation Triple-Channel Digital Isolator (Rev. A) Datasheet

Texas Instruments ISO7731B High-Speed, Basic Insulation Triple-Channel Digital Isolator (Rev. A) Datasheet
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ISO7731B
SLLSF65A – APRIL 2018 – REVISED JANUARY 2019
ISO7731B High-Speed, Basic Insulation Triple-Channel Digital Isolator
1 Features
3 Description
•
•
The ISO7731B device is a high-performance, triplechannel digital isolator with 5000 VRMS isolation
ratings per UL 1577 and 8000 VPK basic insulation
according to VDE.
1
•
•
•
•
•
•
•
•
•
100 Mbps Data Rate
Robust Isolation Barrier:
– >100-Year Projected Lifetime at 1 kVRMS
Working Voltage
– Up to 5000 VRMS Isolation Rating
– ±100 kV/μs Typical CMTI
Wide Supply Range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level Translation
Default Output High (ISO7731B) and Low
(ISO7731FB) Options
Wide Temperature Range: –55°C to +125°C
Low Power Consumption, Typical 1.7 mA per
Channel at 1 Mbps
Low Propagation Delay: 11 ns Typical
(5-V Supplies)
Robust Electromagnetic Compatibility (EMC)
– System-Level ESD, EFT, and Surge Immunity
– ±8 kV IEC 61000-4-2 Contact Discharge
Protection across Isolation Barrier
– Low Emissions
Wide-SOIC (DW-16) Package
Safety-Related Certifications:
– Basic Insulation per DIN V VDE V 088411:2017-01
– UL 1577 Component Recognition Program
– CSA Certification per IEC 60950-1 and IEC
62368-1 End Equipment Standards
– CQC Certification per GB4943.1-2011
– TUV Certification according to EN 60950-1 and
EN 61010-1
– CQC Certification Planned; All Other
Certifications Complete
The ISO7731B device provides high electromagnetic
immunity and low emissions at low power
consumption, while isolating CMOS or LVCMOS
digital I/Os. Each isolation channel has a logic input
and output buffer separated by a double capacitive
silicon dioxide (SiO2) insulation barrier. This device
comes with enable pins which can be used to put the
respective outputs in high impedance for multi-master
driving applications and to reduce power
consumption. The ISO7731B device has two forward
and one reverse-direction channels. If the input power
or signal is lost, the default output is high for device
without suffix F and low for device with suffix F. See
the Device Functional Modes section for further
details.
Used in conjunction with isolated power supplies, this
device helps prevent noise currents on data buses,
such as RS-485, RS-232, and CAN, or other circuits
from entering the local ground and interfering with or
damaging sensitive circuitry. Through innovative chip
design and layout techniques, electromagnetic
compatibility of the ISO7731B device has been
significantly enhanced to ease system-level ESD,
EFT, surge, and emissions compliance. The
ISO7731B device is available in 16-pin wide-SOIC
package.
Device Information(1)
PART NUMBER
ISO7731B
PACKAGE
SOIC (16)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
•
•
•
•
Industrial Automation
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input VCC, VCCO=Output VCC
GNDI=Input ground, GNDO=Output ground
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7731B
SLLSF65A – APRIL 2018 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics—5-V Supply ..................... 8
Supply Current Characteristics—5-V Supply .......... 8
Electrical Characteristics—3.3-V Supply ................ 9
Supply Current Characteristics—3.3-V Supply ....... 9
Electrical Characteristics—2.5-V Supply .............. 10
Supply Current Characteristics—2.5-V Supply ..... 10
Switching Characteristics—5-V Supply................. 11
Switching Characteristics—3.3-V Supply.............. 11
Switching Characteristics—2.5-V Supply.............. 12
Insulation Characteristics Curves ......................... 12
6.19 Typical Characteristics .......................................... 13
7
8
Parameter Measurement Information ................ 14
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
18
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
13.1 Package Option Addendum .................................. 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2018) to Revision A
Page
•
Made editorial and cosmetic changes throughout the document ........................................................................................... 1
•
Changed From: "Isolation Barrier Life: >40 Years" To:">100-Year Projected Lifetime at 1 kVRMS Working Voltage" in
Features.................................................................................................................................................................................. 1
•
Added "Up to 5000 VRMS Isolation Rating" in Features ......................................................................................................... 1
•
Added "±8 kV IEC 61000-4-2 Contact Discharge Protection across Isolation Barrier" in Features....................................... 1
•
Changed From: "All Certifications are Planned" To: "CQC Certification Planned; All Other Certifications Complete" in
Features.................................................................................................................................................................................. 1
•
Changed Simplified Schematic to show two isolation capacitors in series instead of a single capacitor .............................. 1
•
Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in ESD Ratings table ........................................... 4
•
Added table note to Data rate specification in Recommended Operating Conditions table ................................................. 4
•
Updated certification information in Safety-Related Certifications table................................................................................. 7
•
Deleted "EN" from Figure 12 ............................................................................................................................................... 15
•
Updated Figure 15 by fixing ground symbols of "Input (Devices with F suffix)" schematic.................................................. 19
•
Added "How to use isolation to improve ESD, EFT and Surge immunity in industrial systems" application report in
Related Documentation section............................................................................................................................................ 24
2
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SLLSF65A – APRIL 2018 – REVISED JANUARY 2019
5 Pin Configuration and Functions
ISO7731B DW Package
16-Pin SOIC
Top View
1
16 VCC2
GND1 2
15 GND2
INA
3
INB
4
14 OUTA
ISOLATION
VCC1
OUTC 5
13 OUTB
12
INC
NC
6
11
NC
EN1
7
10
EN2
GND1 8
9 GND2
Pin Functions
PIN NAME
PIN NO.
I/O
DESCRIPTION
EN1
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in
high-impedance state when EN1 is low.
EN2
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in
high-impedance state when EN2 is low.
GND1
2, 8
—
Ground connection for VCC1
GND2
9, 15
—
Ground connection for VCC2
INA
3
I
Input, channel A
INB
4
I
Input, channel B
INC
12
I
Input, channel C
NC
6, 11
—
Not connected
OUTA
14
O
Output, channel A
OUTB
13
O
Output, channel B
OUTC
5
O
Output, channel C
VCC1
1
—
Power supply, VCC1
VCC2
16
—
Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
MIN
MAX
UNIT
VCC1, VCC2
Supply voltage (2)
–0.5
6
V
V
Voltage at INx, OUTx, ENx
–0.5
VCCX + 0.5 (3)
V
IO
Output current
–15
15
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
(3) (4)
±8000
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test
(1)
(2)
(3)
(4)
UNIT
±6000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
V
2
2.25
V
VCC1, VCC2
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO–)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
High-level output current
IOL
Low-level output current
2.25
UNIT
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
mA
VIH
High-level input voltage
0.7 × VCCI (1)
VCCI
VIL
Low-level input voltage
0
0.3 × VCCI
DR (2)
Data rate
0
100
Mbps
TA
Ambient temperature
125
°C
(1)
(2)
4
–55
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
100 Mbps is the maximum specified data rate, although higher data rates are possible.
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6.4 Thermal Information
ISO7731B
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
81.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
44.9
°C/W
RθJB
Junction-to-board thermal resistance
45.9
°C/W
ψJT
Junction-to-top characterization parameter
28.1
°C/W
ψJB
Junction-to-board characterization parameter
45.5
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
150
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
50
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
100
mW
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6.6 Insulation Specifications
VALUE
UNIT
External clearance
PARAMETER
(1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage
(1)
Shortest terminal-to-terminal distance across the package
surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
μm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
V
CLR
TEST CONDITIONS
Material group
I
Overvoltage category per IEC 60664-1
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
Rated mains voltage ≤ 600 VRMS
I–IV
Rated mains voltage ≤ 1000 VRMS
I–III
AC voltage (bipolar)
1414
VPK
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test
1000
VRMS
DC voltage
1414
VDC
VTEST = VIOTM = 8000 VPK, t = 60 s (qualification);
VTEST = 1.2 × VIOTM= 9600 VPK, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
6000
VPK
DIN V VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage
VIOWM Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage
qpd
Apparent charge
(3)
(4)
Barrier capacitance, input to output (5)
CIO
Isolation resistance (5)
RIO
Method a, After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1697 VPK, tm = 10 s
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1697 VPK, tm = 10 s
≤5
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM= 9600 VPK, tini = 1 s;
Vpd(m) = 1.5 × VIORM = 2121 VPK, tm = 1 s
≤5
VIO = 0.4 sin (2πft), f = 1 MHz
~0.7
VIO = 500 V, TA = 25°C
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500 V at TS = 150°C
>109
Pollution degree
2
Climatic category
55/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstanding isolation voltage
VTEST = VISO = 5000 VRMS , t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
Certified according to DIN
V VDE V 0884-11:2017-01 Certified according to IEC
and DIN EN 61010-1 (VDE 60950-1 and IEC 62368-1
0411-1):2011-07
UL
CQC
TUV
Recognized under UL 1577
Component Recognition
Program
Plan to certify according to GB
4943.1-2011
Certified according to EN
61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A2:2013
5000 VRMS insulation per EN
61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS
5000 VRMS insulation per EN
60950-1:2006/A2:2013 up to
working voltage of 800 VRMS
Client ID number: 77311
Basic Insulation;
Maximum transient
isolation voltage, 8000
VPK;
Maximum repetitive peak
isolation voltage, 1414
VPK;
Maximum surge isolation
voltage, 6000 VPK
Basic Insulation;
800 VRMS working voltage per
CSA 60950-1-07+A1+A2, IEC
60950-1 2nd Ed. +A1+A2, CSA
62368-1-14 and IEC 623681:2014
Single protection, 5000 VRMS
700 VRMS maximum working
voltage, Altitude ≤ 5000 m,
Tropical Climate
Certificate number:
40047657
Master contract number:
220991
File number: E181974
Certification planned
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
Safety input, output, or
supply current (1)
TEST CONDITIONS
TYP
MAX
279
RθJA = 81.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
427
RθJA = 81.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1
558
PS
Safety input, output, or total
RθJA = 81.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 2
power (1)
TS
Maximum safety
temperature (1)
(1)
MIN
RθJA = 81.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
UNIT
mA
1536
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
4.8
MAX
UNIT
VOH
High-level output voltage
IOH = –4 mA; see Figure 9
VOL
Low-level output voltage
IOL = 4 mA; see Figure 9
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 × VCCI
0.2 × VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
|CMH|
High-level common-mode
transient immunity
VI = VCCI (2), VCM = 1200 V; see Figure 12
85
100
kV/μs
|CML|
Low-level common-mode
transient immunity
VI = 0 V, VCM = 1200 V; see Figure 12
85
100
kV/μs
CI
Input Capacitance
VI = VCC (2) / 2 + 0.4 × sin(2πft), f = 1 MHz, VCC = 5
V
(1)
(2)
V
0.2
0.4
V
0.6 × VCCI
0.7 × VCCI
V
10
–10
μA
μA
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
UNIT
0.8
1.2
mA
ICC2
0.7
1
mA
EN1 = EN2 = 0 V; VI = 0 V (ISO7731B);
VI = VCCI (ISO7731B with F suffix)
ICC1
3
4.3
mA
ICC2
1.8
2.6
mA
EN1 = EN2 = VCCI; VI = VCCI (ISO7731B);
VI = 0 V (ISO7731B with F suffix)
ICC1
1.3
1.7
mA
ICC2
1.6
2.2
mA
EN1 = EN2 = VCCI; VI = 0 V (ISO7731B);
VI = VCCI (ISO7731B with F suffix)
ICC1
3.5
5
mA
ICC2
2.8
4.1
mA
ICC1
2.7
3.4
mA
ICC2
2.3
3.3
mA
ICC1
3
4
mA
ICC2
3.3
4.4
mA
ICC1
8.5
11
mA
ICC2
13.1
16
mA
1 Mbps
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
8
MAX
ICC1
Supply current - DC signal
(1)
TYP
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731B);
VI = 0 V (ISO7731B with F suffix)
Supply current - disable
Supply current - AC signal
MIN
VCCI = Input-side VCC
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
MAX
UNIT
VOH
High-level output voltage
IOH = –2 mA; see Figure 9
VOL
Low-level output voltage
IOL = 2 mA; see Figure 9
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
|CMH|
High-level common-mode
transient immunity
VI = VCCI (1), VCM = 1200 V; see Figure 12
85
100
kV/μs
|CML|
Low-level common-mode
transient immunity
VI = 0 V, VCM = 1200 V; see Figure 12
85
100
kV/μs
(1)
V
0.1
0.3
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
μA
–10
μA
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MAX
UNIT
ICC1
0.8
1.2
mA
ICC2
0.7
1
mA
EN1 = EN2 = 0 V; VI = 0 V (ISO7731B);
VI = VCCI (ISO7731B with F suffix)
ICC1
3
4.3
mA
ICC2
1.8
2.6
mA
EN1 = EN2 = VCCI; VI = VCCI (ISO7731B);
VI = 0 V (ISO7731B with F suffix)
ICC1
1.3
1.7
mA
ICC2
1.6
2.2
mA
EN1 = EN2 = VCCI; VI = 0 V (ISO7731B);
VI = VCCI (ISO7731B with F suffix)
ICC1
3.5
5
mA
ICC2
2.8
4.1
mA
ICC1
2.4
3.4
mA
ICC2
2.2
3.3
mA
ICC1
2.8
3.8
mA
ICC2
2.9
4
mA
ICC1
6.7
8.5
mA
ICC2
10
12.5
mA
Supply current - DC signal
1 Mbps
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
TYP
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731B);
VI = 0 V (ISO7731B with F suffix)
Supply current - disable
Supply current - AC signal
MIN
VCCI = Input-side VCC
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
MAX
UNIT
VOH
High-level output voltage
IOH = –1 mA; see Figure 9
VOL
Low-level output voltage
IOL = 1 mA; see Figure 9
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
|CMH|
High-level common-mode transient
immunity
VI = VCCI (1), VCM = 1200 V; see Figure 12
85
100
kV/μs
|CML|
Low-level common-mode transient
immunity
VI = 0 V, VCM = 1200 V; see Figure 12
85
100
kV/μs
(1)
V
0.05
0.2
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
–10
μA
μA
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
UNIT
0.8
1.2
mA
ICC2
0.7
1
mA
EN1 = EN2 = 0 V; VI = 0 V (ISO7731B);
VI = VCCI (ISO7731B with F suffix)
ICC1
3
4.3
mA
ICC2
1.8
2.6
mA
EN1 = EN2 = VCCI; VI = VCCI (ISO7731B);
VI = 0 V (ISO7731B with F suffix)
ICC1
1.3
1.7
mA
ICC2
1.6
2.2
mA
EN1 = EN2 = VCCI; VI = 0 V (ISO7731B);
VI = VCCI (ISO7731B with F suffix)
ICC1
3.5
5
mA
ICC2
2.8
4.1
mA
ICC1
2.4
3.4
mA
ICC2
2.2
3.2
mA
ICC1
2.7
3.7
mA
ICC2
2.7
3.8
mA
ICC1
5.6
7
mA
ICC2
8
10
mA
1 Mbps
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
10
MAX
ICC1
Supply current - DC signal
(1)
TYP
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731B);
VI = 0 V (ISO7731B with F suffix)
Supply current - disable
Supply current - AC signal
MIN
VCCI = Input-side VCC
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
(3)
TYP
6
MAX
UNIT
16
ns
0.6
4.9
ns
4
ns
4.5
ns
1.3
3.9
ns
1.4
3.9
ns
Disable propagation delay, high-to-high impedance output
8
20
ns
Disable propagation delay, low-to-high impedance output
8
20
ns
Enable propagation delay, high impedance-to-high output for
ISO7731B
7
20
ns
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7731B
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7731B with F suffix
7
20
ns
0.1
0.3
μs
See Figure 9
Same-direction channels
See Figure 9
See Figure 10
Measured from the time VCC
goes below 1.7 V. See Figure 11
Default output delay time from input power loss
tie
MIN
11
Enable propagation delay, high impedance-to-high output for
ISO7731B with F suffix
tPZL
(1)
(2)
TEST CONDITIONS
16
Time interval error
2
0.6
– 1 PRBS data at 100 Mbps
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
11
16
ns
0.1
5
ns
4.1
ns
4.5
ns
1.3
3
ns
1.3
3
ns
Disable propagation delay, high-to-high impedance output
17
30
ns
Disable propagation delay, low-to-high impedance output
17
30
ns
Enable propagation delay, high impedance-to-high output for
ISO7731B
17
30
ns
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7731B
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7731B with F suffix
17
30
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
TEST CONDITIONS
See Figure 9
Same-direction channels
See Figure 9
Enable propagation delay, high impedance-to-high output for
ISO7731B with F suffix
Default output delay time from input power loss
Time interval error
See Figure 10
Measured from the time VCC
goes below 1.7 V. See Figure 11
16
2
– 1 PRBS data at 100 Mbps
0.6
UNIT
ns
Also known as Pulse Skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
(1)
(2)
(3)
MAX
UNIT
18.5
ns
0.2
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
Disable propagation delay, high-to-high impedance output
22
40
ns
Disable propagation delay, low-to-high impedance output
22
40
ns
Enable propagation delay, high impedance-to-high output for
ISO7731B
18
40
ns
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7731B
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO7731B with F suffix
18
40
ns
0.1
0.3
μs
See Figure 9
Same-direction Channels
See Figure 9
See Figure 10
Measured from the time VCC goes
below 1.7 V. See Figure 11
Default output delay time from input power loss
tie
7.5
TYP
12
Enable propagation delay, high impedance-to-high output for
ISO7731B with F suffix
tPZL
MIN
16
Time interval error
2
– 1 PRBS data at 100 Mbps
0.6
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.18 Insulation Characteristics Curves
1800
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
1600
Safety Limiting Power (mW)
Safety Limiting Current (mA)
600
400
300
200
100
1400
1200
1000
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
Figure 1. Thermal Derating Curve for Safety Limiting
Current per VDE
12
0
D001
50
100
150
Ambient Temperature (qC)
200
D003
Figure 2. Thermal Derating Curve for Safety Limiting Power
per VDE
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6.19 Typical Characteristics
6
14
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
10
5
Supply Current (mA)
Supply Current (mA)
12
8
6
4
4
3
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
2
1
2
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
25
D007
CL = 15 pF
50
Data Rate (Mbps)
TA = 25°C
Figure 3. ISO7731B Supply Current vs Data Rate
(With 15-pF Load)
75
100
D008
CL = No Load
Figure 4. ISO7731B Supply Current vs Data Rate
(With No Load)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
5
10
Low-Level Output Current (mA)
D011
15
D012
TA = 25°C
TA = 25°C
Figure 5. High-Level Output Voltage vs High-level
Output Current
Figure 6. Low-Level Output Voltage vs Low-Level
Output Current
2.10
14
2.05
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
0.7
2.00
1.95
1.90
1.85
1.80
1.75
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
1.70
1.65
1.60
-55 -40 -25 -10
5 20 35 50 65 80
Free-Air Temperature (qC)
13
12
11
10
9
tPLH at 2.5 V
tPHL at 2.5 V
95 110 125
8
-55
D009
Figure 7. Power Supply Undervoltage Threshold vs
Free-Air Temperature
-25
tPLH at 3.3 V
tPHL at 3.3 V
5
35
65
Free-Air Temperature (qC)
tPLH at 5 V
tPHL at 5 V
95
125
D010
Figure 8. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
VO
50
tPHL
CL
See Note B
VO
VOH
90%
50%
50%
10%
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
IN
0V
VO
VI
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
tPZH
RL = 1 k
±1%
VOH
VO
50%
0.5 V
tPHZ
50
0V
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Enable/Disable Propagation Delay Time Test Circuit and Waveform
14
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Parameter Measurement Information (continued)
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 11. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
Isolation Barrier
S1
C = 0.1 µF ±1%
IN
OUT
+
VOH or VOL
CL
See Note A
GNDI
A.
+
VCM ±
±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7731B device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is low
then the output goes to high impedance. The ISO7731B device also incorporates advanced circuit techniques to
maximize the CMTI performance and minimize the radiated emissions because of the high frequency carrier and
IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 13, shows a functional
block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 14 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 14. On-Off Keying (OOK) Based Modulation Scheme
16
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8.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
(1)
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT OUTPUT
ISOLATION RATING (1)
ISO7731B
2 Forward,
1 Reverse
100 Mbps
High
5000 VRMS / 8000 VPK
ISO7731B with F
suffix
2 Forward,
1 Reverse
100 Mbps
Low
5000 VRMS / 8000 VPK
See Safety-Related Certifications for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7731B
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7731B device.
Table 2. Function Table (1)
VCCI
PU
X
(1)
(2)
(3)
18
VCCO
INPUT
(INx) (2)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
A low value of Output Enable causes the outputs to be high-impedance
PU
PU
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output goes
to its default logic state. Default is High for ISO7731B and Low for
ISO7731B with F suffix.
PD
PU
X
H or open
Default
Default mode: When VCCI is unpowered, a channel output assumes the
logic state based on the selected default option. Default is High for
IISO7731B and Low for ISO7731B with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
X
PD
X
X
Undetermined
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
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8.4.1 Device I/O Schematics
Input (Devices without F suffix)
VCCI
VCCI VCCI
Input (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
Enable
VCCO
VCCO
VCCO
VCCO
VCCO
2M
~20
1970
OUTx
ENx
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7731B device is a high-performance, triple-channel digital isolator. This device comes with enable pins
on each side which can be used to put the respective outputs in high impedance for multi-master driving
applications and reduce power consumption. The ISO7731B device uses single-ended CMOS-logic switching
technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with
digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform
to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal
lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a
line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7731B device, combined with Texas Instruments' mixed-signal microcontroller, RS-485 transceiver,
transformer driver, and voltage regulator, can create an isolated RS-485 system as shown in Figure 16.
VIN
3.3V
0.1 F
2
Vcc D2 3
1:2.2 MBR0520L
1
SN6501
GND D1
3
1
10 F
OUT
5
TPS76350
10 F 0.1 F
4,5
IN
EN
GND
2
5VISO
10 F
MBR0520L
ISO-BARRIER
0.1 F
0.1 F
0.1 F
DVcc
6
P3.0
XOUT
XIN
16
1
2
5
0.1 F
11
MSP430 UCA0TXD 15
F2132
16
UCA0RXD
DVss
3
4
5
VCC1
VCC2
INA
OUTA
ISO7731
INB
OUTC
7 EN1
4
GND1
2,8
OUTB
INC
VCC
14
13
12
EN2 10
GND2
2
3
4
1
RE
DE
10 MELF
B
D
SN65HVD
3082E A
R
GND
10 MELF
SM712
9,15
4.7nF/
2kV
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Isolated RS-485 Interface Circuit
20
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Typical Application (continued)
9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7731B device only requires two external bypass capacitors to operate. Figure 17 shows the typical circuit
hook-up for the device.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
6
11
7
10
8
9
GND1
GND2
NC
NC
EN2
EN1
GND2
GND1
Figure 17. Typical ISO7731B Circuit Hook-Up
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9.2.3 Application Curves
Ch4 = 1 V / div
Ch4 = 1 V / div
The following typical eye diagrams of the ISO7731B device indicates low jitter and wide open eye at the
maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
Figure 19. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
and 25°C
Ch4 = 500 mV / div
Figure 18. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and
25°C
Time = 2.5 ns / div
Figure 20. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505A. For such applications, detailed power supply design and transformer selection recommendations are
available in the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505A Low-Noise 1-A
Transformer Drivers for Isolated Power Supplies data sheet.
22
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 21. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies
• Texas Instruments, SNx5HVD308xE Low-Power RS-485 Transceivers, Available in a Small MSOP-8
Package
• Texas Instruments, TPS76350 Low-Power 150-mA Low-Dropout Linear Regulators
• Texas Instruments, MSP430F2132 Mixed Signal Microcontroller
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ISO7731B
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www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
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EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
28
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13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
ISO7731BDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
ISO7731B
ISO7731BDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
ISO7731B
ISO7731FBDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
ISO7731FB
ISO7731FBDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
ISO7731FB
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
30
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
ISO7731BDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7731FBDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7731BDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7731FBDWR
SOIC
DW
16
2000
367.0
367.0
38.0
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PACKAGE OPTION ADDENDUM
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13-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7731BDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7731B
ISO7731BDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7731B
ISO7731FBDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7731FB
ISO7731FBDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7731FB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Feb-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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