Texas Instruments | ISO773x-Q1 High-Speed, Robust-EMC Reinforced Triple-Channel Digital Isolators (Rev. B) | Datasheet | Texas Instruments ISO773x-Q1 High-Speed, Robust-EMC Reinforced Triple-Channel Digital Isolators (Rev. B) Datasheet

Texas Instruments ISO773x-Q1 High-Speed, Robust-EMC Reinforced Triple-Channel Digital Isolators (Rev. B) Datasheet
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ISO7730-Q1, ISO7731-Q1
SLLSEU3B – NOVEMBER 2016 – REVISED SEPTEMBER 2018
ISO773x-Q1 High-Speed, Robust-EMC Reinforced Triple-Channel Digital Isolators
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level Translation
Default Output High and Low Options
Low Power Consumption, Typical 1.5 mA per
Channel at 1 Mbps
Low Propagation Delay: 11 ns Typical
(5-V Supplies)
High CMTI: ±100 kV/μs Typical
Robust Electromagnetic Compatibility (EMC)
– System-Level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: >40 Years
Wide-SOIC (DW-16) and QSOP (DBQ-16)
Package Options
Safety-Related Certifications:
– Reinforced Insulation per DIN V VDE V 088411:2017-01
– 5000 VRMS (DW) and 2500 VRMS (DBQ)
Isolation Rating per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
– TUV Certification according to EN 60950-1 and
EN 61010-1
– All Certifications Complete except CQC
Approval of DBQ-16 Package Devices
2 Applications
•
•
•
•
•
Hybrid Electric Vehicles
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
3 Description
This family of devices has reinforced insulation
ratings according to VDE, CSA, TUV and CQC.
The ISO773x-Q1 family of devices provides high
electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by a silicon
dioxide (SiO2) insulation barrier. This device comes
with enable pins which can be used to put the
respective outputs in high impedance for multi-master
driving applications and to reduce power
consumption. The ISO7730-Q1 device has all three
channels in the same direction and the ISO7731-Q1
device has two forward and one reverse-direction
channel. If the input power or signal is lost, the
default output is high for devices without suffix F and
low for devices with suffix F. See the Device
Functional Modes section for further details.
Used in conjunction with isolated power supplies, this
device helps prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, electromagnetic compatibility of the
ISO773x-Q1 device has been significantly enhanced
to ease system-level ESD, EFT, surge, and
emissions compliance. The ISO773x-Q1 family of
devices is available in 16-pin wide-SOIC and QSOP
packages.
Device Information(1)
PART NUMBER
ISO7730-Q1
ISO7731-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (DW)
10.30 mm × 7.50 mm
SSOP (DBQ)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections, respectively, for the input
channels.
VCCO and GNDO are supply and ground
connections, respectively, for the output
channels.
The ISO773x-Q1 devices are high-performance,
triple-channel digital isolators with 5000 VRMS (DW
package) and 3000 VRMS (DBQ package) isolation
ratings per UL 1577.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7730-Q1, ISO7731-Q1
SLLSEU3B – NOVEMBER 2016 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics—5-V Supply ..................... 8
Supply Current Characteristics—5-V Supply .......... 8
Electrical Characteristics—3.3-V Supply ................ 9
Supply Current Characteristics—3.3-V Supply ....... 9
Electrical Characteristics—2.5-V Supply .............. 10
Supply Current Characteristics—2.5-V Supply ..... 10
Switching Characteristics—5-V Supply................. 11
Switching Characteristics—3.3-V Supply.............. 12
Switching Characteristics—2.5-V Supply.............. 12
Insulation Characteristics Curves ......................... 13
6.19 Typical Characteristics .......................................... 14
7
8
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
20
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2017) to Revision B
Page
•
Changed the DIN certification number and certification status throughout the document .................................................... 1
•
Changed the isolation rating of the DBQ package from 2500 VRMS to 3000 VRMS ................................................................ 1
•
Moved the HBM and CDM values from the Features section to the ESD Ratings table ....................................................... 4
•
Added VTEST to the conditions for the maximum transient isolation voltage parameter in the Insulation Specifications
table ........................................................................................................................................................................................ 6
•
Changed the value for the DBQ package from 3600 VPK to 4242 VPK throughout the document........................................ 6
•
Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table ........................................ 6
Changes from Original (November 2016) to Revision A
Page
•
Updated the Safety-Related Certifications table..................................................................................................................... 7
•
Changed the minimum CMTI from 40 to 85 in all Electrical Characteristics tables .............................................................. 8
2
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SLLSEU3B – NOVEMBER 2016 – REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
ISO7730-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
ISO7731-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
1
16 VCC2
VCC1
1
16 VCC2
GND1 2
15 GND2
GND1 2
15 GND2
3
INB
4
INC
5
NC
6
11
NC
NC
NC
7
10
EN2
EN1
ISOLATION
INA
14 OUTA
INA
3
13 OUTB
INB
4
12 OUTC
GND1 8
OUTC 5
9 GND2
14 OUTA
ISOLATION
VCC1
13 OUTB
12
INC
6
11
NC
7
10
EN2
GND1 8
9 GND2
Pin Functions
PIN
I/O
DESCRIPTION
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or
open and in high-impedance state when EN1 is low.
10
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or
open and in high-impedance state when EN2 is low.
GND1
2, 8
2, 8
—
Ground connection for VCC1
GND2
Ground connection for VCC2
NAME
NO.
ISO7730-Q1
ISO7731-Q1
EN1
—
EN2
9, 15
9, 15
—
INA
3
3
I
Input, channel A
INB
4
4
I
Input, channel B
INC
5
12
I
Input, channel C
NC
6, 7, 11
6, 11
—
Not connected
OUTA
14
14
O
Output, channel A
OUTB
13
13
O
Output, channel B
OUTC
12
5
O
Output, channel C
VCC1
1
1
—
Power supply, VCC1
VCC2
16
16
—
Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
MIN
MAX
UNIT
VCC1, VCC2
Supply voltage (2)
–0.5
6
V
V
Voltage at INx, OUTx, ENx
–0.5
VCCX + 0.5 (3)
V
IO
Output current
–15
15
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 3A
±6000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
V
2
2.25
V
VCC1, VCC2
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO–)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
IOL
High-level output current
Low-level output current
2.25
UNIT
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
mA
VIH
High-level input voltage
0.7 × VCCI (1)
VCCI
VIL
Low-level input voltage
0
0.3 × VCCI
DR
Data rate
0
100
Mbps
TA
Ambient temperature
125
°C
(1)
4
-40
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.4 Thermal Information
ISO773x-Q1
THERMAL METRIC (1)
DW (SOIC)
DBQ (QSOP)
16 Pins
16 Pins
UNIT
RθJA
Junction-to-ambient thermal resistance
81.4
109
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
44.9
46.8
°C/W
RθJB
Junction-to-board thermal resistance
45.9
60.6
°C/W
ψJT
Junction-to-top characterization parameter
28.1
35.9
°C/W
ψJB
Junction-to-board characterization parameter
45.5
60
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
150
mW
25
mW
125
mW
150
mW
50
mW
100
mW
ISO7730-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
ISO7731-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
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6.6 Insulation Specifications
PARAMETER
CLR
External clearance
SPECIFICATION
TEST CONDITIONS
DW-16
DBQ-16
UNIT
(1)
Shortest terminal-to-terminal distance through air
>8
>3.7
mm
(1)
Shortest terminal-to-terminal distance across the
package surface
>8
>3.7
mm
CPG
External creepage
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
μm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
>600
>600
V
Material group
According to IEC 60664-1
Overvoltage category per IEC 60664-1
I
I
Rated mains voltage ≤ 150 VRMS
I–IV
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Rated mains voltage ≤ 600 VRMS
I–IV
n/a
Rated mains voltage ≤ 1000 VRMS
I–III
n/a
AC voltage (bipolar)
1414
566
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
1000
400
VRMS
DC Voltage
1414
566
VDC
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 × VIOTM,
t = 1 s (100% production)
8000
4242
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
4000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
'DIN V VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage
(3)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Isolation resistance (5)
RIO
pC
≤5
VIO = 0.4 x sin (2πft), f = 1 MHz
~0.7
~0.7
VIO = 500 V, TA = 25°C
>1012
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
VIO = 500 V at TS = 150°C
>109
>109
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5000
3000
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
All certifications complete except CQC approval of DBQ-16 package devices
VDE
Certified according to 'DIN
V VDE V 0884-11:2017-01
CSA
UL
Certified according to CSA
Component Acceptance Notice
5A, IEC 60950-1 and IEC
60601-1
Certified according to UL 1577
Component Recognition
Program
CQC
TUV
Certified according to EN
61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11
:2009/A1:2010/A12:2011/A2
:2013
Certified according to GB
4943.1-2011
Maximum transient
isolation voltage, 8000 VPK
(DW-16) and 4242 VPK
(DBQ-16);
Maximum repetitive peak
isolation voltage, 1414 VPK
(DW-16, Reinforced) and
566 VPK (DBQ-16);
Maximum surge isolation
voltage, 8000 VPK (DW-16)
and 4000 VPK (DBQ-16)
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.,
800 VRMS (DW-16) and 370
VRMS (DBQ-16) max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (DW-16) max working
voltage
DW-16: Single protection, 5000
VRMS;
DBQ-16: Single protection,
3000 VRMS
DW-16: Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 400 VRMS maximum
working voltage;
DBQ-16: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS maximum
working voltage
Certificate number:
40040142
Master contract number:
220991
File number: E181974
Certificate number:
CQC15001121716
5000 VRMS (DW-16) and
3000 VRMS (DBQ-16)
Reinforced insulation per EN
61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS
(DW-16) and 300 VRMS
(DBQ-16)
5000 VRMS (DW-16) and
3000 VRMS (DBQ-16)
Reinforced insulation per EN
609501:2006/A11:2009/A1:2010/A
12:2011/A2:2013 up to
working voltage of 800 VRMS
(DW -16) and 370 VRMS
(DBQ-16)
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-16 PACKAGE
IS
Safety input, output, or
supply current
RθJA = 81.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
279
RθJA = 81.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
427
RθJA = 81.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1
558
PS
Safety input, output, or total
RθJA = 81.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 3
power
TS
Maximum safety
temperature
mA
1536
mW
150
°C
DBQ-16 PACKAGE
RθJA = 109.0°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2
209
RθJA = 109.0 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2
319
RθJA = 109.0°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2
417
IS
Safety input, output, or
supply current
PS
Safety input, output, or total
RθJA = 109.0°C/W, TJ = 150°C, TA = 25°C, see Figure 4
power
TS
Maximum safety
temperature
(1)
mA
1147
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-toair thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-toair thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded surface mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature
plus the power times the junction-to-air thermal resistance.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
4.8
MAX
UNIT
VOH
High-level output voltage
IOH = –4 mA; see Figure 13
VOL
Low-level output voltage
IOL = 4 mA; see Figure 13
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 × VCCI
0.2 × VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 16
CI
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
(1)
(2)
V
0.2
0.4
V
0.6 × VCCI
0.7 × VCCI
V
10
–10
85
μA
μA
100
kV/μs
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7730-Q1
EN2 = 0 V; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
ICC1
1
1.4
mA
ICC2
0.3
0.4
mA
EN2 = 0 V; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
ICC1
4.3
6
mA
ICC2
0.3
0.4
mA
EN2 = VCC2; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
ICC1
1
1.4
mA
ICC2
1.6
2.5
mA
EN2 = VCC2; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
ICC1
4.3
6
mA
ICC2
1.8
2.7
mA
ICC1
2.6
3.7
mA
ICC2
1.9
2.8
mA
ICC1
2.7
3.8
mA
ICC2
3.3
4.5
mA
ICC1
3.6
4.6
mA
ICC2
17.5
21
mA
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
0.8
1.2
mA
ICC2
0.7
1
mA
EN1 = EN2 = 0 V; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
ICC1
3
4.3
mA
ICC2
1.8
2.6
mA
EN1 = EN2 = VCCI; VI = VCCI (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
1.3
1.7
mA
ICC2
1.6
2.2
mA
EN1 = EN2 = VCCI; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
ICC1
3.5
5
mA
ICC2
2.8
4.1
mA
ICC1
2.7
3.4
mA
ICC2
2.3
3.3
mA
ICC1
3
4
mA
ICC2
3.3
4.4
mA
ICC1
8.5
11
mA
ICC2
13.1
16
mA
Supply current - disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
EN2 = VCCI; All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
ISO7731-Q1
Supply current - disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
8
VCCI = Input-side VCC
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 13
VOL
Low-level output voltage
IOL = 2 mA; see Figure 13
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 16
(1)
MAX
UNIT
V
0.1
0.3
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
μA
–10
85
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7730-Q1
EN2 = 0 V; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
ICC1
1
1.4
mA
ICC2
0.3
0.4
mA
EN2 = 0 V; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
ICC1
4.3
6
mA
ICC2
0.3
0.4
mA
EN2 = VCC2; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
ICC1
1
1.4
mA
ICC2
1.6
2.5
mA
EN2 = VCC2; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
ICC1
4.3
6
mA
ICC2
1.8
2.7
mA
ICC1
2.6
3.7
mA
ICC2
1.8
2.8
mA
ICC1
2.7
3.8
mA
ICC2
2.8
3.9
mA
ICC1
3.3
4.3
mA
ICC2
13
17
mA
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
0.8
1.2
mA
ICC2
0.7
1
mA
EN1 = EN2 = 0 V; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
ICC1
3
4.3
mA
ICC2
1.8
2.6
mA
EN1 = EN2 = VCCI; VI = VCCI (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
1.3
1.7
mA
ICC2
1.6
2.2
mA
EN1 = EN2 = VCCI; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
ICC1
3.5
5
mA
ICC2
2.8
4.1
mA
ICC1
2.4
3.4
mA
ICC2
2.2
3.3
mA
ICC1
2.8
3.8
mA
ICC2
2.9
4
mA
ICC1
6.7
8.5
mA
ICC2
10
12.5
mA
Supply current - disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
EN2 = VCCI; All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
ISO7731-Q1
Supply current - disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
VCCI = Input-side VCC
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 13
VOL
Low-level output voltage
IOL = 1 mA; see Figure 13
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 16
(1)
MAX
V
0.05
0.2
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
–10
85
UNIT
μA
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7730-Q1
EN2 = 0 V; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
ICC1
1
1.4
mA
ICC2
0.3
0.4
mA
EN2 = 0 V; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
ICC1
4.3
6
mA
ICC2
0.3
0.4
mA
EN2 = VCC2; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
ICC1
1
1.4
mA
ICC2
1.6
2.5
mA
EN2 = VCC2; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
ICC1
4.3
6
mA
ICC2
1.8
2.7
mA
ICC1
2.6
3.7
mA
ICC2
1.8
2.7
mA
ICC1
2.6
3.8
mA
ICC2
2.5
3.6
mA
ICC1
3.1
4.2
mA
ICC2
10.2
14
mA
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
0.8
1.2
mA
ICC2
0.7
1
mA
EN1 = EN2 = 0 V; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
ICC1
3
4.3
mA
ICC2
1.8
2.6
mA
EN1 = EN2 = VCCI; VI = VCCI (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
1.3
1.7
mA
ICC2
1.6
2.2
mA
EN1 = EN2 = VCCI; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
ICC1
3.5
5
mA
ICC2
2.8
4.1
mA
ICC1
2.4
3.4
mA
ICC2
2.2
3.2
mA
ICC1
2.7
3.7
mA
ICC2
2.7
3.8
mA
ICC1
5.6
7
mA
ICC2
8
10
mA
Supply current - disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
EN2 = VCC2; All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
ISO7731-Q1
Supply current - disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
10
VCCI = Input-side VCC
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SLLSEU3B – NOVEMBER 2016 – REVISED SEPTEMBER 2018
6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
MIN
TYP
6
MAX
UNIT
11
16
ns
0.6
4.9
ns
4
ns
4.5
ns
1.3
3.9
ns
1.4
3.9
ns
Disable propagation delay, high-to-high impedance output
8
20
ns
Disable propagation delay, low-to-high impedance output
8
20
ns
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1
7
20
ns
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1 with F suffix
7
20
ns
0.1
0.3
μs
See Figure 13
Same-direction channels
See Figure 13
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1 with F suffix
Default output delay time from input power loss
See Figure 14
Measured from the time VCC
goes below 1.7 V. See Figure 15
16
Time interval error
2
– 1 PRBS data at 100 Mbps
0.6
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6
11
16
ns
0.1
5
ns
4.1
ns
4.5
ns
1.3
3
ns
1.3
3
ns
Disable propagation delay, high-to-high impedance output
17
30
ns
Disable propagation delay, low-to-high impedance output
17
30
ns
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1
17
30
ns
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1 with F suffix
17
30
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
Default output delay time from input power loss
tie
(3)
Same-direction channels
See Figure 13
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1 with F suffix
tPZL
(1)
(2)
See Figure 13
See Figure 14
Measured from the time VCC
goes below 1.7 V. See Figure 15
16
Time interval error
2
0.6
– 1 PRBS data at 100 Mbps
UNIT
ns
Also known as Pulse Skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
12
MIN
TYP
MAX
UNIT
12
18.5
ns
0.2
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
Disable propagation delay, high-to-high impedance output
22
40
ns
Disable propagation delay, low-to-high impedance output
22
40
ns
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1
18
40
ns
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1 with F suffix
18
40
ns
0.1
0.3
μs
See Figure 13
Same-direction Channels
See Figure 13
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1 with F suffix
Default output delay time from input power loss
Time interval error
7.5
See Figure 14
Measured from the time VCC goes
below 1.7 V. See Figure 15
16
2
– 1 PRBS data at 100 Mbps
0.6
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SLLSEU3B – NOVEMBER 2016 – REVISED SEPTEMBER 2018
6.18 Insulation Characteristics Curves
450
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
Safety Limiting Current (mA)
Safety Limiting Current (mA)
600
400
300
200
100
350
300
250
200
150
100
50
0
0
0
50
100
150
Ambient Temperature (qC)
0
200
Figure 1. Thermal Derating Curve for Safety Limiting
Current per VDE for DW-16 Package
100
150
Ambient Temperature (qC)
200
D002
Figure 2. Thermal Derating Curve for Safety Limiting
Current per VDE for DBQ-16 Package
1800
1400
1600
1200
Safety Limiting Power (mW)
Safety Limiting Power (mW)
50
D001
1400
1200
1000
800
600
400
1000
800
600
400
200
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
0
50
D003
Figure 3. Thermal Derating Curve for Safety Limiting Power
per VDE for DW-16 Package
100
150
Ambient Temperature (qC)
200
D004
Figure 4. Thermal Derating Curve for Safety Limiting Power
per VDE for DBQ-16 Package
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6.19 Typical Characteristics
7
20
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
Supply Current (mA)
16
14
12
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
6
Supply Current (mA)
18
10
8
6
4
5
4
3
2
2
1
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
1
100
CL = 15 pF
TA = 25°C
Figure 5. ISO7730-Q1 Supply Current vs Data Rate
(With 15-pF Load)
51
Data Rate (Mbps)
76
100
D006
CL = No Load
Figure 6. ISO7730-Q1 Supply Current vs Data Rate
(With No Load)
6
14
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
10
5
Supply Current (mA)
12
Supply Current (mA)
26
D005
8
6
4
4
3
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
2
1
2
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
25
D007
CL = 15 pF
TA = 25°C
Figure 7. ISO7731-Q1 Supply Current vs Data Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D008
CL = No Load
Figure 8. ISO7731-Q1 Supply Current vs Data Rate
(With No Load)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
5
10
Low-Level Output Current (mA)
15
D012
TA = 25°C
Figure 9. High-Level Output Voltage vs High-level
Output Current
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0
D011
TA = 25°C
14
0.7
Figure 10. Low-Level Output Voltage vs Low-Level
Output Current
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Typical Characteristics (continued)
14
2.05
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
2.10
2.00
1.95
1.90
1.85
1.80
1.75
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
1.70
1.65
1.60
-55 -40 -25 -10
5 20 35 50 65 80
Free-Air Temperature (qC)
13
12
11
10
9
tPLH at 2.5 V
tPHL at 2.5 V
95 110 125
8
-55
-25
D009
Figure 11. Power Supply Undervoltage Threshold vs
Free-Air Temperature
tPLH at 3.3 V
tPHL at 3.3 V
5
35
65
Free-Air Temperature (qC)
tPLH at 5 V
tPHL at 5 V
95
125
D010
Figure 12. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
VO
50
tPHL
CL
See Note B
VO
VOH
90%
50%
50%
10%
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
IN
0V
VO
VI
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
tPZH
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
RL = 1 k
±1%
VOH
50%
VO
0.5 V
tPHZ
50
0V
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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Parameter Measurement Information (continued)
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 15. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
S1
Isolation Barrier
C = 0.1 µF ±1%
IN
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
OUT
+
EN
CL
See Note A
GNDI
A.
+
VCM ±
VOH or VOL
±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO773x-Q1 family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is
low then the output goes to high impedance. The ISO773x-Q1 family of devices also incorporates advanced
circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high
frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 17,
shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 18 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 18. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT OUTPUT
ISO7730-Q1
3 Forward,
0 Reverse
100 Mbps
High
ISO7730-Q1 with F
suffix
3 Forward,
0 Reverse
100 Mbps
Low
ISO7731-Q1
2 Forward,
1 Reverse
100 Mbps
High
ISO7731-Q1 with F
suffix
(1)
2 Forward,
1 Reverse
100 Mbps
Low
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
See Safety-Related Certifications for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO773xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO773x-Q1 devices.
Table 2. Function Table (1)
VCCI
VCCO
PU
(2)
(3)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
A low value of Output Enable causes the outputs to be high-impedance
PU
X
(1)
INPUT
(INx) (2)
PU
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output goes
to its default logic state. Default is High for ISO773x-Q1 and Low for
ISO773x-Q1 with F suffix.
PD
PU
X
H or open
Default
Default mode: When VCCI is unpowered, a channel output assumes the
logic state based on the selected default option. Default is High for
IISO773x-Q1 and Low for ISO773x-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
X
PD
X
X
Undetermined
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
VCCI
VCCI
VCCI
Input (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
Enable
VCCO
VCCO
VCCO
VCCO
VCCO
2M
~20
1970
OUTx
ENx
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO773x-Q1 devices are high-performance, triple-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi-master driving
applications and reduce power consumption. The ISO773x-Q1 family of devices use single-ended CMOS-logic
switching technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When
designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators
do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL
digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data
converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7731-Q1 device combined with Texas Instruments' Piccolo™ microcontroller, analog-to-digital receiver,
transformer driver, and voltage regulator can create an isolated serial peripheral interface (SPI) as shown in
Figure 20.
VS
3.3 V
0.1 µF
2
VCC D2 3
MBR0520L
1:1.33
4
OUT
1
3.3VISO
TPS76333-Q1
SN6501-Q1
GND D1
IN
3
1
10 µF
0.1 µF
EN
GND
2
10 µF
MBR0520L
4, 5
2
1 µF
VIN
VOUT
6
REF5025A-Q1
10 µF
4
22 µF
GND
ISO Barrier
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1
4.7 k
29, 57
7
VDDIO
TMS320F28035PAGQ
SPICLKA
SPISIMOA
SPISOMIA
VCC1
EN1
16
VCC2
EN2
6 NC
NC
ISO7731-Q1
3
INA
OUTA
4
OUTB
INB
5
OUTC
INC
33
36
34
VSS
GND1
6, 28
2, 8
4.7 k
8
10
7
36
5
4
AINP MXO +VBD +VA REFP
11
14
32
CS
13
33
12
34
CH0
SCLK
28
16 Analog
Inputs
ADS7953-Q1
SDI
SDO
GND2
9, 15
CH15
BDGND
27
AGND
1, 22
11
REFM
30
Copyright © 2016, Texas Instruments Incorporated
Multiple pins and discrete components are omitted for clarity.
Figure 20. Isolated SPI for an Analog Input Module With 16 Inputs and a Single Slave
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Typical Application (continued)
9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO773x-Q1 family of devices only requires two external bypass capacitors to operate. Figure 21 and
Figure 22 show the typical circuit hook-up for the devices.
2 mm maximum
from VCC1
2 mm maximum
from VCC2
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
6
11
7
10
8
9
GND1
GND2
NC
NC
EN
NC
GND2
GND1
Figure 21. Typical ISO7730-Q1 Circuit Hook-Up
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2 mm maximum
from VCC2
2 mm maximum
from VCC1
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
6
11
7
10
8
9
GND1
GND2
NC
NC
EN2
EN1
GND2
GND1
Figure 22. Typical ISO7731-Q1 Circuit Hook-Up
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9.2.3 Application Curves
Ch4 = 1 V / div
Ch4 = 1 V / div
The following typical eye diagrams of the ISO773x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
Figure 24. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
and 25°C
Ch4 = 500 mV / div
Figure 23. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and
25°C
Time = 2.5 ns / div
Figure 25. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
the SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 26). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 26. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, REF50xxA-Q1 Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
• Texas Instruments, TMS320F28035 Piccolo™ Microcontrollers data sheet
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7730-Q1
Click here
Click here
Click here
Click here
Click here
ISO7731-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2018, Texas Instruments Incorporated
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
16X .008-.012
[0.21-0.30]
.150-.157
[3.81-3.98]
NOTE 4
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[ 0.11 -0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
32
Submit Documentation Feedback
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: ISO7730-Q1 ISO7731-Q1
ISO7730-Q1, ISO7731-Q1
www.ti.com
SLLSEU3B – NOVEMBER 2016 – REVISED SEPTEMBER 2018
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: ISO7730-Q1 ISO7731-Q1
Submit Documentation Feedback
33
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7730FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7730FQ
ISO7730FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7730FQ
ISO7730FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7730FQ
ISO7730FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7730FQ
ISO7730QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7730Q
ISO7730QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7730Q
ISO7730QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7730Q
ISO7730QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7730Q
ISO7731FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7731FQ
ISO7731FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7731FQ
ISO7731FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7731FQ
ISO7731FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7731FQ
ISO7731QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7731Q
ISO7731QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7731Q
ISO7731QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7731Q
ISO7731QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7731Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2018
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7730-Q1, ISO7731-Q1 :
• Catalog: ISO7730, ISO7731
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO7730FQDBQRQ1
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7730FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7730QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7730QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7731FQDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7731FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7731QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7731QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7730FQDBQRQ1
SSOP
DBQ
16
2500
350.0
350.0
43.0
ISO7730FQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7730QDBQRQ1
SSOP
DBQ
16
2500
350.0
350.0
43.0
ISO7730QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7731FQDBQRQ1
SSOP
DBQ
16
2500
350.0
350.0
43.0
ISO7731FQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7731QDBQRQ1
SSOP
DBQ
16
2500
350.0
350.0
43.0
ISO7731QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
.150-.157
[3.81-3.98]
NOTE 4
16X .008-.012
[0.21-0.30]
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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